Capacitor structure

Abstract

A capacitor structure includes at least two first bottom metal vias vertically above a substrate; a first bottom metal layer above and in contact with the first bottom metal vias; and a deep trench capacitor above the first bottom metal layer. The deep trench capacitor includes a bottom electrode above and in contact with a top surface of the first bottom metal layer; a top electrode above the bottom electrode; and a dielectric layer between the bottom electrode and the top electrode. The bottom electrode laterally bounds a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer. The first bottom metal layer laterally bounds a second region larger than and laterally covering the first region.

Description

Technical Field

[0001] This disclosure relates to a capacitor structure. Background Technology

[0002] Different types of capacitors, such as metal-insulator-metal (MIM) capacitors, are widely used in data manipulation and data storage applications. Deep trench MIM capacitors can be used to reduce their size. However, deep trench MIM capacitors may encounter similar reliability issues. Therefore, an improved deep trench MIM capacitor structure is needed. Utility Model Content

[0003] Some embodiments disclosed herein provide a capacitor structure including: at least two first bottom metal vias, a first bottom metal layer, a deep trench, and a capacitor. The at least two first bottom metal vias are vertically disposed above a substrate. The first bottom metal layer is disposed above and in contact with these first bottom metal vias. The deep trench is disposed above the first bottom metal layer. The capacitor is formed within the deep trench and includes: a bottom electrode above and in contact with the top surface of the first bottom metal layer, a top electrode above the bottom electrode, and a dielectric layer disposed between the bottom electrode and the top electrode. The bottom electrode laterally defines a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer, and the first bottom metal layer laterally defines a second region larger than the first region and laterally covering the first region.

[0004] Some embodiments disclosed herein provide a capacitor structure including: at least two first bottom metal vias, a first bottom metal layer, and a deep trench capacitor. The at least two first bottom metal vias are disposed above a substrate. The first bottom metal layer is disposed above and in contact with these first bottom metal vias. The deep trench capacitor is formed above the first bottom metal layer and includes a bottom electrode, a dielectric layer, and a top electrode. The bottom electrode includes a bottom portion in contact with the top surface of the first bottom metal layer and a vertical portion. The dielectric layer includes a bottom portion in contact with the bottom portion of the bottom electrode and a vertical portion in contact with the vertical portion of the bottom electrode. The top electrode contacts the bottom portion and the vertical portion of the dielectric layer. The bottom electrode of the capacitor laterally defines a first region having a first rectangular shape, and the first bottom metal layer laterally defines a second region larger than and laterally covering the first region.

[0005] Some embodiments disclosed herein provide a capacitor structure including: at least two first bottom metal vias, a first bottom metal layer, a deep trench, a capacitor, and a capping layer. The at least two first bottom metal vias are vertically disposed above a substrate. The first bottom metal layer is disposed above and in contact with these first bottom metal vias. The deep trench is disposed above the first bottom metal layer. The capacitor is formed within the deep trench and includes: a bottom electrode above and in contact with the top surface of the first bottom metal layer, a top electrode above the bottom electrode, and a dielectric layer disposed between the bottom electrode and the top electrode. The capping layer is disposed above and in contact with the top electrode of the capacitor. The bottom electrode laterally defines a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer, and the first bottom metal layer laterally defines a second region larger than the first region and laterally covering the first region. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a schematic cross-sectional side view of a semiconductor system including a deep trench MIM capacitor circuit and a control circuit according to some embodiments.

[0008] Figure 2 This is a top view of a well-known deep trench MIM capacitor structure. Figure 3 yes Figure 2 A cross-sectional side view of a conventional deep trench MIM capacitor structure, used to illustrate the connection faults experienced by the conventional deep trench MIM capacitor structure;

[0009] Figure 4 This is a schematic cross-sectional side view of a deep trench MIM capacitor circuit according to some embodiments;

[0010] Figure 5 According to the first embodiment Figure 4 Top view of a medium-deep trench MIM capacitor structure. Figure 6 yes Figure 5 Cross-sectional side view of a medium-deep trench MIM capacitor structure;

[0011] Figure 7 According to the second embodiment Figure 4 Top view of a medium-deep trench MIM capacitor structure. Figure 8 yes Figure 7 Cross-sectional side view of a medium-deep trench MIM capacitor structure;

[0012] Figure 9 According to the third embodiment Figure 4 Top view of a medium-deep trench MIM capacitor structure. Figure 10 yes Figure 9 Cross-sectional side view of a medium-deep trench MIM capacitor structure;

[0013] Figure 11 According to the fourth embodiment Figure 4 Top view of a medium-deep trench MIM capacitor structure. Figure 12 yes Figure 11 Cross-sectional side view of a medium-deep trench MIM capacitor structure;

[0014] Figure 13 According to the fifth embodiment Figure 4 Top view of a medium-deep trench MIM capacitor structure. Figure 14 yes Figure 13 Cross-sectional side view of a medium-deep trench MIM capacitor structure;

[0015] Figure 15 , Figure 16 , Figure 17 , Figure 18 ,and Figure 19 These are respectively based on the first, second, third, fourth, and fifth embodiments. Figure 4 Top view of a medium-deep trench MIM capacitor structure;

[0016] Figure 20 The illustration shows a flowchart of an example method for manufacturing a deep trench MIM capacitor structure according to various embodiments.

[0017] [Symbol Explanation]

[0018] 10:Substrate

[0019] 12: First transistor

[0020] 20: Capacitor

[0021] 20T: Deep Trench

[0022] 22: Bottom electrode

[0023] 22': Bottom electrode

[0024] 22B: Bottom section

[0025] 24: Top electrode

[0026] 24B: Bottom section

[0027] 25:ILD

[0028] 26: Dielectric layer

[0029] 26B: Bottom section

[0030] 28: Covering layer

[0031] 31: First bottom metal layer / bottom metal layer / bottom metal line

[0032] 31C': Connecting part

[0033] 31F: Top surface

[0034] 31': Bottom metal layer

[0035] 32: First bottom metal through hole / bottom metal through hole / through hole

[0036] 32': Bottom metal through hole

[0037] 33: Second bottom metal layer / Second bottom metal line

[0038] 34: Second bottom metal through hole

[0039] 41: First top through hole / First top metal through hole

[0040] 42: First top metal layer / First top metal line

[0041] 43: Top contact pad

[0042] 52: Second transistor

[0043] 61: First bottom metal line

[0044] 62: First bottom metal through hole

[0045] 63: Second bottom metal line

[0046] 64: Second bottom metal through hole

[0047] 71: Second top metal through hole

[0048] 72: Second top metal wire

[0049] 73: Top metal through hole

[0050] 74: Top metal line / layer

[0051] 75: Top contact pad

[0052] 100: Semiconductor Systems

[0053] 100A: Capacitor Circuit / Circuit / Structure

[0054] 100A': Capacitor Structure

[0055] 100B: Control Circuit

[0056] 2000: Method

[0057] 2002–2008: Operations

[0058] 5-5: Line

[0059] 7-7: Line

[0060] 9-9: Line

[0061] 11-11: Line

[0062] 13-13: Line

[0063] A: First Area

[0064] B: Second Area

[0065] B1: First subregion

[0066] B2: Second subregion

[0067] I: line

[0068] II: Line

[0069] III: Line Detailed Implementation

[0070] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0071] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly.

[0072] Capacitors are widely used components in many data manipulation and storage applications. Generally, a capacitor comprises two conductive electrodes on opposite sides of a dielectric or other insulating layer and can be classified based on the materials used to form the electrodes. For example, in a metal-insulator-metal (MIM) capacitor, the electrodes are essentially metal. To minimize size, deep trench (or cup-shaped) capacitor structures located within capacitor openings can be used. The capacitor openings are etched through a termination layer to expose the underlying contact sockets, and over-etching is performed to ensure that the capacitor openings are fully defined in each cell region above the semiconductor wafer. When capacitor openings overlap or shift, over-etching can create micro-trenches beneath the capacitor openings, which can adversely affect reliability. Compared to planar MIM transistors, deep trench MIM capacitors can have increased capacitance within a given space. However, deep trench MIM structures may reside on a small bottom metal layer and connect to logic circuits via the bottom metal layer and small metal vias. This can generate high stress and high thermal effects on the small top metal layer during deposition processes, leading to stress migration and electron migration in the bottom metal layer and the underlying bottom metal vias. This can result in reliability issues such as resistance shift or even open circuits in the bottom metal layer or bottom metal vias. Therefore, an improved deep trench MIM capacitor structure is needed.

[0073] According to some embodiments disclosed herein, a deep trench metal-insulator-metal (MIM) capacitor structure includes at least two first bottom metal vias disposed above a substrate; a first bottom metal layer disposed above and in contact with the first bottom metal vias; a deep trench disposed above the first bottom metal layer; and a capacitor formed within the deep trench. The MIM capacitor includes a bottom electrode having a bottom portion above and in contact with the top surface of the first bottom metal layer; a top electrode above the bottom electrode; and a dielectric layer disposed between the bottom electrode and the top electrode. The bottom electrode of the MIM capacitor laterally defines a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer, and the first top metal layer laterally defines a second region larger than and laterally covering the first region. The first bottom metal vias are laterally located within the second region. In some embodiments, the second region defined by the first bottom metal layer has a second rectangular shape, and at least two first bottom metal vias are laterally located within the first region, or laterally located outside the first region but within the second region. In other embodiments, the second region defined by the first bottom metal layer includes a first sub-region and a second sub-region that have different rectangular shapes and are laterally contacting each other. The first region, defined by the bottom electrode of the MIM capacitor, is laterally located within the first sub-region B1, and the first bottom metal via is laterally located within the second sub-region B2.

[0074] Thus, the deep trench MIM capacitor structure of this application avoids the corner connection of small bottom metal lines in the first bottom metal layer located below and in contact with the bottom electrode of the capacitor, and increases redundant first bottom metal vias located below and in contact with the first bottom metal (e.g., two or more first bottom metal vias). Therefore, it advantageously minimizes the effects of voids and / or broken lines in the first bottom metal and the first bottom metal vias, thereby improving the quality of the deep trench MIM capacitor structure.

[0075] Figure 1 This is a schematic cross-sectional side view of a semiconductor system 100 according to some embodiments, the semiconductor system including at least one capacitor circuit 100A and a control circuit 100B. The semiconductor system 100 can be configured as a system-on-chip (SoC) device integrating various functions on a single wafer. The capacitor circuit 100A and the control circuit 100B are each configured for different functions. For example, the capacitor circuit 100A may form a dynamic random access memory (DRAM) array for memory storage, and the control circuit 100B may serve as logic control circuitry for controlling the capacitor circuit 100A. It should be understood that the semiconductor system 100 may include other features and structures, such as inductors, passivation layers, bonding pads, and packages, but for simplicity and clarity, these are not explicitly shown. Figure 1 The text has been simplified.

[0076] In some embodiments, capacitor circuit 100A includes a substrate 10, a first transistor 12 formed on the substrate 10, and a deep trench MIM capacitor 20 coupled to the first transistor 12 via a plurality of bottom metal lines or layers (such as a first bottom metal layer 31 and a second bottom metal layer 33) and a plurality of bottom metal vias (such as a first bottom metal via 32 and a second bottom metal via 34). MIM capacitor 20 can be used for various functions, such as high-frequency noise filtering in mixed-signal applications. It can also be used as a coupling capacitor in memory applications, oscillators, phase-shift networks, bypass filters, and radio frequency (RF) applications. Figure 1As shown, a deep trench MIM capacitor 20 may be formed in a deep trench 20T disposed above a first bottom metal layer 31, and includes a bottom electrode 22 above and in contact with the top surface of the first bottom metal layer 31, a top electrode 24 above the bottom electrode 22, and a dielectric layer 26 therebetween. In some embodiments, the deep trench MIM capacitor 20 includes a cover layer 28 above and in contact with the top electrode 24. In some embodiments, the capacitor circuit 100A also includes a plurality of top metal vias (such as a first top via 41), a plurality of top metal lines or layers (such as a first top metal layer 42), and a top contact pad 43. (Refer to...) Figure 4 Further details regarding the 100A capacitor circuit are provided.

[0077] In some embodiments, the control circuit 100B includes a second transistor 52 formed on the substrate 10, a plurality of bottom metal lines or layers (such as 61 and 63) and bottom metal vias (such as 62 and 64), a plurality of top metal lines or layers (such as 72 and 74) and top metal vias (such as 71 and 73), and a top contact pad 75, and is capable of controlling the capacitor circuit 100A. In some embodiments, the deep trench MIM capacitor 20 is coupled to the control circuit 100B via a first bottom metal layer 31, a first bottom metal via 32, a second bottom metal layer 33, a second bottom metal via 34, a first transistor 12, and a second transistor 52, and is therefore controllable by the control circuit 100B.

[0078] Figure 2 This is a top view of a conventional MIM capacitor structure 100A'. Figure 3 yes Figure 2 A cross-sectional side view of a medium-deep trench MIM capacitor structure 100A' illustrates a connection failure experienced by the deep trench MIM capacitor structure 100A'. Figure 2 This is a top perspective view, showing the view along three lines I, II, and III respectively. Figure 4 The MIM capacitor structure 100A' comprises a bottom electrode 22', a bottom metal layer 31' with a connecting portion 31C', and three planes at three different levels, including a bottom electrode 22', a bottom metal via 32', and a bottom metal through-hole 32'. Reference Figure 2 and Figure 3The bottom electrode 22' of the MIM capacitor structure 100A' rests on the top surface of the bottom metal layer 31' via a connecting portion 31C'. This connecting portion has at least one narrow corner portion in its top view profile and rests on and laterally covers the single bottom metal via 32' below. Due to the high stress and high heat effects caused by the manufacturing process of the capacitor structure 100A', the bottom metal layer 31' and the bottom metal via 32' may experience connection failures, such as line broken and via open, resulting in connection failures in the capacitor structure 100A'.

[0079] Figure 4 This is a schematic cross-sectional side view of a deep trench MIM capacitor circuit 100A according to some embodiments. (Refer to the above text.) Figure 1 The capacitor circuit 100A includes a substrate 10, a first transistor 12 formed on the substrate 10, and a deep trench MIM capacitor 20 coupled to the first transistor 12 via a plurality of bottom metal layers (such as a first bottom metal layer 31 and a second bottom metal layer 33) and a plurality of bottom metal vias (such as a first bottom metal via 32 and a second bottom metal via 34). In some embodiments, the substrate 10 includes a silicon substrate (e.g., a wafer) with a crystalline structure. Depending on design requirements known in the art, the substrate 10 may include various doping configurations (e.g., a p-type substrate or an n-type substrate). Additionally, the substrate 10 may include various doped regions, such as p-type wells (p-wells) or n-type wells (n-wells). This doped region defines an oxide definition (OD) region. The substrate 10 may also include other elemental semiconductors, such as germanium and diamond. Alternatively, the substrate 10 may include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Furthermore, the substrate 10 may optionally include an epitaxial layer (epip layer), which may be strained to enhance performance, and may include a silicon-on-insulator (SOI) structure.

[0080] In some embodiments, a deep trench MIM capacitor 20 is formed in a deep trench 20T formed above a first bottom metal layer 31. In some embodiments, the deep trench MIM capacitor 20 includes a bottom electrode 22 formed above and in contact with the top surface of the first bottom metal layer 31, a top electrode 24 formed above the bottom electrode 22, and a dielectric layer 26 therebetween. In some embodiments, such as Figure 4As shown, the deep trench MIM capacitor 20 is cup-shaped. In some embodiments, the bottom electrode 22 includes a side portion and a bottom portion 22B that contacts the top surface of the first bottom metal layer 31; the dielectric layer 26 includes a side portion that contacts the side portion of the bottom electrode 22 and a bottom portion 26B that contacts the bottom portion 22B of the bottom electrode 22; the top electrode 24 includes a side portion that contacts the side portion of the dielectric layer 26 and a bottom portion 24B that contacts the bottom portion 26B of the dielectric layer 26. In some embodiments, the deep trench MIM capacitor 20 further includes a cover layer 28 above and in contact with the top electrode 24. In some embodiments, the capacitor circuit 100A includes a plurality of top metal lines or layers (such as the first top metal layer 42), a plurality of top metal vias (such as the first top via 41), and a top contact pad 43.

[0081] In some embodiments, the first transistor 12 is a polysilicon gate transistor; in other embodiments, the first transistor 12 is a metal gate transistor. In some embodiments, the bottom electrode 22 and the top electrode 24 are made of materials selected from TiN and TaN. In some embodiments, the dielectric layer 26 is made of a high-k metal oxide material selected from ZrOx, AlOx, and HfOx. In some embodiments, the bottom metal layer and vias (such as 31, 32, 33, and 34) and the top metal layer and vias (such as 41 and 42) are made of materials selected from copper, tungsten, aluminum, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. In some embodiments, the capping layer 28 is made of materials selected from SIN, oxides, SION, and combinations thereof. In some embodiments, the top contact pad 43 is made of aluminum-doped copper (e.g., 3-5% copper).

[0082] Figure 5 , Figure 7 , Figure 9 , Figure 11 ,and Figure 13 This is a top view of various examples of deep trench MIM capacitor structures according to various embodiments of this application. Figure 6 , Figure 8 , Figure 10 , Figure 12 ,and Figure 14 Various embodiments according to this disclosure Figure 5 , Figure 7 , Figure 9 , Figure 11 ,and Figure 13 Cross-sectional side views of various examples of deep trench MIM capacitor structures.

[0083] Figure 5 According to the first embodiment Figure 4A top perspective view of an example deep trench MIM capacitor structure, showing the various directions along the trench. Figure 4 The three planes shown are the bottom electrode 22, the bottom metal layer 31 without any connecting parts, and at least one bottom metal through-hole 32, as intercepted by the three lines I, II, and III. Figure 6 yes Figure 5 A cross-sectional side view taken along line 5-5 of a medium-deep trench MIM capacitor structure. In some embodiments, reference is made to... Figure 4 The deep trench MIM capacitor 20 includes a bottom electrode 22 formed above and in contact with the top surface of a first bottom metal layer 31, a top electrode 24 formed above the bottom electrode 22, and a dielectric layer 26 therebetween. In some embodiments, reference is also made to... Figure 4 The bottom portion 22B of the bottom electrode 22 rests on a first bottom metal layer 31, which in turn rests on two or more first bottom metal vias 32, which in turn rest on a second bottom metal layer 33. In some embodiments, reference is made to... Figure 4 , Figure 5 ,and Figure 6 The bottom electrode 22 laterally defines a first region A with a first rectangular shape at a level adjacent to the top surface 31F of the first bottom metal layer 31, and the first bottom metal layer 31 laterally defines a second region B with a second rectangular shape, the second region being larger than the first region A and laterally covering the first region A. In some embodiments, such as Figure 5 and Figure 6 As shown, two or more first bottom metal through holes 32 are laterally disposed within a first region A defined by the bottom portion 22B of the bottom electrode 22 and are laterally separated from each other.

[0084] Figure 7 According to the second embodiment Figure 4 A top view of the example deep trench MIM capacitor structure, showing the sections along... Figure 4 The three planes shown are the bottom electrode 22, the bottom metal layer 31 without any connecting parts, and at least one bottom metal through-hole 32, as intercepted by the three lines I, II, and III. Figure 8 yes Figure 7 A cross-sectional side view taken along line 7-7 of a medium-deep trench MIM capacitor structure. Similarly, in some embodiments, reference is made to... Figure 4 The deep trench MIM capacitor 20 includes a bottom electrode 22 formed above and in contact with the top surface of a first bottom metal layer 31, a top electrode 24 formed above the bottom electrode 22, and a dielectric layer 26 therebetween. In some embodiments, reference is also made to... Figure 4The bottom portion 22B of the bottom electrode 22 rests on a first bottom metal layer 31, which in turn rests on two or more first bottom metal vias 32, which in turn rest on a second bottom metal layer 33. In some embodiments, reference is made to... Figure 4 , Figure 7 ,and Figure 8 The bottom electrode 22 laterally defines a first region A with a first rectangular shape at a level adjacent to the top surface 31F of the first bottom metal layer 31, and the first bottom metal layer 31 laterally defines a second region B with a second rectangular shape, the second region being larger than the first region A and laterally covering the first region A. In some embodiments, such as Figure 7 and Figure 8 As shown, two first bottom metal through-holes 32 are laterally disposed separately from each other, laterally outside a first region A defined by the bottom portion 22B of the bottom electrode 22, and laterally within a second region B defined by the top surface of the first bottom metal layer 31. In some embodiments, such as Figure 7 and Figure 8 As shown, the two first bottom metal through holes 32 are laterally parallel and adjacent to one side of the second region B.

[0085] Figure 9 According to the third embodiment Figure 4 A top view of the example deep trench MIM capacitor structure, showing the sections along... Figure 4 The three planes shown are the bottom electrode 22, the bottom metal layer 31 without any connecting parts, and at least one bottom metal through-hole 32, as intercepted by the three lines I, II, and III. Figure 10 yes Figure 9 A cross-sectional side view taken along line 9-9 of a medium-deep trench MIM capacitor structure. Similarly, in some embodiments, reference is made to... Figure 4 The deep trench MIM capacitor 20 includes a bottom electrode 22 formed above and in contact with the top surface of a first bottom metal layer 31, a top electrode 24 formed above the bottom electrode 22, and a dielectric layer 26 therebetween. In some embodiments, reference is also made to... Figure 4 The bottom portion 22B of the bottom electrode 22 rests on a first bottom metal layer 31, which in turn rests on two or more first bottom metal vias 32, which in turn rest on a second bottom metal layer 33. In some embodiments, reference is made to... Figure 4 , Figure 9 ,and Figure 10The bottom electrode 22 laterally defines a first region A with a first rectangular shape at a level adjacent to the top surface 31F of the first bottom metal layer 31, and the first bottom metal layer 31 laterally defines a second region B with a second rectangular shape, the second region being larger than the first region A and laterally covering the first region A. In some embodiments, such as Figure 9 and Figure 10 As shown, two or more (e.g., eight) first bottom metal through holes 32 are laterally disposed apart from each other, laterally outside and around the first region A defined by the bottom portion 22B of the bottom electrode 22, and laterally within the second region B defined by the top surface of the first bottom metal layer 31.

[0086] Figure 11 According to the fourth embodiment Figure 4 A top view of the example deep trench MIM capacitor structure, showing the sections along... Figure 4 The three planes shown are the bottom electrode 22, the bottom metal layer 31 without any connecting parts, and at least one bottom metal through-hole 32, as intercepted by the three lines I, II, and III. Figure 12 yes Figure 11 A cross-sectional side view taken along line 11-11 of a medium-deep trench MIM capacitor structure. Similarly, in some embodiments, reference is made to... Figure 4 The deep trench MIM capacitor 20 includes a bottom electrode 22 formed above and in contact with the top surface of a first bottom metal layer 31, a top electrode 24 formed above the bottom electrode 22, and a dielectric layer 26 therebetween. In some embodiments, reference is also made to... Figure 4 The bottom portion 22B of the bottom electrode 22 rests on a first bottom metal layer 31, which in turn rests on two or more first bottom metal vias 32, which in turn rest on a second bottom metal layer 33. In some embodiments, reference is made to... Figure 4 , Figure 9 ,and Figure 10 The bottom electrode 22 laterally defines a first region A with a first rectangular shape at a level adjacent to the top surface 31F of the first bottom metal layer 31, and the first bottom metal layer 31 laterally defines a second region B with a second rectangular shape, the second region being larger than the first region A and laterally covering the first region A. In some embodiments, such as Figure 11 and Figure 12 As shown, two or more first bottom metal through holes 32 are in lateral contact with each other and form a combined bottom metal through hole 32' laterally within a first region A defined by the bottom electrode 22.

[0087] Figure 13 According to the fifth embodiment Figure 4 A top view of the example deep trench MIM capacitor structure, showing the sections along... Figure 4 The three planes shown are the bottom electrode 22, the bottom metal layer 31 without any connecting parts, and at least one bottom metal through-hole 32, as intercepted by the three lines I, II, and III. Figure 14 yes Figure 13 A cross-sectional side view taken along line 13-13 of a medium-deep trench MIM capacitor structure. Similarly, in some embodiments, reference is made to... Figure 4 The deep trench MIM capacitor 20 includes a bottom electrode 22 formed above and in contact with the top surface of a first bottom metal layer 31, a top electrode 24 formed above the bottom electrode 22, and a dielectric layer 26 therebetween. In some embodiments, reference is also made to... Figure 4 The bottom portion 22B of the bottom electrode 22 rests on a first bottom metal layer 31, which in turn rests on two or more first bottom metal vias 32, which in turn rest on a second bottom metal layer 33. In some embodiments, reference is made to... Figure 4 , Figure 13 ,and Figure 14 The bottom electrode 22 laterally defines a first region A having a first rectangular shape at a level adjacent to the top surface 31F of the first bottom metal layer 31, and the first bottom metal layer 31 laterally defines a second region B. In some embodiments, different from the first, second, third, and fourth embodiments, such as Figure 13 and Figure 14 As shown, the second region B includes a first sub-region B1 and a second sub-region B2 with different rectangular shapes and laterally contacting each other, wherein the first sub-region B1 is larger than the second sub-region B2. In some embodiments, the first region A is laterally located within the first sub-region B1, and the first bottom metal through-hole 32 is laterally located within the second sub-region B2.

[0088] For example Figure 5 , Figure 7 , Figure 9 ,and Figure 11 In some embodiments, the ratio of the area of ​​A to the area of ​​B is in the range of about 0.2 to about 0.8, and the ratio of the area of ​​the through-hole 32 to the area of ​​A is about 0.005 to about 0.2. For example, refer to... Figure 13 In some embodiments, the ratio of the area of ​​A to the area of ​​(B1+B2) is in the range of about 0.2 to about 0.8, and the ratio of the area of ​​the through-hole 32 to the area of ​​A is about 0.005 to about 0.2. (See reference) Figure 5 , Figure 7 , Figure 9 ,and Figure 11In some embodiments, the width of A is in the range of about 100 nm to about 500 nm, and the length of A is in the range of about 500 nm to about 2 μm; the width of B is in the range of about 120 nm to about 600 nm, and the length of B is in the range of about 600 nm to about 2.2 μm. In some embodiments, for example, as Figure 5 , Figure 7 ,and Figure 9 As shown, the via 32 is a square shape with four sides of equal length (ranging from about 20 nm to about 50 nm), and the number of vias 32 is two or more. In other embodiments, for example, as... Figure 11 As shown, the via 32 is rectangular in shape, with a length ranging from about 40 nm to about 100 nm and a width ranging from about 20 nm to about 50 nm, and the number of vias 32 is one (or more than one, not shown). Reference Figure 13 In some embodiments, the width of A is in the range of about 100 nm to about 500 nm, the length of A is in the range of about 500 nm to about 2 μm, the width of B1 is in the range of about 120 nm to about 600 nm, the length of B1 is in the range of about 600 nm to about 2.2 μm, the width of B2 is in the range of about 50 nm to about 250 nm, the length of B2 is in the range of about 100 nm to about 1 μm, the length of each side of the square-shaped via 32 is in the range of about 20 nm to about 50 nm, and the number of vias 32 is two or more. Figure 15 , Figure 16 , Figure 17 , Figure 18 ,and Figure 19 These are respectively based on the first, second, third, fourth, and fifth embodiments. Figure 1 A top view of a portion of the capacitor circuit 100A and a portion of the control circuit 100B illustrates various configurations of the capacitor circuit 100A, such as the bottom electrode 22, the first bottom metal line 31, and the first bottom metal via 32, and the control circuit 100B, including the first bottom metal line 61, the first bottom metal via 62, the second top metal via 71, and the second top metal line 72. Figure 1 , Figure 15 , Figure 16 , Figure 17 , Figure 18 ,and Figure 19As shown, the bottom electrode 22 of the MIM capacitor 20 of the capacitor circuit 100A is coupled to the second top metal line 72 of the control circuit 100B via the first bottom metal line 31, the first bottom metal via 32, the second bottom metal line 33, the second bottom metal via 34, the first transistor 12 of the capacitor circuit 100A, and the second transistor 52, the second bottom metal via 64, the second bottom metal line 63, the first bottom metal via 62, the first bottom metal line 61, and the second top metal via 71 of the control circuit 100B.

[0089] Figure 20 The illustrations depict the manufacturing process according to various embodiments, such as... Figure 4 The flowchart illustrates an example method 2000 for a deep trench MIM capacitor structure 100A. It should be understood that additional embodiments of the method may be implemented. Figure 20 Additional operations are provided before, during, and after the processes described herein, and may replace or eliminate some of the operations described below. The order of operations / processes is interchangeable, and at least some of the operations or processes may be performed in a different order. In some embodiments, at least two or more operations or processes overlap in time or are performed nearly simultaneously.

[0090] In some embodiments, such as Figure 1 As shown, multiple transistors (such as first transistor 12 and second transistor 52) are formed on substrate 10 in the FEOL network. For example, various methods such as oxidation, photolithography, deposition, and etching can be used to form the multiple transistors. In some embodiments, substrate 10 includes a monocrystalline semiconductor layer at least on its surface portion. The substrate may include monocrystalline semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, substrate 10 is a silicon wafer. Substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layers can be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain regions.

[0091] like Figures 4 to 14 and Figure 20As shown, in some embodiments, operation 2002 includes forming at least two first bottom metal vias 32 over the substrate 10. Various methods of optical lithography, etching, and deposition can be used to form at least two first bottom metal vias 32. In some embodiments, prior to forming at least two first bottom metal vias 32, a plurality of second bottom metal vias 34 are formed over and coupled to the first transistor 12, followed by the formation of a second bottom metal layer 33 over and in contact with the plurality of second bottom metal vias 34. In some embodiments, at least two first bottom metal vias 32 are formed over and in contact with the second bottom metal layer 33.

[0092] Next, as Figures 4 to 14 and Figure 20 As shown, in some embodiments, operation 2004 includes forming a first bottom metal layer 31 above and in contact with the first bottom metal via 32. Various methods, including optical lithography, etching, and deposition, can be used to form the first bottom metal layer 31. In some embodiments, the interconnects or layers (such as the first metal layer 31 and the second metal layer 33) and interconnect vias (such as the first metal via 32 and the second metal via 34) are made of a material selected from copper, tungsten, aluminum, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof.

[0093] Next, as Figure 4 and Figure 20 As shown, in some embodiments, operation 2006 includes forming a deep trench 20T within the inter-layer dielectric (ILD) 25 above the first bottom metal layer 31, the deep trench 20T having an open bottom surface and side surfaces. Various methods of optical lithography, etching, and deposition processes can be used to form the deep trench 20T within the ILD 25.

[0094] Next, as Figures 4 to 14 and Figure 20As shown, in some embodiments, operation 2008 includes forming a capacitor 20 within a deep trench 20T. The capacitor 20 includes a bottom electrode 22, a top electrode 24, and a dielectric layer 26 between the bottom electrode 22 and the top electrode 24. In some embodiments, forming the capacitor 20 within the deep trench 20T includes forming a bottom electrode 22, which includes a bottom portion 22B contacting the top surface 31F of a first bottom metal layer 31 and a vertical portion contacting the side surface of the trench 20T; forming a dielectric layer 26, which includes a bottom portion 26B contacting the bottom portion 22B of the bottom electrode 22 and a vertical portion contacting the vertical portion of the bottom electrode 22; and forming a top electrode 24, which includes a bottom portion 24B contacting the bottom portion 26B of the dielectric layer 26 and a vertical portion contacting the vertical portion of the dielectric layer 26. In some embodiments, the bottom electrode 22 and the top electrode 24 are made of a material selected from TiN and TaN. In some embodiments, the dielectric layer 26 is made of a high-k metal oxide material selected from ZrOx, AlOx, and HfOx.

[0095] In some embodiments, such as Figure 4 As shown, a capping layer 28 is formed above and in contact with the top electrode 24. In some embodiments, such as Figure 4 As shown, a capping layer 28 is formed above the top electrode 24 and contacts the sides of the top electrode 24 and the dielectric layer 26. In some embodiments, the capping layer 28 is made of a material selected from SIN, oxides, SION, and combinations thereof.

[0096] In some embodiments, such as Figure 4 As shown, at least one first top metal via 41 is formed over and in contact with the capping layer 28, at least one first top metal wire or layer 42 is formed over and in contact with the at least one first top metal via 41, and at least one top contact pad 43 is formed over and in contact with the first top metal wire or layer 42. In some embodiments, the first top metal via 41, the first top metal wire or layer 42, and the top contact pad 43 are made of Cu, W, Al, and combinations thereof. In some embodiments, the top contact pad 43 is made of a material doped with Cu (e.g., 3-5% Cu).

[0097] In some embodiments, as referenced above Figures 5 to 14 The illustration shows the spatial relationship of the bottom electrode 22 of the capacitor 20, the first bottom metal layer 31 below the bottom electrode 22, and the first bottom metal through hole 32 below the first bottom metal layer 31. The bottom electrode 22 of the capacitor 20 laterally defines a first region A with a rectangular shape at a level adjacent to the top surface of the first bottom metal layer 31. The first bottom metal layer 31 laterally defines a second region B that is larger than and laterally covers the first region A.

[0098] In some embodiments, such as Figures 5 to 12 As shown, the second region B, defined by the first bottom metal layer 31, has a rectangular shape and laterally covers the first region A, defined by the bottom electrode 22 of the capacitor 20. In some embodiments, as Figures 5 to 6 As shown, a first bottom metal through-hole 32 is laterally disposed within a first region A defined by the bottom electrode 22 of the capacitor 20. In some embodiments, such as Figures 7 to 10 As shown, a first bottom metal via 32 is laterally disposed within a second region B defined by a first bottom metal layer 31, but outside a first region A defined by a bottom electrode 22 of the capacitor 20. In some embodiments, at least two first bottom metal vias 32 are laterally contacting each other to form a combined bottom metal via 32', which is laterally disposed within the second region B defined by the first bottom metal layer 31, but outside the first region A defined by a bottom electrode 22 of the capacitor 20.

[0099] In other embodiments, such as Figures 13 to 14 As shown, the second region B, defined by the first bottom metal layer 31, has a first sub-region B1 and a second sub-region B2 that are rectangular in shape and laterally contact each other. In some embodiments, the first region A, covered by the bottom electrode 22 of the capacitor 20, is laterally located within the first sub-region B1 of the second region B, and the bottom metal via 32 is laterally located within the second sub-region B2 of the second region B.

[0100] Thus, the deep trench MIM capacitor structure or circuit 100A of this application reduces or avoids small bottom metal wire corner turns in the first bottom metal layer 31 located below and in contact with the bottom electrode 22 of the capacitor, and increases redundant first bottom metal vias 32 located below and in contact with the first bottom metal layer 31. Therefore, it advantageously minimizes the void effect in the first bottom metal layer 31 and the first bottom metal vias 32, thereby improving the quality of the capacitor structure and circuit.

[0101] In one embodiment disclosed herein, a capacitor structure includes: at least two first bottom metal vias vertically disposed above a substrate; a first bottom metal layer disposed above and in contact with the first bottom metal vias; a deep trench disposed above the first bottom metal layer; and a capacitor formed within the deep trench. The capacitor includes: a bottom electrode above and in contact with the top surface of the first bottom metal layer; a top electrode above the bottom electrode; and a dielectric layer disposed between the bottom electrode and the top electrode. The bottom electrode laterally defines a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer, and the first bottom metal layer laterally defines a second region larger than and laterally covering the first region.

[0102] In some embodiments, the first bottom metal through-holes are laterally located within the second region.

[0103] In some embodiments, the second region has a second rectangular shape.

[0104] In some embodiments, the second region consists of a first sub-region and a second sub-region having different rectangular shapes and being laterally contacted by each other, wherein the first sub-region is larger than the second sub-region.

[0105] In some embodiments, the first region is laterally located within the first sub-region, and the first bottom metal vias are laterally located within the second sub-region.

[0106] In some embodiments, the first bottom metal vias are laterally contacted to form a combined bottom metal via in the second region but outside the first region.

[0107] In some embodiments, the first bottom metal through-holes are laterally disposed in the first region.

[0108] In some embodiments, the first bottom metal through-holes are laterally disposed within the second region but outside the first region.

[0109] In some embodiments, the bottom electrode of the capacitor is coupled to a first transistor via a rear contact, and the first transistor is coupled to a second transistor of a control circuit.

[0110] In some embodiments, the capacitor structure further includes a cover layer disposed above and in contact with the top electrode of the capacitor.

[0111] In some embodiments, the capacitor structure further includes: a first top metal via disposed above and in contact with the cover layer; a first top metal layer disposed above and in contact with the first top metal via; and a top contact disposed above and in contact with the first top metal layer.

[0112] In another embodiment disclosed herein, a capacitor structure includes: at least two first bottom metal vias disposed above a substrate; a first bottom metal layer disposed above and in contact with the first bottom metal vias; and a deep trench capacitor formed above the first bottom metal layer. The deep trench capacitor includes a bottom electrode comprising a bottom portion in contact with the top surface of the first bottom metal layer and a vertical portion; a dielectric layer comprising the bottom portion in contact with the bottom of the bottom electrode and the vertical portion in contact with the vertical portion of the bottom electrode; and a top electrode in contact with the bottom portion and the vertical portion of the dielectric layer. The bottom electrode of the capacitor laterally defines a first region having a first rectangular shape, and the first bottom metal layer laterally defines a second region larger than and laterally covering the first region.

[0113] In some embodiments, the second region laterally covers the first bottom metal through-holes.

[0114] In some embodiments, the second region has a second rectangular shape.

[0115] In some embodiments, the first bottom metal through-holes are laterally covered by the first region.

[0116] In some embodiments, the first bottom metal through-holes are laterally covered by the second region but extend laterally beyond the first region.

[0117] In yet another embodiment disclosed herein, a method of manufacturing a capacitor structure includes: forming at least two first bottom metal vias above a substrate; forming a first bottom metal layer above and in contact with the first bottom metal vias; forming a deep trench above the first bottom metal layer, the deep trench including an open bottom surface and side surfaces; and forming a capacitor within the deep trench. The capacitor includes a bottom electrode, a top electrode, and a dielectric layer between the bottom electrode and the top electrode. The bottom electrode of the capacitor laterally defines a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer, and the first bottom metal layer laterally defines a second region larger than and laterally covering the first region.

[0118] In some embodiments, the second region has a second rectangular shape, and the first bottom metal through-holes are laterally covered by the second region.

[0119] In some embodiments, the second region comprises a first sub-region of a second rectangular shape and a second sub-region of a third rectangular shape that are laterally adjacent to each other, wherein the first region is laterally located within the first sub-region of the second region, and the first bottom metal through holes are laterally located within the second sub-region of the second region.

[0120] In some embodiments, the formation of the capacitor within the deep trench includes the following steps: forming a bottom electrode, the bottom electrode including a bottom portion contacting the top surface of the first bottom metal layer and a vertical portion contacting the side surface of the deep trench; forming a dielectric layer, the dielectric layer including a bottom portion contacting the bottom portion of the bottom electrode and a vertical portion contacting the vertical portion of the bottom electrode; and forming a top electrode contacting the bottom portion and the vertical portion of the dielectric layer.

[0121] As used herein, the terms “about” and “approximately” generally indicate a given quantity of value that may vary based on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the term “about” may indicate a given quantity of value that varies, for example, within a range of 10% to 30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0122] In another embodiment disclosed herein, a capacitor structure includes: at least two first bottom metal vias disposed above a substrate; a first bottom metal layer disposed above and in contact with the first bottom metal vias; and a deep trench capacitor formed above the first bottom metal layer. The deep trench capacitor includes a bottom electrode comprising a bottom portion in contact with the top surface of the first bottom metal layer and a vertical portion; a dielectric layer comprising the bottom portion in contact with the bottom of the bottom electrode and the vertical portion in contact with the vertical portion of the bottom electrode; and a top electrode in contact with the bottom portion and the vertical portion of the dielectric layer. The bottom electrode of the capacitor laterally defines a first region having a first rectangular shape, and the first bottom metal layer laterally defines a second region larger than and laterally covering the first region.

[0123] In yet another embodiment disclosed herein, a method of manufacturing a capacitor structure includes: forming at least two first bottom metal vias above a substrate; forming a first bottom metal layer above and in contact with the first bottom metal vias; forming a deep trench above the first bottom metal layer, the deep trench including an open bottom surface and side surfaces; and forming a capacitor within the deep trench. The capacitor includes a bottom electrode, a top electrode, and a dielectric layer between the bottom electrode and the top electrode. The bottom electrode of the capacitor laterally defines a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer, and the first bottom metal layer laterally defines a second region larger than and laterally covering the first region.

[0124] In yet another embodiment disclosed herein, a capacitor structure includes: at least two first bottom metal vias, a first bottom metal layer, a deep trench, a capacitor, and a capping layer. The at least two first bottom metal vias are vertically disposed above a substrate. The first bottom metal layer is disposed above and in contact with these first bottom metal vias. The deep trench is disposed above the first bottom metal layer. The capacitor is formed within the deep trench and includes: a bottom electrode above and in contact with the top surface of the first bottom metal layer, a top electrode above the bottom electrode, and a dielectric layer disposed between the bottom electrode and the top electrode. The capping layer is disposed above and in contact with the top electrode of the capacitor. The bottom electrode laterally defines a first region having a first rectangular shape at a level adjacent to the top surface of the first bottom metal layer, and the first bottom metal layer laterally defines a second region larger than the first region and laterally covering the first region.

[0125] As used herein, the terms “about” and “approximately” generally indicate a given quantity of value that may vary based on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the term “about” may indicate a given quantity of value that varies, for example, within a range of 10% to 30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0126] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A capacitor structure, characterized in that, Include: At least two first bottom metal through holes are vertically disposed above a substrate; A first bottom metal layer is disposed above and in contact with the first bottom metal through-holes; A deep trench is disposed above the first bottom metal layer; and A capacitor formed within the deep trench and comprising: A bottom electrode is located above and in contact with a top surface of the first bottom metal layer; A top electrode, which is located above the bottom electrode; and A dielectric layer is disposed between the bottom electrode and the top electrode. The bottom electrode laterally defines a first region having a first rectangular shape at a position adjacent to the top surface of the first bottom metal layer, and The first bottom metal layer laterally defines a second region that is larger than the first region and laterally covers the first region.

2. The capacitor structure as described in claim 1, characterized in that, These first bottom metal through-holes are laterally located within the second region.

3. The capacitor structure as described in claim 1, characterized in that, The second region has a second rectangular shape.

4. The capacitor structure as described in claim 1, characterized in that, The second region is composed of a first sub-region and a second sub-region with different rectangular shapes that are laterally in contact with each other, wherein the first sub-region is larger than the second sub-region.

5. A capacitor structure, characterized in that, Include: At least two first bottom metal through holes are disposed above a substrate; A first bottom metal layer is disposed above and in contact with the first bottom metal through-holes; A deep trench capacitor, formed above the first bottom metal layer, and comprising: A bottom electrode includes a bottom portion in contact with a top surface of the first bottom metal layer and a vertical portion; A dielectric layer comprising a bottom portion in contact with the bottom portion of the bottom electrode and a vertical portion in contact with the vertical portion of the bottom electrode; and A top electrode that contacts the bottom portion and the vertical portion of the dielectric layer. The bottom electrode of the capacitor laterally defines a first region having a first rectangular shape, and The first bottom metal layer laterally defines and covers a second region that is larger than and laterally covers the first region.

6. The capacitor structure as described in claim 5, characterized in that, The second region laterally covers the first bottom metal through holes.

7. The capacitor structure as described in claim 5, characterized in that, These first bottom metal through-holes are laterally covered by the first region.

8. The capacitor structure as described in claim 5, characterized in that, The first bottom metal through-holes are laterally covered by the second region but extend laterally beyond the first region.

9. A capacitor structure, characterized in that, Include: At least two first bottom metal through holes are vertically disposed above a substrate; A first bottom metal layer is disposed above and in contact with the first bottom metal through-holes; A deep trench is disposed above the first bottom metal layer; and A capacitor formed within the deep trench and comprising: A bottom electrode is located above and in contact with a top surface of the first bottom metal layer; A top electrode, which is located above the bottom electrode; and A dielectric layer is disposed between the bottom electrode and the top electrode, and A covering layer is disposed above and in contact with the top electrode of the capacitor. The bottom electrode laterally defines a first region having a first rectangular shape at a position adjacent to the top surface of the first bottom metal layer, and The first bottom metal layer laterally defines a second region that is larger than the first region and laterally covers the first region.

10. The capacitor structure as described in claim 9, characterized in that, It further includes: A first top metal through-hole is disposed above and in contact with the cover layer; A first top metal layer is disposed above and in contact with the first top metal through-hole; and A top contact is disposed above and in contact with the first top metal layer.

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