High electron mobility transistor

Abstract

The utility model provides a kind of high electron mobility transistor, the high electron mobility transistor includes source field plate, the source field plate includes at least three layers of source field plate layer, from close to the semiconductor substrate to away from the semiconductor substrate, the three layers of source field plate layer include first source field plate layer, second source field plate layer and third source level field plate layer, wherein, the distance of the third source level field plate layer to the semiconductor substrate is less than or equal to 600nm, by the source field plate can adjust electric field distribution, weaken the channel electric field near gate and drain, improve the withstand voltage of the high electron mobility transistor, increase reliability.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a high electron mobility transistor. Background Technology

[0002] A high electron mobility transistor (HEMT) is a field-effect transistor (FET) based on a heterojunction structure, primarily used for high-frequency, low-noise, and high-power applications. Its core advantage lies in utilizing the high electron mobility of the two-dimensional electron gas (2DEG) at the heterojunction interface to achieve high-current applications.

[0003] Currently, one of the most significant problems with high electron mobility transistors (HMTs) remains the poor breakdown voltage reliability caused by electric field concentration. Therefore, improving the breakdown voltage capability of HMTs remains a key research focus for those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to provide a high electron mobility transistor to solve the problem of poor voltage withstand capability caused by electric field concentration in existing high electron mobility transistors.

[0005] To solve the above-mentioned technical problems, this utility model provides a high electron mobility transistor, the high electron mobility transistor comprising:

[0006] Semiconductor substrate;

[0007] The gate metal electrode, source ohmic metal electrode, and drain ohmic metal electrode are located on the semiconductor substrate; and,

[0008] A source field plate, comprising at least three source field plate layers, from near the semiconductor substrate to away from the semiconductor substrate, wherein the three source field plate layers include a first source field plate layer, a second source field plate layer and a third source field plate layer, wherein the distance of the third source field plate layer to the semiconductor substrate is less than or equal to 600 nm.

[0009] Optionally, in the high electron mobility transistor, the first source field plate and the gate metal electrode are located in the same photomask layer.

[0010] Optionally, in the high electron mobility transistor, the source ohmic metal electrode and the drain ohmic metal electrode are located in the same photomask layer; the first source field plate layer is located in front of the source ohmic metal electrode layer, or the first source field plate layer is located in behind the source ohmic metal electrode layer.

[0011] Optionally, in the high electron mobility transistor, the second source field plate and the first source field plate overlap.

[0012] Optionally, in the high electron mobility transistor, the second source field plate layer also overlaps with the gate metal electrode and / or the third source field plate layer.

[0013] Optionally, in the high electron mobility transistor, the high electron mobility transistor further includes a drain field plate, the drain field plate comprising a drain field plate layer.

[0014] Optionally, in the high electron mobility transistor, the drain field plate and the second source field plate are located in the same photomask layer.

[0015] Optionally, in the high electron mobility transistor, the high electron mobility transistor further includes: a first metal layer and a second metal layer, wherein the first metal layer is connected to the source ohmic metal electrode and the source field plate, and the second metal layer is connected to the drain ohmic metal electrode.

[0016] Optionally, in the high electron mobility transistor, the source field plate further includes a fourth source field plate layer, which is located in the same photomask layer as the first metal layer.

[0017] Optionally, in the high electron mobility transistor, the fourth source field plate and the third source field plate overlap; in a direction horizontal to the semiconductor substrate, the fourth source field plate is closer to the drain ohmic electrode than the third source field plate.

[0018] In the high electron mobility transistor provided by this utility model, the high electron mobility transistor includes a source field plate, which includes at least three source field plate layers, from near the semiconductor substrate to away from the semiconductor substrate. The three source field plate layers include a first source field plate layer, a second source field plate layer, and a third source field plate layer. The distance between the third source field plate layer and the semiconductor substrate is less than or equal to 600 nm. The source field plate can adjust the electric field distribution, weaken the channel electric field near the gate and drain, and improve the breakdown voltage of the high electron mobility transistor. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a high electron mobility transistor according to Embodiment 1 of this utility model.

[0020] Figure 2 This is a schematic diagram of the high electron mobility transistor of Embodiment 2 of this utility model.

[0021] Figure 3 This is a schematic diagram of the high electron mobility transistor of Embodiment 3 of this utility model.

[0022] The reference numerals in the attached figures are explained as follows:

[0023] 10 - High electron mobility transistor; 100 - Semiconductor substrate; 101 - Source region; 102 - Drain region; 103 - Gate structure; 110 - Gate metal electrode; 120 - Source ohmic metal electrode; 130 - Drain ohmic metal electrode; 140 - Source field plate; 141 - Source field plate layer; 141A - First source field plate layer; 141B - Second source field plate layer; 141C - Third source field plate layer; 141D - Fourth source field plate layer; 150 - First dielectric layer; 151 - Second dielectric layer; 152 - Third dielectric layer; 153 - Fourth dielectric layer; 154 - Fifth dielectric layer; 160 - First metal layer; 161 - Second metal layer; h - Distance.

[0024] 20 - High electron mobility transistor; 200 - Semiconductor substrate; 210 - Gate metal electrode; 220 - Source ohmic metal electrode; 230 - Drain ohmic metal electrode; 240 - Source field plate; 241 - Source field plate layer; 241A - First source field plate layer; 241B - Second source field plate layer; 241C - Third source field plate layer; 241D - Fourth source field plate layer; 250 - First dielectric layer; 251 - Second dielectric layer; 252 - Third dielectric layer; 253 - Fourth dielectric layer; 254 - Fifth dielectric layer; 260 - First metal layer; 261 - Second metal layer; 270 - Drain field plate; 271 - Drain field plate layer.

[0025] 30 - High electron mobility transistor; 300 - Semiconductor substrate; 301 - Source region; 302 - Drain region; 303 - Gate structure; 310 - Gate metal electrode; 320 - Source ohmic metal electrode; 330 - Drain ohmic metal electrode; 340 - Source field plate; 341 - Source field plate layer; 341A - First source field plate layer; 341B - Second source field plate layer; 341C - Third source field plate layer; 341D - Fourth source field plate layer; 350 - First dielectric layer; 351 - Second dielectric layer; 352 - Third dielectric layer; 353 - Fourth dielectric layer; 354 ​​- Fifth dielectric layer; 360 - First metal layer; 361 - Second metal layer. Detailed Implementation

[0026] The high electron mobility transistor proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0027] The terminology used in this utility model is for the purpose of describing particular embodiments only and is not intended to limit the utility model. Unless otherwise defined in this application, the technical or scientific terms used in this utility model should be understood in their ordinary sense by one of ordinary skill in the art to which this utility model pertains. The words "first," "second," and similar terms used in this utility model specification and claims do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, the words "a" or "one" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, the words "upper / upper layer" and / or "lower / lower layer" and similar terms are for ease of description only and are not limited to a location or spatial orientation. The words "comprising" or "including" and similar terms mean that the elements or structures preceding "comprising" or "including" cover the elements or structures listed after "comprising" or "including" and their equivalents, and do not exclude other elements or structures. The words "connected" or "linked" and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0028] Example 1

[0029] Please refer to Figure 1 This is a schematic diagram of the high electron mobility transistor according to Embodiment 1 of this utility model. Figure 1 As shown, the high electron mobility transistor 10 includes: a semiconductor substrate 100; a gate metal electrode 110, a source ohmic metal electrode 120, and a drain ohmic metal electrode 130 located on the semiconductor substrate 100; and a source field plate 140, the source field plate 140 including at least three source field plate layers 141, from near the semiconductor substrate 100 to away from the semiconductor substrate 100, the three source field plate layers 141 including a first source field plate layer 141A, a second source field plate layer 141B, and a third source field plate layer 141C, wherein the distance from the third source field plate layer 141C to the semiconductor substrate 100 is less than or equal to 600 nm.

[0030] That is, among the first source field plate layer 141A, the second source field plate layer 141B, and the third source field plate layer 141C, the third source field plate layer 141C is the furthest from the semiconductor substrate 100, and its distance h from the semiconductor substrate 100 is less than or equal to 600 nm; correspondingly, the distances from the first source field plate layer 141A to the semiconductor substrate 100 and the distances from the second source field plate layer 141B to the semiconductor substrate 100 will be even smaller. For example, in some embodiments of this application, the distance from the third source field plate layer 141C to the semiconductor substrate 100 is 400 nm, the distance from the second source field plate layer 141B to the semiconductor substrate 100 is 300 nm, and the distance from the first source field plate layer 141A to the semiconductor substrate 100 is 200 nm.

[0031] In this embodiment, the source field plate 140 can adjust the electric field distribution, weaken the channel electric field near the gate and drain, and improve the breakdown voltage of the high electron mobility transistor 10. Specifically, among the first source field plate layer 141A, the second source field plate layer 141B, and the third source field plate layer 141C, the third source field plate layer 141C is the furthest from the semiconductor substrate 100, with a distance to the semiconductor substrate 100 less than or equal to 600 nm. That is, the distances from the first source field plate layer 141A, the second source field plate layer 141B, and the third source field plate layer 141C to the semiconductor substrate 100 are all relatively small, thereby allowing for better control of the electric field distribution, avoiding electric field interference, and improving the breakdown voltage of the high electron mobility transistor 10.

[0032] In some embodiments of this application, the semiconductor substrate 100 may include a first nitrogen-based semiconductor layer (not shown) and a second nitrogen-based semiconductor layer (not shown) stacked sequentially. The band gap of the second nitrogen-based semiconductor layer is larger than that of the first nitrogen-based semiconductor layer. The first nitrogen-based semiconductor layer may be made of, for example, gallium nitride (GaN), and the second nitrogen-based semiconductor layer may be made of, for example, aluminum gallium nitride (AlGaN), forming a region between them that accommodates a two-dimensional electron gas (2DEG).

[0033] An active region 101 and a drain region 102 are formed in the semiconductor substrate 100, and a gate structure 103 is formed on the semiconductor substrate 100. In the extending direction of the semiconductor substrate 100, the distance between the gate structure 103 and the source region 101 is smaller than the distance between the gate structure 103 and the drain region 102, that is, the gate structure 103 is closer to the source region 101 than the drain region 102.

[0034] like Figure 1 As shown, a first dielectric layer 150 is deposited on the semiconductor substrate 100. The first dielectric layer 150 can be a single-layer structure or a multi-layer stacked structure. The material of the first dielectric layer 150 can be silicon oxide, silicon nitride, etc. The first dielectric layer 150 has a first opening (not shown in the figure) exposing the source region 101 and a second opening (not shown in the figure) exposing the drain region 102. The source ohmic metal electrode 120 is connected to the source region 101 through the first opening, and the drain ohmic metal electrode 130 is connected to the drain region 102 through the second opening. The source ohmic metal electrode 120 and the drain ohmic metal electrode 130 can be located in the same photomask layer. The first opening and the second opening extend into the two-dimensional electron gas region to ensure the electrical performance of the connection between the source ohmic metal electrode 120 and the source region 101, and the electrical performance of the connection between the drain ohmic metal electrode 130 and the drain region 102.

[0035] Please continue to refer to this. Figure 1 A second dielectric layer 151 is covered on the first dielectric layer 150. The second dielectric layer 151 can be a single-layer structure or a multi-layer stacked structure. The material of the second dielectric layer 151 may include, for example, silicon oxide, silicon nitride, etc. In this embodiment, the second dielectric layer 151 has a third opening (not shown in the figure), which extends through the first dielectric layer 150 to expose the gate structure 103. The gate metal electrode 110 is connected to the gate structure 103 through the third opening.

[0036] In the extending direction of the semiconductor substrate 100, the distance between the gate metal electrode 110 and the source ohmic metal electrode 120 is smaller than the distance between the gate metal electrode 110 and the drain ohmic metal electrode 130, that is, the gate metal electrode 110 is closer to the source ohmic metal electrode 120 relative to the drain ohmic metal electrode 130.

[0037] like Figure 1 As shown in this embodiment, the first source field plate 141A and the gate metal electrode 110 are located in the same photomask layer. Here, the first source field plate 141A can be formed simultaneously with the gate metal electrode 110, wherein a portion of the gate metal electrode 110 can cover the second dielectric layer 151, and another portion is connected to the gate structure 103 through the third opening; the first source field plate 141A is located between the gate metal electrode 110 and the drain ohmic metal electrode 130, and close to the second dielectric layer 151 of the gate metal electrode 110.

[0038] In this embodiment, the source ohmic metal electrode 120 and the drain ohmic metal electrode 130 are formed before the first source field plate layer 141A. The first source field plate layer 141A may be located one or more layers after the source ohmic metal electrode 120 and the drain ohmic metal electrode 130. In some embodiments of this application, the second dielectric layer 151 covers the source ohmic metal electrode 120 and the drain ohmic metal electrode 130, and the first source field plate layer 141A is located on the second dielectric layer 151. The surface of the first source field plate layer 141A is higher than the surfaces of the source ohmic metal electrode 120 and the drain ohmic metal electrode 130.

[0039] In this embodiment, a third dielectric layer 152 is deposited on the second dielectric layer 151. The third dielectric layer 152 can be a single-layer structure or a multi-layer stacked structure. The material of the third dielectric layer 152 may include, for example, silicon oxide, silicon nitride, etc.

[0040] The second source field plate 141B is located on the third dielectric layer 152. For example... Figure 1 As shown, the second source field plate layer 141B and the first source field plate layer 141A overlap, that is, the projection of the second source field plate layer 141B on the semiconductor substrate 100 and the projection of the first source field plate layer 141A on the semiconductor substrate 100 have overlapping portions.

[0041] In some embodiments of this application, the second source field plate 141B may overlap with the gate metal electrode 110, that is, the projection of the second source field plate 141B on the semiconductor substrate 100 and the projection of the gate metal electrode 110 on the semiconductor substrate 100 have overlapping portions. In other embodiments of this application, the second source field plate 141B may not overlap with the gate metal electrode 110.

[0042] Please continue to refer to this. Figure 1 A fourth dielectric layer 153 is covered on the third dielectric layer 152. The fourth dielectric layer 153 can be a single-layer structure or a multi-layer stacked structure. The material of the fourth dielectric layer 153 may include, for example, silicon oxide, silicon nitride, etc.

[0043] The third source field layer 141C is located on the fourth dielectric layer 153. In this embodiment, the third source field layer 141C and the second source field layer 141B overlap, that is, the projections of the third source field layer 141C on the semiconductor substrate 100 and the projections of the second source field layer 141B on the semiconductor substrate 100 have overlapping portions. In other embodiments of this application, the third source field layer 141C and the second source field layer 141B may not overlap.

[0044] In this embodiment, a fifth dielectric layer 154 is covered on the fourth dielectric layer 153. The fifth dielectric layer 154 can be a single-layer structure or a multi-layer stacked structure. The material of the fifth dielectric layer 154 may include, for example, silicon oxide, silicon nitride, etc.

[0045] The high electron mobility transistor 10 further includes a first metal layer 160 and a second metal layer 161 located on the fifth dielectric layer 154, wherein the first metal layer 160 and the second metal layer 161 are located on the same photomask layer, for example, the first metal layer 160 and the second metal layer 161 can be formed by performing photolithography and etching processes on the same metal layer.

[0046] In this embodiment, the source field plate 140 further includes a fourth source field plate layer 141D, which is located in the same photomask layer as the first metal layer 160. The fourth source field plate layer 141D and the third source field plate layer 141C overlap, meaning that the projections of the fourth source field plate layer 141D onto the semiconductor substrate 100 and the projections of the third source field plate layer 141C onto the semiconductor substrate 100 have overlapping portions. In the direction horizontal to the semiconductor substrate 100, the fourth source field plate layer 141D is closer to the drain ohmic metal electrode 130 than the third source field plate layer 141C.

[0047] In this embodiment, the source field plate 140 includes a first source field plate layer 141A, a second source field plate layer 141B, a third source field plate layer 141C, and a fourth source field plate layer 141D. The second source field plate layer 141B overlaps with the first source field plate layer 141A, the third source field plate layer 141C, and the fourth source field plate layer 141D, and may also overlap with the gate metal electrode 110. The source field plate 140 can weaken the electric field near the gate structure and improve the breakdown voltage of the high electron mobility transistor 10.

[0048] like Figure 1As shown in the embodiment of this application, the first source field plate layer 141A, the second source field plate layer 141B, the third source field plate layer 141C, and the fourth source field plate layer 141D are separated by the third dielectric layer 152, the fourth dielectric layer 153, and the fifth dielectric layer 154, respectively.

[0049] like Figure 1 As shown, the first metal layer 160 is connected to the source ohmic metal electrode 120, and the second metal layer 161 is connected to the drain ohmic metal electrode 130. A fourth opening (not shown) may be formed in the fifth dielectric layer 154, extending through the fourth dielectric layer 153, the third dielectric layer 152, and the second dielectric layer 151 to expose the source ohmic metal electrode 120. The first metal layer 160 is connected to the source ohmic metal electrode 120 through the fourth opening. A fifth opening (not shown) may also be formed in the fifth dielectric layer 154, extending through the fourth dielectric layer 153, the third dielectric layer 152, and the second dielectric layer 151 to expose the drain ohmic metal electrode 130. The second metal layer 161 is connected to the drain ohmic metal electrode 130 through the fifth opening.

[0050] In this embodiment, the first metal layer 160 is also connected to the source field plate 140. Specifically, the first metal layer 160 is connected to each of the source field plate layers 141 of the source field plate 140. Here, the first metal layer 160 is connected to the first source field plate layer 141A, the second source field plate layer 141B, the third source field plate layer 141C, and the fourth source field plate layer 141D. The first metal layer 160 can be connected to each of the source field plate layers 141 of the source field plate 140 at the edge of the device to simplify the wiring structure.

[0051] In summary, the high electron mobility transistor 10 provided in this embodiment includes a source field plate 140, which comprises at least three source field plate layers 141, extending from near the semiconductor substrate 100 to away from the semiconductor substrate 100. The three source field plate layers 141 include a first source field plate layer 141A, a second source field plate layer 141B, and a third source field plate layer 141C. The distance h from the third source field plate layer 141C to the semiconductor substrate 100 is less than or equal to 600 nm. The source field plate 140 can adjust the electric field distribution, weaken the channel electric field near the gate and drain, and improve the breakdown voltage of the high electron mobility transistor 10.

[0052]

Example 2

[0053] Please refer to Figure 2 This is a schematic diagram of the high electron mobility transistor in Embodiment 2 of this utility model. Figure 2 As shown, the high electron mobility transistor 20 includes: a semiconductor substrate 200; a gate metal electrode 210, a source ohmic metal electrode 220, and a drain ohmic metal electrode 230 located on the semiconductor substrate 200; and a source field plate 240, the source field plate 240 including at least three source field plate layers 241, from near the semiconductor substrate 200 to away from the semiconductor substrate 200, the three source field plate layers 241 including a first source field plate layer 241A, a second source field plate layer 241B, and a third source field plate layer 241C, wherein the distance from the third source field plate layer 241C to the semiconductor substrate 200 is less than or equal to 600 nm.

[0054] The difference between this second embodiment and the first embodiment is that, in this second embodiment, the high electron mobility transistor 20 further includes a drain field plate 270, which includes a drain field plate layer 271. In some embodiments of this application, the drain field plate layer 271 and the second source field plate layer 241B may be located in the same photomask layer.

[0055] For example, in some embodiments of this application, a first dielectric layer 250, a second dielectric layer 251, a third dielectric layer 252, a fourth dielectric layer 253, and a fifth dielectric layer 254 are sequentially stacked on the semiconductor substrate 200. The first source field plate layer 241A is located on the second dielectric layer 251, and the first source field plate layer 241A, the second source field plate layer 241B, and the third source field plate layer 241C are separated by the third dielectric layer 252 and the fourth dielectric layer 253, respectively. In some embodiments of this application, the drain field plate layer 271 may be located in the same photomask layer as the second source field plate layer 241B, that is, the drain field plate layer 271 may be located on the third dielectric layer 252.

[0056] In some embodiments of this application, the drain field plate 271 may overlap with the drain ohmic metal electrode 230, that is, the projection of the drain field plate 271 on the semiconductor substrate 200 and the projection of the drain ohmic metal electrode 230 on the semiconductor substrate 200 have overlapping portions.

[0057] Please continue to refer to this. Figure 2In some embodiments of this application, the high electron mobility transistor 20 further includes a first metal layer 260 and a second metal layer 261 located on the fifth dielectric layer 254. Here, the first metal layer 260 and the second metal layer 261 are located on the same photomask layer, for example, by performing photolithography and etching processes on the same metal layer to form the first metal layer 260 and the second metal layer 261.

[0058] In this embodiment, the source field plate 240 further includes a fourth source field plate layer 241D, which is located in the same photomask layer as the first metal layer 260. The fourth source field plate layer 241D and the third source field plate layer 241C overlap, meaning that the projections of the fourth source field plate layer 241D onto the semiconductor substrate 200 and the projections of the third source field plate layer 241C onto the semiconductor substrate 200 have overlapping portions. In the direction horizontal to the semiconductor substrate 200, the fourth source field plate layer 241D is closer to the drain ohmic metal electrode 230 than the third source field plate layer 241C.

[0059] The first metal layer 260 is connected to the source ohmic metal electrode 220, and the second metal layer 261 is connected to the drain ohmic metal electrode 230. The first metal layer 260 is also connected to the source field plate 240, and the second metal layer 261 is also connected to the drain field plate 270. The first metal layer 260 and the second metal layer 261 can be connected to the source field plate 240 and the drain field plate 270 respectively at the edge of the device.

[0060] In the high electron mobility transistor 20 provided in this embodiment of the invention, not only can the electric field distribution be adjusted through the source field plate 240 to weaken the channel electric field near the gate and drain, but the electric field distribution can also be adjusted through the drain field plate 270, thereby further improving the breakdown voltage of the high electron mobility transistor 20. Wherein, the parts not described in this embodiment two can be referred to in embodiment one, and will not be repeated here.

[0061]

Example 3

[0062] Please refer to Figure 3 This is a schematic diagram of the high electron mobility transistor in Embodiment 3 of this utility model. Figure 3As shown, the high electron mobility transistor 30 includes: a semiconductor substrate 300; a gate metal electrode 310, a source ohmic metal electrode 320, and a drain ohmic metal electrode 330 located on the semiconductor substrate 300; and a source field plate 340, the source field plate 340 including at least three source field plate layers 341, from near the semiconductor substrate 300 to away from the semiconductor substrate 300, the three source field plate layers 341 including a first source field plate layer 341A, a second source field plate layer 341B, and a third source field plate layer 341C, wherein the distance from the third source field plate layer 341C to the semiconductor substrate 300 is less than or equal to 600 nm.

[0063] The difference between this third embodiment and the first embodiment is that, in the first embodiment, the source ohmic metal electrode 120 and the drain ohmic metal electrode 130 are formed before the first source field plate layer 141A. The second dielectric layer 151 covers the source ohmic metal electrode 120 and the drain ohmic metal electrode 130, and the first source field plate layer 141A is located on the second dielectric layer 151, with its surface higher than the surfaces of the source ohmic metal electrode 120 and the drain ohmic metal electrode 130. In this third embodiment, the first source field plate layer 341A is formed before the source ohmic metal electrode 320 and the drain ohmic metal electrode 330, and the first source field plate layer 341A may be located one or more layers before the source ohmic metal electrode 320 and the drain ohmic metal electrode 330.

[0064] like Figure 3 As shown, in some embodiments of this application, a first dielectric layer 350 is covered on the semiconductor substrate 300, and the first dielectric layer 350 exposes the gate structure 303. The gate metal electrode 310 is connected to the exposed gate structure 303, and the first source field plate layer 341A is located on the first dielectric layer 350, and the first source field plate layer 341A and the gate structure 303 may be located in the same photomask layer.

[0065] A second dielectric layer 351 is disposed on the first dielectric layer 350, and the second dielectric layer 351 covers the gate metal electrode 310 and the first source field plate layer 341A. In some embodiments of this application, the second source field plate layer 341B is located on the second dielectric layer 351.

[0066] In this embodiment, a third dielectric layer 352 covers the second dielectric layer 351, and the third dielectric layer 352 covers the second source field plate layer 341B, exposing the source region 301 and the drain region 302. The source ohmic metal electrode 320 is connected to the source region 301, and the drain ohmic metal electrode 330 is connected to the drain region 302. The source ohmic metal electrode 320 and the drain ohmic metal electrode 330 may be located in the same photomask layer. The source ohmic metal electrode 320 and the drain ohmic metal electrode 330 pass through the first dielectric layer 350, the second dielectric layer 351, and the third dielectric layer 352, respectively, and are connected to the source region 301 and the drain region 302.

[0067] Please continue to refer to this. Figure 3 In this embodiment, a fourth dielectric layer 353 covers the third dielectric layer 352, and the fourth dielectric layer 353 covers the source ohmic metal electrode 320 and the drain ohmic metal electrode 330. The third source field plate layer 341C is located on the fourth dielectric layer 353. A fifth dielectric layer 354 covers the fourth dielectric layer 353, and the source field plate 340 further includes a fourth source field plate layer 341D, which is located on the fifth dielectric layer 354.

[0068] In Embodiment 3 of this application, the first source field plate layer 341A is formed before the source ohmic metal electrode 320 and the drain ohmic metal electrode 330. The surface of the first source field plate layer 341A is lower than the surfaces of the source ohmic metal electrode 320 and the drain ohmic metal electrode 330, which can further reduce the distance between the source field plate 340 and the semiconductor substrate 300, thereby further adjusting the electric field distribution, weakening the channel electric field near the gate and drain, and improving the breakdown voltage of the high electron mobility transistor.

[0069] In this embodiment, the high electron mobility transistor 30 further includes a first metal layer 360 and a second metal layer 361 located on the fifth dielectric layer 354. Here, the first metal layer 360, the second metal layer 361, and the fourth source field plate layer 341D can be located in the same photomask layer.

[0070] In this embodiment, the first metal layer 360 is connected to the source ohmic metal electrode 320, and the second metal layer 361 is connected to the drain ohmic metal electrode 330. The first metal layer 360 is also connected to the source field plate 340. In other embodiments of this application, the high electron mobility transistor 30 may further include a drain field plate, and the second metal layer 361 is also connected to the drain field plate.

[0071] In the high electron mobility transistor 30 provided in this embodiment of the present invention, the high electron mobility transistor 30 includes a source field plate 340, which includes at least three source field plate layers 341, arranged from near the semiconductor substrate 300 to away from the semiconductor substrate 300. The three source field plate layers 341 include a first source field plate layer 341A, a second source field plate layer 341B, and a third source field plate layer 341C. The distance from the third source field plate layer 341C to the semiconductor substrate 300 is less than or equal to 600 nm. The source field plate 340 can adjust the electric field distribution, weaken the channel electric field near the gate and drain, and improve the breakdown voltage of the high electron mobility transistor 30. For parts not described in this embodiment three, please refer to embodiments one and two accordingly; these will not be repeated in this embodiment three.

[0072] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.

[0073] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A high electron mobility transistor, characterized in that, The high electron mobility transistor includes: Semiconductor substrate; The gate metal electrode, source ohmic metal electrode, and drain ohmic metal electrode are located on the semiconductor substrate; and, A source field plate, comprising at least three source field plate layers, from near the semiconductor substrate to away from the semiconductor substrate, wherein the three source field plate layers include a first source field plate layer, a second source field plate layer and a third source field plate layer, wherein the distance of the third source field plate layer to the semiconductor substrate is less than or equal to 600 nm.

2. The high electron mobility transistor as described in claim 1, characterized in that, The first source field plate and the gate metal electrode are located in the same photomask layer.

3. The high electron mobility transistor as described in claim 2, characterized in that, The source ohmic metal electrode and the drain ohmic metal electrode are located in the same photomask layer; the first source field plate layer is located in front of the source ohmic metal electrode layer, or the first source field plate layer is located in the back of the source ohmic metal electrode layer.

4. The high electron mobility transistor as described in claim 1, characterized in that, The second source field plate layer and the first source field plate layer overlap.

5. The high electron mobility transistor as described in claim 4, characterized in that, The second source field plate layer also overlaps with the gate metal electrode and / or the third source field plate layer.

6. The high electron mobility transistor as claimed in claim 1, characterized in that, The high electron mobility transistor further includes a drain field plate, wherein the drain field plate comprises a drain field plate layer.

7. The high electron mobility transistor as described in claim 6, characterized in that, The drain field plate and the second source field plate are located in the same photomask layer.

8. The high electron mobility transistor according to any one of claims 1 to 7, characterized in that, The high electron mobility transistor further includes: a first metal layer and a second metal layer, wherein the first metal layer is connected to the source ohmic metal electrode and the source field plate, and the second metal layer is connected to the drain ohmic metal electrode.

9. The high electron mobility transistor as described in claim 8, characterized in that, The source field plate also includes a fourth source field plate layer, which is located in the same photomask layer as the first metal layer.

10. The high electron mobility transistor as claimed in claim 9, characterized in that, The fourth source field plate and the third source field plate overlap; in the direction horizontal to the semiconductor substrate, the fourth source field plate is closer to the drain ohmic electrode than the third source field plate.

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