Semiconductor device

Abstract

The utility model discloses a semiconductor device contains base, matrix area, drift area, source electrode area, drain electrode area, first dielectric structure, gate electrode, second dielectric structure and field plate. Matrix area has first conductive type, sets up in the base, and drift area has second conductive type, sets up in the base, and the lateral close matrix area. Source electrode area sets up in the matrix area, and drain electrode area sets up in the drift area. First dielectric structure sets up on the drift area, and the first side of first dielectric structure is close to drain electrode area. Gate electrode sets up on the matrix area, and a part of gate electrode extends to the second side and top surface of first dielectric structure along the first direction laterally. Second dielectric structure sets up above first dielectric structure, and field plate sets up on second dielectric structure, wherein field plate and gate electrode are separated a distance laterally in the first direction, and the overhead pattern of field plate has at least one gap.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and in particular to a semiconductor device with a transistor having a field plate. Background Technology

[0002] Bipolar-CMOS-DMOS (BCD) technology is the most commonly used power electronic component in power conversion systems. Laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors are power transistors with a horizontal current direction and a drift region between the gate and drain regions. The drift region is a lightly doped region with a lower doping concentration than the source and drain regions, used to avoid or suppress the high electric field between the source and drain regions. LDMOS field-effect transistors can be used to transmit high-frequency and high-power electrical signals, making them suitable for high-speed switching applications. However, to achieve faster switching speeds and lower switching losses, LDMOS field-effect transistors still require improvement in many aspects. Utility Model Content

[0003] In view of this, the purpose of this invention is to provide a semiconductor device suitable for laterally diffused metal-oxide-semiconductor field-effect transistors. This semiconductor device utilizes the planar layout and electrical coupling configuration of the field plate and gate electrode to reduce the total gate charge (Qg), achieving faster switching speeds and lower switching losses. Simultaneously, this semiconductor device can also utilize the dielectric stack beneath the field plate to maintain or increase the drain-source breakdown voltage (BVdss), making the semiconductor device more resistant to high voltages.

[0004] According to one embodiment, the present invention provides a semiconductor device including a substrate, a substrate region, a drift region, a source region, a drain region, a first dielectric structure, a gate electrode, a second dielectric structure, and a field plate. The substrate region has a first conductivity type and is disposed in the substrate. The drift region has a second conductivity type and is disposed in the substrate, laterally close to the substrate region. The source region is disposed in the substrate region, and the drain region is disposed in the drift region. The first dielectric structure is disposed on the drift region, and a first side of the first dielectric structure is close to the drain region. The gate electrode is disposed on the substrate region, and a portion of the gate electrode extends laterally along a first direction to a second side and a top surface of the first dielectric structure. The second dielectric structure is disposed above the first dielectric structure, and the field plate is disposed on the second dielectric structure, wherein the field plate and the gate electrode are laterally separated by a gap in the first direction, and the top view pattern of the field plate has at least one gap.

[0005] The field plate and the gate electrode are electrically isolated from each other, and the field plate is configured to be electrically coupled to a source / base voltage.

[0006] The top view of the panel includes a plurality of parallel strips that extend along a first direction and are spaced apart from each other in a second direction. At least one gap is located between two adjacent strips of the plurality of strips.

[0007] The top view of the panel also includes a connecting portion extending along the second direction, and the ends of the multiple strips on the same side are connected together via the connecting portion.

[0008] The plurality of strips includes a plurality of first strips and a plurality of second strips arranged alternately in the second direction, and in the first direction, the length of the plurality of first strips is greater than the length of the plurality of second strips.

[0009] The top view of the field plate also includes a connecting portion extending along the second direction, and the ends of the plurality of first strips and the plurality of second strips on the same side are connected together via the connecting portion.

[0010] The top view of the panel includes two strips and a connecting part. The two strips are parallel to each other and extend along the first direction. The ends of the two strips on the same side are connected together via the connecting part. In a second direction, the width of the gap between the two strips is greater than or equal to the sum of the widths of the two strips.

[0011] The dielectric constant of the second dielectric structure is higher than that of the first dielectric structure, and the thickness of the second dielectric structure is less than that of the first dielectric structure.

[0012] The invention also includes a third dielectric structure disposed between the first dielectric structure and the second dielectric structure, wherein the dielectric constants of the second dielectric structure, the third dielectric structure and the first dielectric structure decrease sequentially, and the thickness of each of the second dielectric structure and the third dielectric structure is less than the thickness of the first dielectric structure.

[0013] According to another embodiment, the present invention provides a semiconductor device, including: a substrate, a dielectric structure, a gate electrode, a source region, a drain region, and a field plate. The dielectric structure is disposed on the substrate, the gate electrode is disposed on the substrate, and a portion of the gate electrode covers the dielectric structure. Both the source region and the drain region are disposed within the substrate, wherein the gate electrode is located between the source region and the drain region, with the source region closer to the gate electrode and the drain region farther from the gate electrode. The field plate is disposed above the dielectric structure, wherein the field plate and the gate electrode are laterally separated by a gap in a first direction, and the top view of the field plate has at least one gap in a second direction, with the first direction perpendicular to the second direction. Attached Figure Description

[0014] To facilitate understanding, the accompanying drawings and detailed textual descriptions can be consulted while reading this utility model. Specific embodiments of this utility model are explained in detail with reference to the corresponding drawings, which also illustrate the working principle of these embodiments. Furthermore, for clarity, the features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0015] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0016] Figure 2 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0017] Figure 3 This is a top view of the gate electrode, field plate, first dielectric structure, and drain region of a semiconductor device according to another embodiment of the present invention.

[0018] Figure 4 , Figure 5 and Figure 6 This is a top view schematic diagram of the field plate and the first dielectric structure of a semiconductor device according to some other embodiments of the present invention.

[0019] Figure 7 and Figure 8 This is a cross-sectional schematic diagram of the drift region, drain region, dielectric stack, and field plate of a semiconductor device according to other embodiments of the present invention.

[0020] Explanation of reference numerals in the attached figures: 100 ~ Semiconductor device; 101 ~ Substrate; 103 ~ Substrate region; 105 ~ Drift region; 107 ~ Source region; 108 ~ Base region; 109 ~ Drain region; 110 ~ Gate dielectric layer; 111 ~ Gate electrode; 111FP ~ Partial; 113 ~ Field plate; 113-1, 113-2, 113-3, 113-4 ~ Strips; 113-5 ~ First strip; 113-6 ~ Second strip; 113C ~ Connector; 114-1, 114-2, 114-3, 114-4, 114-5, 114-6, 114-7 ~ Gap; 115 ~ Conductive contact; 120 ~ Dielectric stack; 121 ~ First dielectric structure; 121S1 ~ First side surface; 121S2 ~ Second side surface; 121T ~ Top surface; 122 ~ Second dielectric structure; 123 ~ Third dielectric structure; 124 ~ Fourth dielectric structure; 125 ~ Fifth dielectric structure; L, L1, L2, LC, L5, L6 ~ Length; P ~ Spacing; W ~ Distance; W1, W2, W3, W4, W5, W6, Ws ~ Width; Vs / b ~ Source / base voltage; Vgs ~ Gate-source voltage; Vds ~ Drain-source voltage; Cgs, Cgs1, Cgs2, Cgs3, Cgs4 ~ Gate-source capacitance; Cgd-1, Cgd-2 ~ Gate-drain capacitance; C FP C FP1 C FP2 C FP3 C FP4 ~Field plate capacitance; H, H1, H2, H3, H4~Height; A-A', B-B'~Cut lines of the cross section. Detailed Implementation

[0021] This utility model provides several different embodiments that can be used to implement different features of the utility model. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following description of "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," so that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this utility model may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate the relationship between different embodiments and / or configurations.

[0022] Furthermore, regarding spatially related descriptive terms mentioned in this utility model, such as "below," "low," "high," "below," "above," "above," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0023] Although this utility model uses terms such as "first," "second," and "third" to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this utility model, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0024] The terms "about" or "generally" used in this invention typically mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without a specific mention of "about" or "generally," the meaning of "about" or "substantially" may be implied.

[0025] Although the present invention is described below by way of specific embodiments, the principles of the present invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the present invention, certain details have been omitted, and these omitted details fall within the scope of knowledge of those skilled in the art.

[0026] This invention relates to a semiconductor device with a transistor having a slit-type field plate. Embodiments of this invention utilize a planar layout of the gate electrode and the field plate to reduce the area of ​​the gate electrode covering the first dielectric structure. Furthermore, the top view of the field plate shows a slit, thereby reducing the total gate charge (Qg) and achieving faster switching speeds and lower switching losses. Additionally, embodiments of this invention can utilize the dielectric stack beneath the field plate to maintain or increase the drain-source breakdown voltage (BVdss), enabling the semiconductor device to withstand high voltages.

[0027] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 100 according to an embodiment of the present invention. Figure 2 This is a top view schematic diagram of a semiconductor device 100 according to an embodiment of the present invention, wherein... Figure 1 For along Figure 2 The section tangent A-A' is drawn in the diagram. (See reference...) Figure 1 The semiconductor device 100 includes at least a substrate 101, a substrate region 103, a drift region 105, a source region 107, a base region 108, a drain region 109, a gate dielectric layer 110, a gate electrode 111, a first dielectric structure 121, a second dielectric structure 122, and a field plate 113. In some embodiments, the substrate 101 is, for example, a P-type substrate, a P-type epitaxial layer, or a combination thereof. Alternatively, the substrate 101 may also include a lightly doped N-type epitaxial layer disposed on the P-type substrate. The substrate region 103 has a first conductivity type, such as a P-type well region, and is disposed in the substrate 101. The drift region 105 has a second conductivity type, such as a lightly doped N-type well region, and is disposed in the substrate 101 and laterally adjacent to the substrate region 103. In one embodiment, the substrate region 103 may be laterally adjacent to the drift region 105. In another embodiment, the substrate region 103 may be laterally separated from the drift region 105, and a portion of the substrate 101 may be located between the substrate region 103 and the drift region 105. In some embodiments, the bottom surface of the substrate region 103 may be flush with or higher than the bottom surface of the drift region 105. The semiconductor device 100 of this invention is applicable to a bipolar-CMOS-DMOS integrated architecture (BCD architecture) composed of a bipolar transistor-complementary metal-oxide-semiconductor (CMOS) transistor-double-diffused metal-oxide-semiconductor (DMOS) transistor, and the configuration relationship of the substrate 101, the substrate region 103, and the drift region 105 can be adjusted according to various requirements of the semiconductor device 100, and is not limited to... Figure 1 The form.

[0028] See also Figure 1 Source region 107 and base region 108 are disposed in substrate region 103, wherein source region 107 has a second conductivity type, such as a heavily doped N-type region, and base region 108 has a first conductivity type, such as a heavily doped P-type region. In one embodiment, base region 108 may be laterally adjacent to source region 107, and both source region 107 and base region 108 are electrically coupled to source / base voltage Vs / b, such as a 0-volt ground voltage. Drain region 109 also has a second conductivity type, such as a heavily doped N-type region, and drain region 109 is disposed in drift region 105 and electrically coupled to drain-source voltage Vds. First dielectric structure 121 is disposed on drift region 105, and the first side 121S1 of the first dielectric structure 121 is close to drain region 109. A gate electrode 111 is disposed on the substrate region 103 and the drift region 105, and a portion 111FP of the gate electrode 111 extends laterally along a first direction (e.g., the X-axis direction) to the second side surface 121S2 and the top surface 121T of the first dielectric structure 121 (i.e., a portion 111FP covers a portion of the first dielectric structure 121), wherein the portion 111FP of the gate electrode 111 on the first dielectric structure 121 can serve as a field plate. A gate dielectric layer 110 is located between the gate electrode 111 and the substrate region 103, and between the gate electrode 111 and the drift region 105. Furthermore, both the first dielectric structure 121 and the gate electrode 111 are disposed on the substrate 101, and a portion 111FP of the gate electrode 111 covers the first dielectric structure 121. Both the source region 107 and the drain region 109 are disposed within the substrate 101, and the gate electrode 111 is located between the source region 107 and the drain region 109, with the source region 107 being closer to the gate electrode 111 and the drain region 109 being farther away from the gate electrode 111.

[0029] In one embodiment, the second dielectric structure 122 can be directly disposed on the first dielectric structure 121, and the field plate 113 is disposed on the second dielectric structure 122, wherein the field plate 113 and the gate electrode 111 are laterally separated by a distance P in the first direction (X-axis). In some embodiments, in the first direction, the distance P can be about 10% to about 20% of the length L1 of the first dielectric structure 121. Furthermore, according to embodiments of the present invention, the field plate 113 has at least one slit in its top view on the XY plane, as will be discussed laterally. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6As shown. The top view of the field plate 113 shows at least one slit in the second direction (Y-axis), and the first direction is perpendicular to the second direction. Furthermore, in the semiconductor device 100 of this invention, the field plate 113 and the gate electrode 111 are electrically isolated from each other, and the field plate 113 is configured to be electrically coupled to the source / base voltage Vs / b, thereby reducing the total gate charge (Qg). In some embodiments, the gate electrode 111 may be composed of polycrystalline silicon, and the field plate 113 may be composed of a metallic material used to create conductive contacts, such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), combinations thereof, other alloys, or metal silicides.

[0030] like Figure 1 As shown, the gate electrode 111 is electrically coupled to the gate-source voltage Vgs. A gate-source capacitance Cgs is generated between the gate electrode 111 and the substrate region 103. A gate-drain capacitance Cgd-1 is generated between the gate electrode 111 and the drift region 105, and another gate-drain capacitance Cgd-2 is generated between a portion 111FP of the gate electrode 111 and the drift region 105. The total gate charge (Qg) is proportional to the gate capacitance (Cgg), and the gate capacitance (Cgg) is equal to the sum of the gate-source capacitance Cgs, the gate-drain capacitance Cgd-1, and the other gate-drain capacitance Cgd-2. According to embodiments of the present invention, the length L2 of a portion 111FP of the gate electrode 111 in the first direction (X-axis) can be reduced to approximately 10% to approximately 20% of the length L1 of the first dielectric structure 121, whereas the length of the portion of the existing gate field plate covering the dielectric structure in the first direction is typically at least 50% greater than the length of the dielectric structure. Therefore, compared to the planar configuration of existing gate field plates, embodiments of the present invention can significantly reduce the gate capacitance (Cgg), particularly the sum of the gate-drain capacitance, thereby effectively reducing the total gate charge (Qg), enabling the semiconductor device 100 to achieve faster switching speeds and lower switching losses. Furthermore, according to embodiments of the present invention, the field plate 113 and the gate electrode 111 are electrically isolated from each other, thus preventing the generation of gate-drain capacitance (Cgd) between the field plate 113 and the drift region 105, further reducing the total gate charge (Qg), which is beneficial for high-frequency, high-speed switching applications of the semiconductor device 100.

[0031] In addition, such as Figure 1As shown, in one embodiment, a third dielectric structure 123 and a fourth dielectric structure 124 may be disposed between the first dielectric structure 121 and the second dielectric structure 122, wherein the dielectric constants of the second dielectric structure 122, the third dielectric structure 123, and the fourth dielectric structure 124 may be higher than the dielectric constant of the first dielectric structure 121. In another embodiment, the dielectric constants of the second dielectric structure 122, the fourth dielectric structure 124, the third dielectric structure 123, and the first dielectric structure 121 decrease sequentially. Furthermore, the thicknesses of the second dielectric structure 122, the third dielectric structure 123, and the fourth dielectric structure 124 are all less than the thickness of the first dielectric structure 121. In some embodiments, the first dielectric structure 121 is composed of, for example, silicon dioxide (SiO2), the second dielectric structure 122 is composed of, for example, silicon nitride (Si3N4), and the third dielectric structure 123 and the fourth dielectric structure 124 are composed of, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), zirconium oxide (ZrO2), or silicon oxynitride (SiON), but are not limited thereto. Furthermore, in some embodiments, the total thickness of the first dielectric structure 121, the second dielectric structure 122, the third dielectric structure 123, and the fourth dielectric structure 124 in the Z-axis direction may be approximately 500 nm to 1000 nm, and the thickness of the first dielectric structure 121 may be at least 50% of the total thickness.

[0032] Furthermore, in the XY plane, the vertical projected area of ​​the first dielectric structure 121 is larger than the vertical projected area of ​​the field plate 113. The top view pattern of the second dielectric structure 122 overlaps with and is vertically aligned with the top view pattern of the field plate 113. The second dielectric structure 122 can serve as an etch stop layer when fabricating the field plate 113. In some embodiments, the top view patterns of the third dielectric structure 123 and the fourth dielectric structure 124 may also overlap with and be vertically aligned with the top view pattern of the field plate 113, and the vertical projected area of ​​the first dielectric structure 121 is larger than the vertical projected area of ​​each of the third dielectric structure 123 and the fourth dielectric structure 124. In one embodiment, multiple dielectric material layers and metal material layers deposited on the first dielectric structure 121 can be etched and patterned together to simultaneously form the second dielectric structure 122, the third dielectric structure 123, the fourth dielectric structure 124, and the field plate 113. Furthermore, according to some embodiments of the present invention, the dielectric stack below the field plate 113 can be adjusted, for example, by adjusting the number of dielectric layers, the dielectric constant of each dielectric structure, and / or the thickness of each dielectric structure stacked between the field plate 113 and the first dielectric structure 121, thereby maintaining or increasing the drain-source breakdown voltage (BVdss), making the semiconductor device 100 more resistant to high voltage.

[0033] See Figure 2In one embodiment, in the XY plane, the top view of the field plate 113 includes a plurality of parallel strips 113-1, 113-2, 113-3, and 113-4, all extending along a first direction (X-axis) and spaced apart from each other in a second direction (Y-axis). A plurality of gaps 114-1, 114-2, and 114-3 are located between two adjacent strips. In the first direction (X-axis), the length L of the strips 113-1, 113-2, 113-3, and 113-4 may all be the same. In the second direction (Y-axis), the widths W1, W2, W3, and W4 of the strips 113-1, 113-2, 113-3, and 113-4 may all be the same or different from each other. Furthermore, there is a distance W between the outermost boundaries of these strips (i.e., the uppermost side of strip 113-1 and the lowermost side of strip 113-4), and the sum of the widths W1, W2, W3, and W4 of these strips is approximately 10% to approximately 50% of this distance W. In the second direction (Y-axis), the widths of these slits 114-1, 114-2, and 114-3 may all be the same or different from each other. Additionally, the area of ​​the first dielectric structure 121 covered by the gate electrode 111 accounts for approximately 10% to approximately 20% of the total area of ​​the first dielectric structure 121.

[0034] Furthermore, these strips 113-1, 113-2, 113-3, and 113-4 can generate their own gate-source capacitances Cgs1, Cgs2, Cgs3, and Cgs4 with the gate electrode 111, the sum of which is Cgs'. In a comparative example, when the metal field plate has no gaps and the length of the metal field plate is L and the width is W, a gate-source capacitance Cgs can be generated between the metal field plate and the gate electrode in the comparative example. Since the top view of the field plate 113 of this invention has gaps 114-1, 114-2 and 114-3, the total effective capacitance area of ​​the field plate 113 of this invention is smaller than the effective capacitance area of ​​the metal field plate of the comparative example. This makes the total gate-source capacitance Cgs' generated between the gap-type field plate 113 of this invention and the gate electrode 111 smaller than the gate-source capacitance Cgs generated between the metal field plate and the gate electrode of the comparative example. This reduces the total gate charge (Qg) of the semiconductor device 100 of this invention, achieving faster switching speed and lower switching loss.

[0035] In addition, such as Figure 2As shown, multiple conductive contacts 115 are formed on the source region 107, base region 108, drain region 109 and gate electrode 111. The field plate 113 of this invention can be fabricated using the metal material that forms these conductive contacts 115, and simultaneously through the same deposition and patterning process. Therefore, the fabrication of the field plate 113 of this invention does not require increasing the number of photomasks and process steps, thereby saving the manufacturing cost and time of the semiconductor device 100.

[0036] Figure 3 This is a top view of the gate electrode 111, field plate 113, first dielectric structure 121, and drain region 109 of a semiconductor device 100 according to another embodiment of the present invention. To make the diagram clear and easy to understand, some features of the semiconductor device 100 are shown below. Figure 3 Not shown in the drawing, please refer to the above. Figure 1 and Figure 2 The relevant explanations will not be repeated here. For example... Figure 3 As shown, in some embodiments, the top view of the field plate 113 includes strips 113-1, 113-2, and 113-3, and a connecting portion 113-C extending along a second direction (Y-axis). The ends of strips 113-1, 113-2, and 113-3 on the same side (right side) are connected together via the connecting portion 113-C. Multiple gaps 114-1 and 114-2 are each located between two adjacent strips of these strips 113-1, 113-2, and 113-3. The connecting portion 113-C is located near the drain region 109 and away from the gate electrode 111, thereby increasing the breakdown voltage (BV) of the semiconductor device 100. Figure 3 The top view of the panel 113 is illustrated using three strips, two gaps, and a connecting part as an example, but it is not limited thereto. In other embodiments, the panel 113 may also include more than three strips and a corresponding number of gaps and connecting parts. For example, it can be... Figure 2 The four strips 113-1, 113-2, 113-3, and 113-4 are connected together by a connecting portion 113-C. Furthermore, in some embodiments, in the first direction (X-axis), the length L of these strips 113-1, 113-2, and 113-3 may all be the same. In the second direction (Y-axis), the widths W1, W2, and W3 of these strips 113-1, 113-2, and 113-3 may all be the same or different from each other, and the widths of the gaps 114-1 and 114-2 may also be the same or different. Additionally, in the second direction (Y-axis), the connecting portion 113-C has a length LC, and the sum of the widths W1, W2, and W3 of these strips may be from approximately 10% to approximately 50% of the length LC.

[0037] Figure 4 , Figure 5 and Figure 6This is a top view schematic diagram of the field plate 113 and the first dielectric structure 121 of the semiconductor device 100 according to other embodiments of the present invention. To make the drawings clear and easy to understand, some features of the semiconductor device 100 are shown below. Figure 4 , Figure 5 and Figure 6 Not shown in the drawing, please refer to the above. Figure 1 , Figure 2 and Figure 3 The relevant explanations will not be repeated here. For example... Figure 4 As shown, in one embodiment, the top view of the field plate 113 includes a plurality of first strips 113-5 and a plurality of second strips 113-6 arranged alternately in a second direction (Y-axis), and a plurality of gaps 114-4, 114-5, 114-6 and 114-7 are respectively located between adjacent first strips 113-5 and second strips 113-6. In the first direction (X-axis), the length L5 of these first strips 113-5 is greater than the length L6 of these second strips 113-6. In the second direction (Y-axis), the width W5 of these first strips 113-5 and the width W6 of these second strips 113-6 may be the same or different. Additionally, there is a distance W between the uppermost first strip 113-5 and the lowermost first strip 113-5, and the sum of the widths W5 of the first strips 113-5 and W6 of the second strips 113-6 is approximately 10% to approximately 50% of this distance W. Alternatively, it is also possible to... Figure 3 A shorter strip is inserted between the long strips 113-1, 113-2, and 113-3 of the field plate 113, and then removed. Figure 3 The connecting part 113-C.

[0038] like Figure 5 As shown, in one embodiment, Figure 4 The top view of the field plate 113 may also include a connecting portion 113-C extending along the second direction (Y-axis), and the ends of the first strips 113-5 and the second strips 113-6 on the same side (right side) are connected together via the connecting portion 113-C. Figure 5 For details of other features of the field plate 113, please refer to the foregoing. Figure 3 and Figure 4 The relevant explanations will not be repeated here.

[0039] like Figure 6As shown, in one embodiment, the top view of the field plate 113 may include two parallel strips 113-1 and 113-2 extending along a first direction (X-axis), and a connecting portion 113-C. The right ends of the two strips 113-1 and 113-2 are connected together via the connecting portion 113-C, and a gap 114-1 is located between the strips 113-1 and 113-2. In the first direction (X-axis), the lengths of the two strips 113-1 and 113-2 may be the same or different, and in the second direction (Y-axis), the width W1 of strip 113-1 and the width W2 of strip 113-2 may also be the same or different. Additionally, in the second direction (Y-axis), the connecting portion 113-C has a length LC, and the sum of the width W1 of the strip 113-1 and the width W2 of the strip 113-2 can be approximately 10% to approximately 50% of the length LC, and the width Ws of the gap 114-1 can be greater than or equal to the sum of the widths W1 and W2. Furthermore, in one embodiment, as... Figure 6 As shown, strips 113-1 and 113-2 can be connected to the sides of the two ends of the connecting portion 113-C, respectively. In another embodiment, strips 113-1 and 113-2 can also be connected to the same side of the middle region of the connecting portion 113-C, thereby reducing the width Ws of the gap 114-1. Figure 6 For details of other features of the field plate 113, please refer to the foregoing. Figure 2 and Figure 3 The relevant explanations will not be repeated here.

[0040] Figure 7 and Figure 8 This is a cross-sectional schematic diagram of the drift region 105, drain region 109, dielectric stack 120, and field plate 113 of the semiconductor device 100 according to other embodiments of the present invention. Figure 7 and Figure 8 It is along Figure 2 The cross-sectional tangent line B-B' is drawn in the diagram. To make the diagram clear and easy to understand, some features of the semiconductor device 100 are shown in... Figure 7 and Figure 8 Not shown in the drawing, please refer to the above. Figure 1 Please refer to the relevant explanations. Figure 7 In one embodiment, the field plate 113 includes a plurality of parallel strips 113-1, 113-2, 113-3, and 113-4 separated by gaps. The dielectric stack 120 includes a first dielectric structure 121, a third dielectric structure 123, a fourth dielectric structure 124, and a second dielectric structure 122 stacked sequentially from bottom to top. The bottom surfaces of these strips 113-1, 113-2, 113-3, and 113-4 are all at the same height from the bottom surface of the first dielectric structure 121, for example, all at a height H, so that the field plate capacitance C between these strips 113-1, 113-2, 113-3, and 113-4 and the drift region 105 is equal.FP All are the same. Field plate capacitance C FP The field plate capacitance C is mainly controlled by the height H of the dielectric stack 120, and can also be increased by adjusting the number of dielectric structure layers, the thickness of each dielectric structure, and the dielectric constant of the dielectric stack 120. FP This improves the breakdown voltage of the semiconductor device 100. In this embodiment, the top surfaces of these strips 113-1, 113-2, 113-3 and 113-4 are at the same horizontal height, so the field plate 113 has good flatness and is easy to manufacture.

[0041] See Figure 8 In another embodiment, the field plate 113 includes a plurality of strips 113-1, 113-2, 113-3 and 113-4 that are parallel to each other and separated by gaps. The dielectric stack 120 includes a first dielectric structure 121, a second dielectric structure 122, a third dielectric structure 123, a fourth dielectric structure 124 and a fifth dielectric structure 125. The heights between the bottom surfaces of these strips 113-1, 113-2, 113-3 and 113-4 and the bottom surface of the first dielectric structure 121 may be different, for example, heights H1, H2, H3 and H4. Specifically, a second dielectric structure 122, a third dielectric structure 123, and a fourth dielectric structure 124 are stacked between strip 113-1 and the first dielectric structure 121; a second dielectric structure 122 and a third dielectric structure 123 are stacked between strip 113-2 and the first dielectric structure 121; a second dielectric structure 122 and a fourth dielectric structure 124 are stacked between strip 113-3 and the first dielectric structure 121; and a second dielectric structure 122, a third dielectric structure 123, and a fifth dielectric structure 125 are stacked between strip 113-4 and the first dielectric structure 121. This allows the field plate capacitance between each of these strips 113-1, 113-2, 113-3, and 113-4 and the drift region 105 to be different, for example, a field plate capacitance C. FP1 C FP2 C FP3 and C FP4 In this embodiment, the dielectric stack 120 below these strips 113-1, 113-2, 113-3 and 113-4 can be adjusted according to the electric field intensity distribution below the field plate 113 to optimize the field plate capacitance, thereby meeting the requirements of semiconductor devices for different breakdown voltages. This is applicable to high-voltage component applications and increases the process tolerance when manufacturing semiconductor devices.

Claims

1. A semiconductor device, characterized in that, include: One base; A substrate region having a first conductivity type is disposed in the substrate; A drift region having a second conductivity type is disposed in the substrate and is laterally close to the substrate region; A source pole region is disposed in the substrate region; A single absorption pole region is set within this drift region; A first dielectric structure is disposed on the drift region, and a first side of the first dielectric structure is close to the drain region; A gate electrode is disposed on the substrate region, and a portion of the gate electrode extends laterally along a first direction to a second side surface and a top surface of the first dielectric structure. A second dielectric structure is disposed above the first dielectric structure; as well as A field plate is disposed on the second dielectric structure, wherein the field plate and the gate electrode are laterally spaced apart by a distance in the first direction, and a top view of the field plate has at least one gap.

2. The semiconductor device as claimed in claim 1, characterized in that, The field plate and the gate electrode are electrically isolated from each other, and the field plate is configured to be electrically coupled to a source / base voltage.

3. The semiconductor device as claimed in claim 1, characterized in that, The top view of the panel includes a plurality of parallel strips that extend along the first direction and are spaced apart from each other in a second direction, with at least one gap located between two adjacent strips.

4. The semiconductor device as claimed in claim 3, characterized in that, The top view of the panel also includes a connecting portion extending along the second direction, and the ends of the plurality of strips on the same side are connected together via the connecting portion.

5. The semiconductor device as claimed in claim 3, characterized in that, The plurality of strips includes a plurality of first strips and a plurality of second strips arranged alternately in the second direction, and in the first direction, the length of the plurality of first strips is greater than the length of the plurality of second strips.

6. The semiconductor device as claimed in claim 5, characterized in that, The top view of the panel also includes a connecting portion extending along the second direction, and the ends of the plurality of first strips and the plurality of second strips on the same side are connected together via the connecting portion.

7. The semiconductor device as claimed in claim 1, characterized in that, The top view of the panel includes two strips and a connecting part. The two strips are parallel to each other and extend along the first direction. The ends of the two strips on the same side are connected together via the connecting part. In a second direction, the width of the gap between the two strips is greater than or equal to the sum of the widths of the two strips.

8. The semiconductor device as claimed in claim 1, characterized in that, The dielectric constant of the second dielectric structure is higher than that of the first dielectric structure, and the thickness of the second dielectric structure is less than that of the first dielectric structure.

9. The semiconductor device as claimed in claim 1, characterized in that, It also includes a third dielectric structure disposed between the first dielectric structure and the second dielectric structure, wherein the dielectric constants of the second dielectric structure, the third dielectric structure and the first dielectric structure decrease sequentially, and the thickness of the second dielectric structure and the third dielectric structure is less than the thickness of the first dielectric structure.

10. A semiconductor device, characterized in that, include: One base; A dielectric structure is disposed on the substrate; A gate electrode is disposed on the substrate, and a portion of the gate electrode covers the dielectric structure; A source region and a drain region are both disposed within the substrate, wherein the gate electrode is located between the source region and the drain region, and the source region is close to the gate electrode, while the drain region is far from the gate electrode. as well as A field plate is disposed above the dielectric structure, wherein the field plate and the gate electrode are laterally separated by a gap in a first direction, and a top view of the field plate has at least one gap in a second direction, and the first direction is perpendicular to the second direction.

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