Double-top-corner rounding structure and power semiconductor device
Patent Information
- Application Number
- CN202522218212.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-21
- Publication Date
- 2026-10-09
- Estimated Expiration
- 2035-10-21
AI Technical Summary
电场集中不仅会显著增加栅极氧化层的电场强度，导致栅氧可靠性下降，还可能诱发局部击穿或漏电流异常，进而影响IGBT的静态与动态电学特性，如阈值电压漂移、关断损耗增大，甚至引发早期失效
本申请第一方面提供的双顶角圆化结构，通过在硅衬底与沟槽顶部过渡区域设置第一圆角结构，并在栅极结构的顶角处形成第二圆角结构，有效缓解了传统沟槽栅IGBT中因直角顶角引起的局部电场集中问题。该设计显著降低了栅极氧化层在高电场应力下的峰值电场强度，从而提升了栅氧的可靠性与器件整体的耐压能力；同时，圆化结构有助于改善载流子分布均匀性，减少漏电流和界面态密度，进一步优化器件的静态特性（如导通压降、阈值电压稳定性）和动态性能（如开关速度与关断损耗）。综上，该双顶角圆化结构在不显著增加工艺复杂度的前提下，有效兼顾了高耐压、低损耗与高可靠性，为高性能功率半导体器件的开发提供了关键技术支撑。
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Figure CN224844610U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, specifically relating to a double-vertex rounded structure and a power semiconductor device. Background Technology
[0002] Insulated-gate bipolar transistors (IGBTs), as core components in power semiconductor devices, are widely used in new energy vehicles, rail transportation, industrial frequency conversion, smart grids, and renewable energy fields due to their combination of the high input impedance of MOSFETs and the low on-state voltage drop of bipolar transistors. However, with the increasing demands on device performance in power electronic systems, IGBTs face continuous technical challenges in terms of high voltage withstand capability, low loss, high reliability, and high integration.
[0003] Currently, IGBT gate structures are mainly divided into two types: planar gate and trench gate. Compared to planar gate structures, trench gate IGBTs, by embedding the gate inside the silicon substrate, effectively shorten the carrier injection path, reduce the on-state voltage drop, and improve current density and switching performance, thus offering greater advantages in medium- and high-power applications. However, in the manufacturing process of trench gate IGBTs, a deep and narrow trench structure is typically formed on the silicon substrate using a dry etching process. This process often creates a near 90° right-angle vertex structure at the top edge of the trench.
[0004] This right-angled apex structure is prone to causing local electric field concentration during device operation, especially under high electric field stress conditions. Electric field concentration not only significantly increases the electric field strength of the gate oxide layer, leading to a decrease in gate oxide reliability, but may also induce local breakdown or abnormal leakage current, thereby affecting the static and dynamic electrical characteristics of the IGBT, such as threshold voltage drift, increased turn-off loss, and even premature failure. Utility Model Content
[0005] The technical problem to be solved by this application is to provide a double-vertex rounded structure and a power semiconductor device, which significantly reduces the peak electric field intensity of the gate oxide layer under high electric field stress, thereby improving the reliability of the gate oxide and the overall withstand voltage capability of the device.
[0006] In a first aspect, this application provides a double-corner rounded structure and a power semiconductor device, comprising: a first rounded corner structure disposed at the top transition between the surface of a silicon substrate and the trench structure, and a second rounded corner structure disposed at the top corner of a gate structure.
[0007] Optionally, the radius of curvature of the first rounded corner structure is 5nm~100nm.
[0008] Optionally, the linewidth of the trench structure is 0.2μm to 2μm, and the depth is 2μm to 30μm.
[0009] Optionally, the radius of curvature of the second rounded corner structure is 5nm~100nm.
[0010] Optionally, the radius of curvature of the second rounded corner structure is equal to the radius of curvature of the first rounded corner structure.
[0011] Optionally, the top of the gate structure is 5nm to 200nm above the surface of the silicon substrate.
[0012] In a second aspect, this application provides a power semiconductor device including a silicon substrate having a trench structure, the trench structure being filled with polysilicon to form a gate structure, the inner wall of the trench structure having a gate oxide layer for isolating the silicon substrate from the gate structure, and the power semiconductor device further including the double-vertex rounded structure as described above.
[0013] Optionally, the thickness of the gate oxide layer is 20nm~150nm.
[0014] Optionally, the top of the gate oxide layer is located no more than 10 nm below the first rounded corner structure.
[0015] The beneficial effects of this application are: The double-corner rounded structure provided in the first aspect of this application effectively alleviates the problem of local electric field concentration caused by right-angled corners in traditional trench gate IGBTs by setting a first rounded corner structure in the transition region between the silicon substrate and the top of the trench, and forming a second rounded corner structure at the corner of the gate structure. This design significantly reduces the peak electric field intensity of the gate oxide layer under high electric field stress, thereby improving the reliability of the gate oxide and the overall breakdown voltage capability of the device. At the same time, the rounded structure helps to improve the uniformity of carrier distribution, reduce leakage current and interface state density, and further optimize the static characteristics (such as on-state voltage drop and threshold voltage stability) and dynamic performance (such as switching speed and turn-off loss) of the device. In summary, this double-corner rounded structure effectively balances high breakdown voltage, low loss and high reliability without significantly increasing process complexity, providing key technical support for the development of high-performance power semiconductor devices.
[0016] The power semiconductor device provided in the second aspect of this application is based on a trench gate structure design and integrates the aforementioned double-vertical-corner rounded structure. This effectively alleviates the problem of electric field concentration caused by right-angle vertices in traditional trench gate devices. Especially in the high-voltage off state, it can significantly reduce the peak electric field intensity of the gate oxide layer at the inner and outer corners of the top of the trench, thereby suppressing failure mechanisms such as gate oxide breakdown, abnormal leakage current, and threshold voltage drift, and significantly improving the uniformity and reliability of the electric field distribution of the device. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the double-vertex rounded structure of the power semiconductor device provided in the embodiments of this application; Figure 2 A schematic diagram of the unrounded top corners of the trench structure on the silicon substrate provided in an embodiment of this application; Figure 3 The above is a simulation test diagram of a power semiconductor device provided in the embodiments of this application.
[0018] In the figure: 100, silicon substrate; 110, trench structure; 120, first rounded corner structure; 200, gate structure; 210, second rounded corner structure; 300, gate oxide layer. Detailed Implementation
[0019] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0020] Firstly, such as Figure 1-2 As shown, the present application provides a double-corner rounded structure, including: a first rounded corner structure 120 disposed at the top transition between the surface of the silicon substrate 100 and the trench structure 110, and a second rounded corner structure 210 disposed at the top corner of the gate structure 200.
[0021] The double-corner rounded structure provided in the first aspect of this application effectively alleviates the problem of local electric field concentration caused by right-angled corners in traditional trench gate IGBTs by setting a first rounded corner structure 120 in the transition region between the silicon substrate 100 and the top of the trench, and forming a second rounded corner structure 210 at the corner of the gate structure 200. This design significantly reduces the peak electric field intensity of the gate oxide layer 300 under high electric field stress, thereby improving the reliability of the gate oxide and the overall breakdown voltage capability of the device. At the same time, the rounded structure helps to improve the uniformity of carrier distribution, reduce leakage current and interface state density, and further optimize the static characteristics (such as on-state voltage drop and threshold voltage stability) and dynamic performance (such as switching speed and turn-off loss) of the device. In summary, this double-corner rounded structure effectively balances high breakdown voltage, low loss and high reliability without significantly increasing process complexity, providing key technical support for the development of high-performance power semiconductor devices.
[0022] In one possible implementation, the radius of curvature of the first rounded corner structure 120 is 5 nm to 100 nm. For example, the radius of curvature of the first rounded corner structure 120 can be any typical but non-limiting point value or a range between any two points, such as 5 nm, 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 80 nm, or 100 nm. In this case, it is sufficient to effectively alleviate the electric field concentration effect caused by the sharp right angle formed at the top of the trench due to dry etching, without significantly encroaching on the effective active area of the device or affecting the structural integrity of the trench gate due to excessively large rounded corners.
[0023] In one possible implementation, the trench structure 110 has a linewidth of 0.2 μm to 2 μm and a depth of 2 μm to 30 μm. For example, the linewidth of the trench structure 110 can be any typical but non-limiting value, such as 0.2 μm, 0.5 μm, 1.0 μm, 1.5 μm, or 2 μm, or a range between any two such values. The depth of the trench structure 110 can be any typical but non-limiting value, such as 2 μm, 5 μm, 10 μm, 15 μm, 20 μm, or 30 μm, or a range between any two such values. In this case, the high voltage withstand capability and high current density requirements of power semiconductor devices are balanced. A narrower linewidth helps increase the trench density per unit area, enhances gate control capability, and reduces on-resistance; while a larger depth effectively extends the depletion region propagation path, improving breakdown voltage, which is particularly suitable for medium- to high-power applications. Meanwhile, this size range is compatible with existing deep trench etching processes (such as high aspect ratio reactive ion etching), and can provide a process window for subsequent formation of a double-corner rounded structure (such as a first fillet) at the top of the trench while ensuring sidewall perpendicularity. Combined with the aforementioned first fillet curvature radius of 5nm to 100nm, this trench geometry design can achieve an optimized balance between suppressing electric field concentration, improving gate oxide reliability, and maintaining device performance, making it suitable for the fabrication of high-performance trench gate IGBTs or similar power semiconductor devices.
[0024] In one possible implementation, the radius of curvature of the second rounded corner structure 210 is 5nm to 100nm. For example, the radius of curvature of the first rounded corner structure 120 can be any typical but non-limiting point value or an interval between any two points, such as 5nm, 10nm, 20nm, 30nm, 50nm, 60nm, 80nm, or 100nm. In this case, the second rounded corner structure 210 is located at the apex corner of the gate structure 200 itself, and its rounding treatment can effectively alleviate the local electric field enhancement effect caused by sharp corners resulting from photolithography and etching processes. When the radius of curvature is too small (<5nm), the rounding effect is limited and it is difficult to significantly improve the electric field distribution; while if it is too large (>100nm), it may cause the gate structure 200 to expand laterally, affecting the device integration density or resulting in insufficient spacing with adjacent structures. By combining the first rounded corner structure 120 with a gate oxide layer 300 of appropriate thickness, this design synergistically reduces the electric field peak of the gate oxide layer on both the inner and outer sides of the top of the trench, significantly improving the reliability of the device under high voltage turn-off conditions, suppressing gate oxide degradation and early breakdown risk, while maintaining good switching performance and process manufacturability.
[0025] In one possible implementation, the radius of curvature of the second rounded corner structure 210 is equal to that of the first rounded corner structure 120. This allows for a smooth overall transition of the geometric profile of the silicon-oxide-gate three-phase interface region at the top of the trench, effectively eliminating multiple electric field abrupt changes at the interfaces, thus distributing the electric field intensity more evenly and significantly reducing local electric field peaks. Secondly, the matched radius of curvature helps to obtain a more uniform gate oxide layer 300 during thermal oxidation or subsequent dielectric deposition, avoiding weak oxide layers caused by geometric abrupt changes and improving dielectric reliability.
[0026] In one possible implementation, the top of the gate structure 200 is 5 nm to 200 nm above the surface of the silicon substrate 100. Exemplarily, the top of the gate structure 200 can be any typical but non-limiting point value or any range between any two points, such as 5 nm, 10 nm, 20 nm, 50 nm, 100 nm, 150 nm, or 200 nm above the surface of the silicon substrate 100. In this case, a moderate bump (e.g., 5 nm to 50 nm) helps improve the contact reliability between the gate and the subsequent metal interconnect layer, reduces contact resistance, and provides a more forgiving process window for contact hole lithography and etching; while a higher bump (e.g., 50 nm to 200 nm) can further enhance the wiring flexibility of the gate, especially suitable for high-density integration or multilayer metal interconnect structures. Simultaneously, this bump height works in conjunction with the aforementioned first rounded corner structure 120 and second rounded corner structure 210 to ensure that even when the top of the gate is above the silicon surface, its apex region can still effectively suppress electric field concentration through rounding, avoiding the risk of gate oxide electric field distortion or dielectric breakdown caused by abrupt step changes.
[0027] Secondly, this application provides a power semiconductor device including a silicon substrate 100, the silicon substrate 100 having a trench structure 110, the trench structure 110 being filled with polysilicon to form a gate structure 200, the inner wall of the trench structure 110 having a gate oxide layer 300 for isolating the silicon substrate 100 from the gate structure 200, and the power semiconductor device also including the above-mentioned double-vertex rounded structure.
[0028] The power semiconductor device provided in the second aspect of this application is based on a trench gate structure design and integrates the aforementioned double-vertical-corner rounded structure. This effectively alleviates the problem of electric field concentration caused by right-angle vertices in traditional trench gate devices. Especially in the high-voltage off state, it can significantly reduce the peak electric field intensity of the gate oxide layer 300 at the inner and outer corners of the top of the trench, thereby suppressing failure mechanisms such as gate oxide breakdown, abnormal leakage current, and threshold voltage drift, and significantly improving the uniformity and reliability of the electric field distribution of the device.
[0029] In one possible implementation, the gate oxide layer 300 has a thickness of 20 nm to 150 nm. For example, the thickness of the gate oxide layer 300 can be any typical but non-limiting value, such as 20 nm, 30 nm, 50 nm, 60 nm, 100 nm, 120 nm, or 150 nm, or a range between any two values. In this case, the requirements for device breakdown voltage, gate control efficiency, and reliability are fully considered. A thicker oxide layer (e.g., close to 150 nm) can significantly improve the insulation strength between the gate and the silicon substrate 100, effectively suppressing tunneling current and time-dependent dielectric breakdown (TDDB) under high electric fields, making it particularly suitable for power devices operating under high voltage conditions; while a relatively thin oxide layer (e.g., 20 nm to 50 nm) helps enhance the gate's ability to control the channel's electric field, reducing the threshold voltage and increasing the switching speed.
[0030] In one possible implementation, the top of the gate oxide layer 300 is located no more than 10 nm below the first rounded corner structure 120. Thus, the first rounded corner structure 120 is located in the transition region between the silicon substrate 100 surface and the trench sidewall, which is one of the most prone "hot spots" for electric field concentration. If the gate oxide layer 300 extends too high, covering the top of the rounded corner or even exceeding it, it will form an oxide layer with uneven thickness or localized thinning in areas with high curvature, leading to an abnormally high electric field strength. Limiting the top of the gate oxide layer 300 to within 10 nm below the first rounded corner structure 120 ensures that the oxide layer mainly covers the relatively gentle trench sidewall region, avoiding the high-curvature rounded corner tip, thereby obtaining a more uniform and reliable dielectric thickness distribution.
[0031] like Figure 3As shown in the simulation test diagram of the power semiconductor device provided in the embodiment of this application, only the top corner of the trench structure is rounded: when the test voltage is -35V, the gate emitter leakage current increases sharply, and the negative switching capability is about -35V; Double-vertices rounded structure: The gate emitter leakage current increases sharply at a test voltage of -45V, and the negative turnaround capability is approximately -45V. Compared to the original structure, the leakage current is smaller at negative voltages between -35V and -45V. The leakage current is even smaller at positive voltages between 60V and 70V.
[0032] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of protection of this application is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this application as described above, which are not provided in detail for the sake of brevity.
[0033] One or more embodiments in this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments in this application should be included within the protection scope of this application.
Claims
1. A double-vertex rounded structure, characterized in that, include: A first rounded corner structure (120) is disposed at the top transition between the surface of the silicon substrate (100) and the top of the trench structure (110), and a second rounded corner structure (210) is disposed at the top corner of the gate structure (200).
2. The double-vertex rounded structure according to claim 1, characterized in that, The radius of curvature of the first rounded corner structure (120) is 5nm~100nm.
3. The double-vertex rounded structure according to claim 1, characterized in that, The groove structure (110) has a line width of 0.2μm to 2μm and a depth of 2μm to 30μm.
4. The double-vertex rounded structure according to any one of claims 1-3, wherein the radius of curvature of the second rounded corner structure (210) is 5nm~100nm.
5. The double-vertex rounded structure according to claim 4, characterized in that, The radius of curvature of the second rounded corner structure (210) is equal to the radius of curvature of the first rounded corner structure (120).
6. The double-vertex rounded structure according to claim 1, characterized in that, The top of the gate structure (200) is 5nm to 200nm above the surface of the silicon substrate (100).
7. A power semiconductor device, characterized in that, The device includes a silicon substrate (100) having a trench structure (110) filled with polysilicon to form a gate structure (200), the inner wall of the trench structure (110) having a gate oxide layer (300) for isolating the silicon substrate (100) from the gate structure (200), and the power semiconductor device further includes a double-vertex rounded structure as described in any one of claims 1-6.
8. The power semiconductor device according to claim 7, characterized in that, The thickness of the gate oxide layer (300) is 20nm~150nm.
9. The power semiconductor device according to claim 7, characterized in that, The top of the gate oxide layer (300) is located no more than 10 nm below the first rounded corner structure (120).