A semiconductor device

Abstract

The embodiment of the present application provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer arranged on one side of the substrate along a first direction, an implanted layer arranged on a side of the epitaxial layer away from the substrate along the first direction, a first source region, a gate region and a drain electrode, the first source region and the gate region are formed in the implanted layer, and the first source region and the gate region are adjacent, the drain electrode is arranged on a side of the substrate away from the epitaxial layer, the first source region, the gate region and the drain electrode all extend along a second direction, a gate electrode is arranged on a side of the implanted layer away from the substrate, the gate electrode extends along the second direction and is electrically connected with the gate region, a first interruption region is formed at the gate region, the first interruption region extends along the first direction and a third direction and disconnects at least part of the gate region. The first interruption region disconnects at least part of the gate region, can reduce the contact area of the gate region and the gate electrode, further reduces the current generated between the first source region and the gate region, can also reduce the gate-drain capacitance, and thus the energy consumption of the semiconductor device can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] Conventional semiconductor devices typically include structures such as a substrate, epitaxial layer, source region, gate region, and drain region. Due to differences in the placement of the substrate, epitaxial layer, source region, gate region, and drain region, as well as the type of doping, diode and / or transistor structures may be formed inside the semiconductor device during the manufacturing process, leading to increased energy consumption when the semiconductor device is electrically conductive. Utility Model Content

[0003] This application provides a semiconductor device in which at least a portion of the gate region is disconnected by a first interrupt region, which can reduce the contact area between the gate region and the gate electrode, thereby reducing the current generated between the first source region and the gate region. At the same time, it can also reduce the gate leakage capacitance, thereby achieving the effect of reducing the power consumption of the semiconductor device.

[0004] This application provides a semiconductor device, including,

[0005] Substrate;

[0006] An epitaxial layer is disposed on one side of the substrate along a first direction; the first direction is the thickness direction of the substrate.

[0007] An implantation layer is disposed along the first direction on the side of the epitaxial layer opposite to the substrate;

[0008] A first source region, a gate region, and a drain electrode; the first source region and the gate region are formed within the implantation layer and are adjacent to each other; the drain electrode is disposed on the side of the substrate opposite to the epitaxial layer; the first source region, the gate region, and the drain electrode all extend along a second direction, which is perpendicular to the first direction;

[0009] A gate electrode is disposed on the side of the implantation layer opposite to the substrate; the gate electrode extends along the second direction and is electrically connected to the gate region;

[0010] A first interruption region is formed at the gate region; the first interruption region extends along the first direction and a third direction, and interrupts at least a portion of the gate region; the third direction is perpendicular to the first direction and the second direction.

[0011] In one possible implementation, the first interruption region extends through the gate region along the first direction and the third direction to completely disconnect the gate region.

[0012] In one possible implementation, along the third direction, the first interruption region is located in the middle of the gate region to disconnect a portion of the gate region.

[0013] In one possible implementation, the maximum dimension of the cross-section of the first interrupted region perpendicular to the first direction is no greater than 1 micrometer.

[0014] In one possible implementation, a conductive element is disposed between the gate electrode and the gate region, the conductive element extending along the second direction; the conductive element electrically conducts to both the gate electrode and the gate region.

[0015] In one possible implementation, a second interruption region is also included, the second interruption region being formed at the conductive element;

[0016] The second interruption region extends along the first direction and the third direction, and disconnects at least a portion of the conductive element.

[0017] In one possible implementation, the second interruption region extends through the conductive element along the first direction and the third direction to completely disconnect the conductive element.

[0018] In one possible implementation, along the third direction, the second interruption region is located in the middle of the conductive element to partially disconnect the gate region.

[0019] In one possible implementation, an insulating element is provided within the second interruption zone.

[0020] In one possible implementation, the gate region includes a first doped region and a second doped region; the first doped region is formed inside the second doped region; the doping concentration of the first doped region is greater than the doping concentration of the second doped region; the gate region electrically connects to the gate electrode through the first doped region.

[0021] In one possible implementation, a second source region is also included, which includes a first sub-region and a well region;

[0022] Along the third direction, the first sub-region is adjacent to the first source region, and the first sub-region is located on the side of the first source region away from the gate region;

[0023] Along the third direction, the first sub-region is adjacent to the well region; along the first direction, the first source region is adjacent to the well region, and the well region is spaced apart from the gate region.

[0024] In one possible implementation, the doping concentration of the first source region and the doping concentration of the first sub-region are greater than the doping concentration of the well region.

[0025] In one possible implementation, the first sub-region has a first side facing the substrate, and the well region has a second side facing the substrate, wherein the first side is closer to the substrate than the second side.

[0026] In one possible implementation, the gate region, the first sub-region, and the well region are P-type doped; the first source region, the epitaxial layer, the implantation layer, and the substrate are N-type doped.

[0027] In one possible implementation, a source electrode is disposed on the side of the injection layer opposite to the substrate; the source electrode extends along the second direction and is electrically connected to the first source region and the first sub-region.

[0028] In one possible implementation, there are two first source regions and two second source regions; along the third direction, the two first source regions and the two second source regions are located on both sides of the gate region, and the well regions of the two second source regions are opposite to each other and spaced apart.

[0029] The semiconductor device provided in this application embodiment has a current I that is related to the current density J and the area A through which the current flows, where I = J·A. Therefore, the smaller the area A through which the current flows, the smaller the current I. In this application embodiment, the first interruption region disconnects at least part of the gate region, which can reduce the contact area between the gate region and the gate electrode, thereby reducing the current generated between the first source region and the gate region. At the same time, it can also correspondingly reduce the gate-drain capacitance, thereby achieving the effect of reducing the power consumption of the semiconductor device. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0031] Figure 1 A top view of a first type of semiconductor device provided in some embodiments of this application;

[0032] Figure 2 for Figure 1 A partial sectional view along the AA direction;

[0033] Figure 3 for Figure 1 A partial sectional view along the BB direction;

[0034] Figure 4 A top view of a second semiconductor device provided in some embodiments of this application;

[0035] Figure 5 for Figure 4 A partial sectional view along the CC direction;

[0036] Figure 6 A top view of a third semiconductor device provided in some embodiments of this application;

[0037] Figure 7 for Figure 6 A partial sectional view along the DD direction.

[0038] Figure label:

[0039] 100. Substrate;

[0040] 200, Epitaxial layer; 210, Buffer layer; 220, Drift region;

[0041] 300, Implantation layer; 310, First source region; 320, Gate region; 321, Sub-gate region; 322, First gate connection region; 323, Second gate connection region; 324, First doped region; 325, Second doped region; 330, First interruption region; 331, First depletion region; 332, Second depletion region; 340, Second source region; 341, First sub-region; 341a, First surface; 342, Well region; 342a, Second surface;

[0042] 400. Gate electrode;

[0043] 500, source electrode;

[0044] 600, Drain electrode;

[0045] 700, Conductive component; 710, Second interruption zone; 711, Insulating component; 720, Sub-conductive component.

[0046] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0047] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0048] Conventional semiconductor devices typically include structures such as a substrate, epitaxial layer, source region, gate region, and drain region. Due to differences in the placement of the substrate, epitaxial layer, source region, gate region, and drain region, as well as the type of doping, diode and / or transistor structures may be formed inside the semiconductor device during the manufacturing process, leading to increased energy consumption when the semiconductor device is electrically conductive.

[0049] This application provides a semiconductor device in which the magnitude of current I is related to the current density J and the area A through which the current flows, where I = J·A. Therefore, the smaller the area A through which the current flows, the smaller the current I. In the embodiments of this application, the first interruption region at least partially disconnects the gate region, which can reduce the contact area between the gate region and the gate electrode, thereby reducing the current generated between the first source region and the gate region. At the same time, it can also correspondingly reduce the gate-drain capacitance, thereby achieving the effect of reducing the power consumption of the semiconductor device.

[0050] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0051] Firstly, see [the following] Figures 1-7 As shown in the embodiment of this application, a semiconductor device is provided, including a substrate 100, an epitaxial layer 200, an implantation layer 300, a first source region 310, a gate region 320, a gate electrode 400, a source electrode 500, and a drain electrode 600. The epitaxial layer 200 is disposed on one side of the substrate 100 along a first direction X, wherein the first direction X is the thickness direction of the substrate 100; the implantation layer 300 is disposed on the side of the epitaxial layer 200 away from the substrate 100. The first source region 310 and the gate region 320 are both formed in the implantation layer 300, and the first source region 310 and the gate region 320 are adjacent to each other in a third direction Z. The first source region 310 and the gate region 320 both extend in the implantation layer 300 along a second direction Y, wherein the second direction Y is perpendicular to the first direction X, and the third direction Z is perpendicular to the first direction X and the second direction Y. The gate electrode 400 is disposed on the side of the implantation layer 300 away from the substrate 100, and the gate electrode 400 is electrically connected to the gate region 320; the source electrode 500 is disposed on the side of the implantation layer 300 away from the substrate 100, and the source electrode 500 is electrically connected to the first source region 310; the drain electrode 600 is disposed on the side of the substrate 100 away from the epitaxial layer 200; the gate electrode 400, the source electrode 500 and the drain electrode 600 all extend along the second direction Y.

[0052] In this embodiment, voltages are applied to the first source region 310 and the gate region 320 by the source electrode 500 and the gate electrode 400, respectively. By adjusting the magnitude of the voltage applied to the gate region 320, the semiconductor device can be turned on and off. When the semiconductor device is in the on state, the current flows from the drain electrode 600 through the substrate 100, the epitaxial layer 200, the injection layer 300, and finally to the source electrode 500.

[0053] It is understandable that, since the first source region 310 and the gate region 320 are adjacent, their doping types must be different in the semiconductor device. That is, when the first source region 310 is P-type doped, the gate region 320 is N-type doped, and vice versa; no particular limitation is made. Because the adjacent first source region 310 and gate region 320 have different doping types, a diode structure is formed between them. For example, this diode structure includes a Zener diode. When the semiconductor device is in the on-state, a current is generated between the first source region 310 and the gate region 320, thereby increasing the power consumption of the semiconductor device.

[0054] Further, see Figures 1-5 As shown in the embodiment of this application, a first interruption region 330 is provided at the gate region 320, and the first interruption region 330 extends along the first direction X and the third direction Z. It can be understood that since the gate region 320 has a certain thickness in the first direction X and the gate region 320 extends along the second direction Y, the first interruption region 330 extending along the first direction X and the second direction Y respectively can interrupt at least a portion of the gate region 320.

[0055] It should be noted that the magnitude of the current I is related to the current density J and the area A through which the current flows, where I = J·A. Therefore, the smaller the area A through which the current flows, the smaller the current I. In this embodiment, the first interruption region 330 disconnects at least a portion of the gate region 320, which can reduce the contact area between the gate region 320 and the gate electrode 400, thereby reducing the current generated between the first source region 310 and the gate region 320. At the same time, it can also correspondingly reduce the gate-drain capacitance, thereby achieving the effect of reducing the power consumption of the semiconductor device.

[0056] In this embodiment of the application, by selectively doping the implantation layer 300, a first interruption region 330 can be formed on the gate region 320 while forming the gate region 320. The first interruption region 330 is the implantation layer 300 without doping.

[0057] In some implementations, see Figures 1-3As shown, the first interruption region 330 extends along the first direction X and the third direction Z, and the first interruption region 330 penetrates the gate region 320 in the first direction X and penetrates the gate region 320 in the third direction Z, thereby causing the first interruption region 330 to break the gate region 320. In other words, the gate region 320 is completely broken in the second direction Y.

[0058] For example, under the interruption effect of the first interruption region 330 on the gate region 320, the gate region 320 is divided into two sub-gate regions 321 along the second direction Y. The gate electrode 400 extending along the second direction Y can electrically conduct the two sub-gate regions 321 respectively, thereby ensuring the normal conduction and disconnection of the semiconductor device. Since the first interruption region 330 interrupts the gate region 320, the overall contact area between the gate region 320 and the gate electrode 400 is reduced, thereby reducing the current generated between the first source region 310 and the gate region 320. At the same time, the gate leakage capacitance can also be reduced accordingly to reduce the power consumption of the semiconductor device.

[0059] Furthermore, multiple first interrupt regions 330 can be provided on the gate region 320, thereby forming more than two sub-gate regions 321. Since the more first interrupt regions 330 there are, the smaller the contact area between the gate region 320 and the gate electrode 400, the smaller the current generated between the first source region 310 and the gate region 320, resulting in a smaller gate-drain capacitance and thus a lower power consumption of the semiconductor device.

[0060] In some implementations, see Figure 2 , Figure 4 and Figure 5 As shown, the first interruption region 330 extends along the first direction X and the third direction Z. The first interruption region 330 penetrates the gate region 320 in the first direction X, does not penetrate the gate region 320 in the third direction Z, and is located in the middle of the gate region 320 in the third direction Z, so as to partially disconnect the gate region 320.

[0061] In this embodiment, the first interrupt region 330 disconnects part of the gate region 320 in the third direction Z. This can reduce the contact area between the gate region 320 and the gate electrode 400 while ensuring the integrity of the gate region 320. It can also reduce the current generated between the first source region 310 and the gate region 320. At the same time, it can also reduce the gate leakage capacitance accordingly, thereby reducing the power consumption of the semiconductor device.

[0062] Furthermore, when multiple first interrupt regions 330 are provided on the gate region 320 along the second direction Y, the contact area between the gate region 320 and the gate electrode 400 can be reduced more effectively while ensuring the integrity of the gate region 320. This can better reduce the current generated between the first source region 310 and the gate region 320 and the gate leakage capacitance, thereby reducing the energy consumption of the semiconductor device.

[0063] In some embodiments, the maximum cross-sectional dimension of the first interruption region 330 in the direction perpendicular to the first direction X is no greater than 1 micrometer. For example, when the first interruption region 330 penetrates the gate region 320 in the first direction X and also penetrates the gate region 320 in the third direction Z, the maximum dimension of the first interruption region 330 in the second direction Y is no greater than 1 micrometer. That is, in the second direction Y, the spacing between two adjacent sub-gate regions 321 is no greater than 1 micrometer. As another example, when the first interruption region 330 penetrates the gate region 320 in the first direction X, does not penetrate the gate region 320 in the third direction Z, and is located in the middle of the gate region 320 in the third direction Z, the maximum dimension of the first interruption region 330 in the second direction Y is no greater than 1 micrometer, and simultaneously, the maximum dimension of the first interruption region 330 in the third direction Z is no greater than 1 micrometer.

[0064] In this embodiment, due to the presence of the first interrupt region 330 on the gate region 320, a depletion region is generated in the first interrupt region 330 when the semiconductor device is in the on state. The presence of the depletion region can prevent current from entering the first interrupt region 330 and affecting the working efficiency and energy consumption of the semiconductor device.

[0065] For example, when the first interrupt region 330 penetrates the gate region 320 in the first direction X and the first interrupt region 330 penetrates the gate region 320 in the third direction Z, when the semiconductor device is in the on state, the two adjacent sub-gate regions 321 will form depletion regions in the first interrupt region 330. Since the distance between the two adjacent sub-gate regions 321 in this embodiment is no more than 1 micrometer, the depletion regions formed by the two adjacent sub-gate regions 321 in the first interrupt region 330 can be connected, thereby better preventing current from entering the first interrupt region 330.

[0066] Another example is when the first interruption region 330 penetrates the gate region 320 in the first direction X, the first interruption region 330 does not penetrate the gate region 320 in the third direction Z, and the first interruption region 330 is located in the middle of the gate region 320 in the third direction Z, see [reference needed]. Figure 5As shown, the first interrupt region 330 has a first gate connection region 322 and a second gate connection region 323 on both sides along the third direction Z. The first gate connection region 322 and the second gate connection region 323 can ensure the integrity of the gate region 320. When the semiconductor device is in the conducting state, the first gate connection region 322 can form a first depletion region 331 in the first interrupt region 330, and the second gate connection region 323 can form a second depletion region 332 in the first interrupt region 330. Since the maximum size of the first interrupt region 330 in the third direction Z in this embodiment is no greater than 1 micrometer, that is, the distance between the first gate connection region 322 and the second gate connection region 323 is no greater than 1 micrometer, so that the first depletion region 331 and the second depletion region 332 can be connected, thereby better preventing current from entering the first interrupt region 330.

[0067] In some implementations, see Figures 1-7 As shown, a conductive element 700 is provided between the gate electrode 400 and the gate region 320. The conductive element 700 extends along the second direction Y and is electrically connected to both the gate electrode 400 and the gate region 320.

[0068] The conductive element 700 in this embodiment is a metal silicide to ensure good electrical conduction between the gate electrode 400 and the gate region 320.

[0069] In some implementations, see Figure 6 and Figure 7 As shown, a second interruption region 710 is provided on the conductive element 700, wherein the second interruption region 710 extends along a first direction X and a second direction Y. It can be understood that, since the conductive element 700 has a certain thickness in the first direction X and extends along the second direction Y, the second interruption region 710 extending along the first direction X and the second direction Y respectively can disconnect at least a portion of the conductive element 700, thereby reducing the contact area between the conductive element 700 and the gate electrode 400 and the gate region 320.

[0070] It should be noted that the magnitude of the current I is related to the current density J and the area A through which the current flows, where I = J·A. Therefore, the smaller the area A through which the current flows, the smaller the current I. In this embodiment, since the gate electrode 400 and the gate region 320 are indirectly connected through the conductive element 700, reducing the contact area between the conductive element 700 and the gate electrode 400 and the gate region 320 can also reduce the current generated between the first source region 310 and the gate region 320. At the same time, it can also correspondingly reduce the gate leakage capacitance, thereby achieving the effect of reducing the power consumption of the semiconductor device.

[0071] In this embodiment, through deposition and etching processes, a conductive element 700 can be selectively formed on the side of the implantation layer 300 away from the substrate 100, and a second interruption region 710 is formed on the conductive element 700 at the same time.

[0072] In some embodiments, the second interruption region 710 extends along the first direction X and the third direction Z, and the second interruption region 710 penetrates the conductive member 700 in the first direction X and the conductive member 700 in the third direction Z, thereby causing the second interruption region 710 to break the conductive member 700, that is, the conductive member 700 is completely disconnected in the second direction Y.

[0073] For example, under the interruption effect of the second interruption region 710 on the conductive element 700, the conductive element 700 is divided into two sub-conductive elements 720 along the second direction Y. The gate electrode 400 and the gate region 320 extending along the second direction Y are electrically connected through the two sub-conductive elements 720, thereby ensuring the normal conduction and disconnection of the semiconductor device. Since the second interruption region 710 interrupts the conductive element 700, the contact area between the conductive element 700 and the gate electrode 400 and the gate region 320 is reduced, thereby reducing the current generated between the first source region 310 and the gate region 320. At the same time, the gate leakage capacitance can also be reduced accordingly to reduce the power consumption of the semiconductor device.

[0074] Furthermore, multiple second interrupt regions 710 can be provided on the conductive element 700, thereby forming more than two sub-conductive elements 720. Since the more second interrupt regions 710 there are, the smaller the contact area between the conductive element 700 and the gate electrode 400 and the gate region 320, the smaller the current generated between the first source region 310 and the gate region 320, and the smaller the corresponding gate-drain capacitance, the lower the power consumption of the semiconductor device.

[0075] In some implementations, see Figure 6 and Figure 7 As shown, the second interruption region 710 extends along the first direction X and the third direction Z. The second interruption region 710 penetrates the conductive member 700 in the first direction X, does not penetrate the conductive member 700 in the third direction Z, and is located in the middle of the conductive member 700 in the third direction Z, so as to partially disconnect the conductive member 700.

[0076] In this embodiment, the second interrupt region 710 disconnects part of the conductive element 700 in the third direction Z. This can ensure the integrity of the conductive element 700 while reducing the contact area between the conductive element 700 and the gate electrode 400 and the gate region 320, respectively. It can also reduce the current generated between the first source region 310 and the gate region 320, and at the same time, it can also reduce the gate leakage capacitance accordingly, thereby reducing the power consumption of the semiconductor device.

[0077] Furthermore, when multiple second interrupt regions 710 are provided on the conductive element 700 along the second direction Y, the contact area between the conductive element 700 and the gate electrode 400 and the gate region 320 can be reduced more effectively while ensuring the integrity of the conductive element 700. This can better reduce the current generated between the first source region 310 and the gate region 320 and the gate leakage capacitance, thereby reducing the energy consumption of the semiconductor device.

[0078] In some implementations, see Figure 6 and Figure 7 As shown, an insulating member 711 is provided within the second interruption region 710. That is, the insulating member 711 is an interlayer dielectric disposed between the gate electrode 400 and the gate region 320. The insulating member 711 can insulate the adjacent sub-conductive members 720 and can also insulate the gate electrode 400 and the gate region 320 corresponding to the position of the second interruption region 710. On the other hand, the insulating member 711 can assist in the formation of the conductive members 700 and the gate electrode 400.

[0079] In some implementations, see Figure 2 , Figure 5 and Figure 7 As shown, the gate region 320 includes a first doped region 324 and a second doped region 325. The first doped region 324 is formed inside the second doped region 325, and the doping concentration of the first doped region 324 is greater than that of the second doped region 325. The gate region 320 is electrically connected to the gate electrode 400 through the first doped region 324, and the gate region 320 is adjacent to the first source region 310 through the second doped region 325. For example, when no conductive element 700 is provided between the gate electrode 400 and the gate region 320, the first doped region 324 directly contacts the gate electrode 400 to achieve electrical conduction between the gate region 320 and the gate electrode 400. When a conductive element 700 is provided between the gate electrode 400 and the gate region 320, the first doped region 324 directly contacts the conductive element 700 to achieve electrical conduction between the gate region 320 and the conductive element 700.

[0080] In this embodiment, by having the first doped region 324 with a higher doping concentration directly contact the conductive element 700, the electrical resistance between the gate region 320 and the conductive element 700 can be reduced, thereby improving the working efficiency of the semiconductor device.

[0081] Furthermore, by forming a second doped region 325 outside the first doped region 324, the breakdown voltage capability of the semiconductor device in this embodiment can be better improved.

[0082] In some implementations, see Figure 2 , Figure 3 , Figure 5 and Figure 7 As shown, the semiconductor device further includes a second source region 340, which includes a first sub-region 341 and a well region 342. The first sub-region 341 is adjacent to the first source region 310 in the third direction Z, and is located on the side of the first source region 310 away from the gate region 320. The first sub-region 341 is electrically connected to the source electrode 500. The well region 342 is adjacent to the first sub-region 341 in the third direction Z, and is spaced apart from the gate region 320. Further, in this embodiment, the first source region 310 and the well region 342 are adjacent in the first direction X.

[0083] When the semiconductor device of this embodiment is in the on state, a channel current is generated in the gap between the gate region 320 and the well region 342. That is, a channel current is generated in the injection layer 300 between the gate region 320 and the well region 342. At this time, the current flows from the drain electrode 600 through the substrate 100, the epitaxial layer 200, the injection layer 300 excluding the first source region 310, the second source region 340 and the gate region 320, and the first source region 310 to the source electrode 500.

[0084] In some embodiments, the doping concentration of the first source region 310 and the doping concentration of the first sub-region 341 are greater than the doping concentration of the well region 342. That is, the doping concentration of the well region 342 is smaller than that of the first source region 310 and the first sub-region 341.

[0085] It is understandable that, since the semiconductor device is in the on state, a channel current is generated in the gap between the well region 342 and the gate region 320. Therefore, a lower doping concentration in the well region 342 can ensure the formation of the channel current in order to enable the semiconductor device to conduct.

[0086] It is worth mentioning that since the doping concentration of the second doped region 325 of the gate region 320 is smaller than that of the first doped region 324, that is, the doping concentration of the periphery of the gate region 320 is smaller, the formation of channel current can still be guaranteed to enable the semiconductor device to conduct.

[0087] In some implementations, see Figure 2 , Figure 3 , Figure 5 and Figure 7 As shown, the first sub-region 341 has a first surface 341a facing the substrate 100, and the well region 342 has a second surface 342a facing the substrate 100, wherein the first surface 341a of the first sub-region 341 is closer to the substrate 100 than the second surface 342a of the well region 342.

[0088] In this embodiment, the first sub-region 341 extends along the first direction X, and the first surface 341a of the first sub-region 341 is located in the epitaxial layer 200, while the well region 342 is located entirely in the implantation layer 300, thereby making the first surface 341a of the first sub-region 341 closer to the substrate 100 than the second surface 342a of the well region 342.

[0089] It is worth mentioning that, since the first sub-region 341 and the well region 342 are adjacent in the third direction Z, and the first surface 341a is closer to the substrate 100 than the second surface 342a in the first direction X, the first sub-region 341 and the well region 342 can form a step shape on the side of the first sub-region 341 and the well region 342 that is closer to the substrate 100. When the semiconductor device of this embodiment is in the conducting state, during the process of current flowing through the epitaxial layer 200, the injection layer 300, the first source region 310 and reaching the source electrode 500, the first surface 341a of the first sub-region 341 and the second surface 342a of the well region 342 can guide the current, thereby improving the working efficiency of the semiconductor device.

[0090] In some embodiments, the gate region 320, the first sub-region 341, and the well region 342 are all P-type doped, while the first source region 310, the epitaxial layer 200, the implantation layer 300, and the substrate 100 are N-type doped.

[0091] More specifically, both the first doped region 324 and the second doped region 325 in the gate region 320 are P-type doped, with the first doped region 324 having a heavier P-type doping and the second doped region 325 having a lighter P-type doping, resulting in different doping concentrations between the first doped region 324 and the second doped region 325. Both the first sub-region 341 and the well region 342 are P-type doped, with the first sub-region 341 having a heavier P-type doping and the well region 342 having a lighter P-type doping, resulting in different doping concentrations between the first sub-region 341 and the well region 342.

[0092] In this embodiment, since the adjacent gate region 320 and the first source region 310 are P-type doped and N-type doped, respectively, a diode structure is formed between the first source region 310 and the gate region 320 when a voltage is applied, resulting in current between the first source region 310 and the gate region 320, thereby increasing the power consumption of the semiconductor device. Since both the gate region 320 and the well region 342 are P-type doped, while the implantation layer 300 between the gate region 320 and the well region 342 is N-type doped, a transistor structure is formed between the gate region 320, the implantation layer 300 between the gate region 320 and the well region 342, and the well region 342. Current also exists between the gate region 320, the implantation layer 300 between the gate region 320 and the well region 342, and the well region 342, further increasing the power consumption of the semiconductor device.

[0093] It is worth mentioning that, in the embodiments of this application, by forming a first interrupt region 330 at the gate region 320 and / or forming a second interrupt region 710 at the conductive element 700, the conduction area between the gate electrode 400 and the gate region 320 can be reduced, thereby reducing the current generated due to the presence of the diode structure and the transistor structure. At the same time, the gate leakage capacitance can also be reduced accordingly, thereby better reducing the power consumption of the semiconductor device.

[0094] When the semiconductor device of this application embodiment is in the on state, the current from the drain electrode 600 sequentially passes through the N-type doped substrate 100, the N-type doped epitaxial layer 200, the N-type doped implantation layer 300, and the N-type doped first source region 310 to reach the source electrode 500.

[0095] In some implementations, see Figure 2 , Figure 3 , Figure 5 and Figure 7 As shown, there are two first source regions 310 and two second source regions 340. Along the third direction Z, the two first source regions 310 are located on opposite sides of the gate region 320, and the two second source regions 340 are located on opposite sides of the gate region 320. The well regions 342 of the two second source regions 340 are positioned opposite each other and spaced apart along the third direction Z. Correspondingly, the number of source electrodes 500 in this embodiment is also two, and the two source electrodes 500 are located on opposite sides of the gate electrode 400 along the third direction Z.

[0096] It is understood that since there are two first source regions 310 and two second source regions 340, and they are located on both sides of the gate region 320 in the third direction Z, a diode structure is formed between each first source region 310 and the gate region 320. Similarly, a transistor structure is formed between each well region 342 and the injection layer 300 located between the corresponding well region 342 and the gate region 320, as well as between the well region 342 and the gate region 320. That is to say, there are two diode structures and two transistor structures in the semiconductor device of this application embodiment, which increases the power consumption of the semiconductor device. However, by forming a first interrupt region 330 at the gate region 320 and / or forming a second interrupt region 710 at the conductive element 700, the conduction area between the gate electrode 400 and the gate region 320 can be reduced, thereby reducing the current generated at the two diode structures and the two transistor structures. At the same time, the gate leakage capacitance can also be reduced accordingly, thus better reducing the power consumption of the semiconductor device.

[0097] When the semiconductor in this embodiment is in the on state, current flows from the drain electrode 600 through the substrate 100 into the epitaxial layer 200, then from the epitaxial layer 200 into the implantation layer 300, and then through the implantation layer 300 into the two first source regions 310 and reaches the two source electrodes 500. During this process, since the first surface 341a of each first sub-region 341 and the second surface 342a of the corresponding well region 342 can both guide the current, and the positions of the two well regions 342 are opposite and spaced apart in the third direction Z. As the current flows from the epitaxial layer 200 into the injection layer 300, the current can flow from the first surface 341a of the first sub-region 341 to the second surface 342a of the corresponding well region 342. Under the combined guiding effect of the second surfaces 342a of the two well regions 342, the current will be converged in the injection layer 300 located between the two well regions 342. The converged current is then guided by the injection layer 300 located between the two well regions 342 and the gate region 320 to the two first source regions 310, thereby allowing the current to reach the two source electrodes 500 respectively.

[0098] In some implementations, see Figure 2 , Figure 3 , Figure 5 and Figure 7 As shown, the epitaxial layer 200 includes a buffer layer 210 and a drift region 220. The buffer layer 210 is formed on one side of the substrate 100 along the first direction X, while the drift region 220 is formed on the side of the buffer layer 210 away from the substrate 100. The implantation layer 300 is formed on the side of the drift region 220 away from the substrate 100. In this embodiment, the first surface 341a of the first sub-region 341 extends into the drift region 220 in the first direction X.

[0099] When the semiconductor device of this embodiment is in the on state, the current flows from the drain electrode 600 through the substrate 100, the buffer layer 210 and the drift region 220 to the injection layer 300.

[0100] For example, the semiconductor device in this application embodiment is a junction field-effect transistor.

[0101] Finally, it should be noted that other embodiments of this utility model will readily occur to those skilled in the art upon consideration of the specification and practice of the utility model disclosed herein. This utility model is intended to cover any variations, uses, or adaptations of this utility model that follow the general principles of this utility model and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this utility model is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that: include, Substrate (100); An epitaxial layer (200) is disposed on one side of the substrate (100) along a first direction; the first direction is the thickness direction of the substrate (100); An implantation layer (300) is disposed along the first direction on the side of the epitaxial layer (200) facing away from the substrate (100); A first source region (310), a gate region (320), and a drain electrode (600); the first source region (310) and the gate region (320) are formed within the implantation layer (300), and the first source region (310) and the gate region (320) are adjacent to each other; the drain electrode (600) is disposed on the side of the substrate (100) away from the epitaxial layer (200); the first source region (310), the gate region (320), and the drain electrode (600) all extend along a second direction, which is perpendicular to the first direction; A gate electrode (400) is disposed on the side of the implantation layer (300) facing away from the substrate (100); the gate electrode (400) extends along the second direction and is electrically connected to the gate region (320); A first interruption region (330) is formed at the gate region (320); the first interruption region (330) extends along the first direction and a third direction and interrupts at least a portion of the gate region (320); the third direction is perpendicular to the first direction and the second direction.

2. The semiconductor device according to claim 1, characterized in that: The first interruption region (330) penetrates the gate region (320) along the first direction and the third direction to completely disconnect the gate region (320).

3. The semiconductor device according to claim 1, characterized in that: Along the third direction, the first interruption region (330) is located in the middle of the gate region (320) to disconnect part of the gate region (320).

4. The semiconductor device according to any one of claims 1-3, characterized in that: Perpendicular to the first direction, the maximum dimension of the cross-section of the first interrupted region (330) is no greater than 1 micrometer.

5. The semiconductor device according to any one of claims 1-3, characterized in that: A conductive element (700) is provided between the gate electrode (400) and the gate region (320), and the conductive element (700) extends along the second direction; the conductive element (700) electrically conducts the gate electrode (400) and the gate region (320) respectively.

6. The semiconductor device according to claim 5, characterized in that: It also includes a second interruption region (710) formed at the conductive element (700); The second interruption region (710) extends along the first direction and the third direction, and disconnects at least a portion of the conductive element (700).

7. The semiconductor device according to claim 6, characterized in that: The second interruption zone (710) penetrates the conductive element (700) along the first direction and the third direction to completely disconnect the conductive element (700).

8. The semiconductor device according to claim 6, characterized in that: Along the third direction, the second interruption region (710) is located in the middle of the conductive element (700) to partially disconnect the gate region (320).

9. The semiconductor device according to any one of claims 6-8, characterized in that: An insulating element (711) is provided in the second interruption zone (710).

10. The semiconductor device according to any one of claims 1-3 and 6-8, characterized in that: The gate region (320) includes a first doped region (324) and a second doped region (325); the first doped region (324) is formed inside the second doped region (325); the doping concentration of the first doped region (324) is greater than the doping concentration of the second doped region (325); the gate region (320) is electrically connected to the gate electrode (400) through the first doped region (324).

11. The semiconductor device according to claim 10, characterized in that: It also includes a second source region (340), which includes a first sub-region (341) and a well region (342). Along the third direction, the first sub-region (341) is adjacent to the first source region (310), and the first sub-region (341) is located on the side of the first source region (310) away from the gate region (320); Along the third direction, the first sub-region (341) is adjacent to the well region (342); along the first direction, the first source region (310) is adjacent to the well region (342), and the well region (342) is spaced apart from the gate region (320).

12. The semiconductor device according to claim 11, characterized in that: The doping concentration of the first source region (310) and the doping concentration of the first sub-region (341) are greater than the doping concentration of the well region (342).

13. The semiconductor device according to claim 11, characterized in that: The first sub-region (341) has a first surface (341a) facing the substrate (100), and the well region (342) has a second surface (342a) facing the substrate (100), wherein the first surface (341a) is closer to the substrate (100) than the second surface (342a).

14. The semiconductor device according to claim 11, characterized in that: The gate region (320), the first sub-region (341) and the well region (342) are P-type doped; the first source region (310), the epitaxial layer (200), the implantation layer (300) and the substrate (100) are N-type doped.

15. The semiconductor device according to claim 11, characterized in that: The injection layer (300) has a source electrode (500) disposed on the side opposite to the substrate (100); the source electrode (500) extends along the second direction and is electrically connected to the first source region (310) and the first sub-region (341).

16. The semiconductor device according to any one of claims 11-15, characterized in that: The number of the first source region (310) and the second source region (340) are both two; along the third direction, the two first source regions (310) and the two second source regions (340) are located on both sides of the gate region (320), and the positions of the trap regions (342) of the two second source regions (340) are opposite and spaced apart.

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