Stacked structure chip, display driving chip and touch and display integrated driving chip

Abstract

The utility model discloses a kind of stacked structure chip, display drive chip and touch and display integrated drive chip.The stacked structure chip, including the first wafer and the second wafer of stacked arrangement, the first wafer and the second wafer are bonded;The first wafer includes first substrate and multiple gate oxide devices on the first substrate, and the multiple gate oxide devices include at least two different gate oxide thickness gate oxide devices;The second wafer includes second substrate and single gate oxide device on the second substrate, and the single gate oxide device includes multiple gate oxide thickness same gate oxide device;The gate oxide thickness of the multiple gate oxide devices is all greater than the gate oxide thickness of the single gate oxide device.The chip can meet the demand of low cost and high performance, and help to save area.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a stacked structure chip, a display driver chip, and a touch and display integrated driver chip. Background Technology

[0002] In semiconductor chip design, multiple functional devices with varying pressure tolerances are often placed on a wafer. The lower the pressure tolerance of these devices, the more refined the wafer fabrication process, resulting in higher costs but better performance. Conversely, the higher the pressure tolerance of these devices, the more flexible the wafer fabrication process, resulting in lower costs but lower performance. In other words, current semiconductor chip design faces the challenge of balancing low cost and high performance. Utility Model Content

[0003] This utility model provides a stacked structure chip, a display driver chip, and a touch and display integrated driver chip to solve the problem of difficulty in balancing low cost and high performance in existing chip design processes.

[0004] A stacked chip includes a first wafer and a second wafer stacked together, wherein the first wafer and the second wafer are bonded together. The first wafer includes a first substrate and a multi-gate oxide device disposed on the first substrate, wherein the multi-gate oxide device includes at least two types of gate oxide devices with different gate oxide thicknesses; The second wafer includes a second substrate and a single-gate oxide device disposed on the second substrate, wherein the single-gate oxide device includes a plurality of gate oxide devices with the same gate oxide thickness; The gate oxide thickness of the multi-gate oxide device is greater than that of the single-gate oxide device.

[0005] Preferably, the multi-gate oxide device includes a first gate oxide thickness device, a second gate oxide thickness device, and a third gate oxide thickness device; The gate oxide thickness of the first gate oxide thickness device is 60nm-90nm; The gate oxide thickness of the second gate oxide thickness device is 12nm-20nm; The gate oxide thickness of the third gate oxide thickness device is 5nm-8nm.

[0006] Preferably, the gate oxide thickness of the single-gate oxide device is 1nm-3nm.

[0007] Preferably, the first wafer further includes a plurality of first dielectric layers, a plurality of first metal layers, a first metal bonding structure, and a first pad; the plurality of first dielectric layers and the plurality of first metal layers are alternately arranged; the bottom first dielectric layer is in contact with the front side of the first substrate; the bottom first metal layer is in contact with the first pad, and the top first metal layer is in contact with the first metal bonding structure; The second wafer includes a plurality of second dielectric layers, a plurality of second metal layers, and a second metal bonding structure; the plurality of second dielectric layers and the plurality of second metal layers are alternately arranged; the bottom second dielectric layer is in contact with the front side of the second substrate, and the top second metal layer is in contact with the second metal bonding structure; The first dielectric layer at the top layer is bonded to the second dielectric layer at the top layer, and the first metal bonding structure is bonded to the second metal bonding structure.

[0008] Preferably, the number of the plurality of first metal layers is three or more; the number of the second metal layers is three or more.

[0009] Preferably, the first dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; the second dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; and both the first metal bonding structure and the second metal bonding structure are copper bonding structures.

[0010] Preferably, all of the first metal layers are copper metal layers; Alternatively, all of the first metal layers may be aluminum metal layers; Alternatively, one portion of the plurality of the first metal layers may be an aluminum metal layer and another portion may be a copper metal layer.

[0011] Preferably, all of the second metal layers are copper metal layers.

[0012] Preferably, among the plurality of first metal layers, the bottom first metal layer has the smallest thickness and the top first metal layer has the largest thickness; Among the multiple second metal layers, the bottom second metal layer has the smallest thickness, and the top second metal layer has the largest thickness.

[0013] A display driver chip with a stacked structure includes the aforementioned stacked structure chip; The first wafer integrates the medium- and high-voltage sections of the data driver, the medium- and high-voltage sections of the timing controller, the medium- and high-voltage sections of the I / O circuit, the medium- and high-voltage sections of the power management circuit, the medium- and high-voltage sections of the digital-to-analog converter circuit, and the ESD protection circuit. The second wafer integrates logic circuits, a low-voltage section of a data driver, a low-voltage section of a timing controller, a low-voltage section of an I / O circuit, a low-voltage section of a power management circuit, a low-voltage section of a digital-to-analog converter circuit, a memory cell, a clock management circuit, and a high-speed interface circuit.

[0014] A touch and display integrated driver chip with a stacked structure, comprising the aforementioned stacked structure chip; The first wafer integrates the medium-high voltage section of the data driver, the medium-high voltage section of the timing controller, the medium-high voltage section of the I / O circuit, the medium-high voltage section of the power management circuit, the medium-high voltage section of the digital-to-analog converter circuit, the ESD protection circuit, and the medium-high voltage section of the touch circuit. The second wafer integrates logic circuits, low-voltage sections of data drivers, low-voltage sections of timing controllers, low-voltage sections of I / O circuits, low-voltage sections of power management circuits, low-voltage sections of digital-to-analog converter circuits, memory cells, clock management circuits, high-speed interface circuits, and low-voltage sections of touch circuits.

[0015] The stacked chip, display driver chip, and touch and display integrated driver chip provided in this embodiment of the invention can be fabricated using a process technology with a high number of nodes to prepare a first wafer with multiple gate oxide devices, and a process technology with a low number of nodes to prepare a second wafer with a single gate oxide device. This process decouples the process technologies of the first and second wafers, achieving the goal of balancing low cost and ensuring the overall performance of the stacked chip. The first and second wafers are stacked and bonded to enable high-density interconnection between the two wafers, which helps save area and improve overall performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a stacked chip structure in one embodiment of the present invention; Figure 2 This is a schematic diagram of a display driver chip with a stacked structure in one embodiment of the present invention; Figure 3 This is a schematic diagram of a touch and display integrated driver chip with a stacked structure in one embodiment of the present invention.

[0018] In the figure: 100, first wafer; 110, first substrate; 120, multi-gate oxide device; 121, first gate oxide thickness device; 122, second gate oxide thickness device; 123, third gate oxide thickness device; 130, first dielectric layer; 140, first metal layer; 150, first metal bonding structure; 160, first pad; 200, Second wafer; 210, Second substrate; 220, Single gate oxide device; 221, Fourth gate oxide thickness device; 230, Second dielectric layer; 240, Second metal layer; 250, Second metal bonding structure.

[0019] 310. Medium and high voltage sections of data drivers; 320. Medium and high voltage sections of timing controllers; 330. Medium and high voltage sections of I / O circuits; 340. Medium and high voltage sections of power management circuits; 350. Medium and high voltage sections of digital-to-analog converter circuits; 360. ESD protection circuits; 370. Medium and high voltage sections of touch circuits; 400. Logic circuit; 410. Low-voltage section of data driver; 420. Low-voltage section of timing controller; 430. Low-voltage section of I / O circuit; 440. Low-voltage section of power management circuit; 450. Low-voltage section of digital-to-analog converter circuit; 460. Memory cell; 470. Clock management circuit; 480. High-speed interface circuit; 490. Low-voltage section of touch circuit. Detailed Implementation

[0020] To make the technical problems solved, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0021] This application provides a stacked structure chip, such as Figure 1 As shown, the stacked structure chip includes a first wafer 100 and a second wafer 200 stacked together, and the first wafer 100 and the second wafer 200 are bonded together; the first wafer 100 includes a first substrate 110 and a multi-gate oxide device 120 disposed on the first substrate 110, the multi-gate oxide device 120 including at least two gate oxide devices with different gate oxide thicknesses; the second wafer 200 includes a second substrate 210 and a single gate oxide device 220 disposed on the second substrate 210, the single gate oxide device 220 including multiple gate oxide devices with the same gate oxide thickness; the gate oxide thickness of the multi-gate oxide device 120 is greater than the gate oxide thickness of the single gate oxide device 220.

[0022] The first wafer 100 and the second wafer 200 are two independently configured wafers. The first wafer 100 and the second wafer 200 integrate different devices and can be manufactured using different process technologies. The first substrate 110 and the second substrate 210 are the substrates of the first wafer 100 and the second wafer 200, respectively, serving as the wafer substrate carrier, typically a Si substrate. The front side of the substrate supports the functional devices, while the back side supports auxiliary fixing or other functions. A multi-gate oxide device 120 is integrated on the first wafer 100, including at least two gate oxide devices with different gate oxide thicknesses. A single-gate oxide device 220 is integrated on the second wafer 200, including multiple gate oxide devices with the same gate oxide thickness. Gate oxide devices consist of gate oxide and polysilicon integrated on the gate oxide. The gate oxide is disposed on one surface of the substrate. The formation and disappearance of communication on the substrate surface are controlled by the electric field of the gate oxide device. In other words, the gate oxide, polysilicon and substrate work together to form a complete switching structure, enabling it to realize the switching function of voltage controlling current.

[0023] As an example, the multi-gate oxide device 120 disposed on the first wafer 100 includes multiple gate oxide devices with different gate oxide thicknesses, for example, integrating three gate oxide devices with different gate oxide thicknesses on the first substrate 110, which may include Figure 1 The first gate oxide thickness device 121, the second gate oxide thickness device 122, and the third gate oxide thickness device 123 are shown. Each gate oxide thickness represents a functional device corresponding to a certain operating voltage, enabling the first gate oxide thickness device 121, the second gate oxide thickness device 122, and the third gate oxide thickness device 123 on the first wafer 100 to control the operation of at least three functional devices corresponding to different operating voltages, for example, controlling the operation of high-voltage devices, medium-voltage devices, and I / O devices. The single gate oxide device 220 disposed on the second wafer 200 includes multiple gate oxide devices with the same gate oxide thickness, for example... Figure 1 The fourth gate oxide thickness device 221 shown has the same gate oxide thickness, which enables the multiple fourth gate oxide thickness devices 221 on the second wafer 200 to control the operation of a functional device corresponding to a certain operating voltage, for example, to control the operation of a low-voltage device.

[0024] The gate oxide thickness of the multi-gate oxide device 120 is greater than that of the single-gate oxide device 220, indicating that the thicker gate oxide of the multi-gate oxide device 120 provides stronger load-bearing capacity. The fabrication process for the multi-gate oxide device 120 involves a larger number of nodes, is more mature, and has lower cost. Conversely, the single-gate oxide device 220 has a thinner gate oxide, resulting in weaker load-bearing capacity. The fabrication process for the single-gate oxide device 220 involves a smaller number of nodes, is more advanced, and has higher cost. However, the single-gate oxide device 220 has a larger on-state current, leading to faster switching speed and lower power consumption, thus ensuring overall performance. In this example, a first wafer 100 with multi-gate oxide devices 120 can be fabricated using a process with a larger number of nodes, while a second wafer 200 with single-gate oxide devices 220 can be fabricated using a process with a smaller number of nodes. This process decouples the fabrication processes of the first wafer 100 and the second wafer 200, achieving a balance between low cost and ensuring the overall performance of the stacked chip structure. The first wafer 100 and the second wafer 200 are stacked and bonded to enable high-density interconnection between the two wafers, which helps to save area and improve overall performance.

[0025] In this example, the manufacturing processes of the first wafer 100 and the second wafer 200 are decoupled. This means that the iteration speed of the stacked chip depends on the manufacturing processes of the two wafers. Since the first wafer 100 is manufactured using a process with a higher node count, the process is more mature, resulting in a slower iteration speed. Conversely, the second wafer 200 is manufactured using a process with a lower node count, the process is more advanced, and the iteration speed is faster. When the manufacturing process of the second wafer 200 is updated, the stacked chip is updated accordingly, thereby improving the iteration speed of the stacked chip and freeing it from the constraints of the manufacturing process update speed of the first wafer 100.

[0026] In one embodiment, the multi-gate oxide device 120 includes a first gate oxide thickness device 121, a second gate oxide thickness device 122, and a third gate oxide thickness device 123; the gate oxide thickness of the first gate oxide thickness device 121 is 60nm-90nm; the gate oxide thickness of the second gate oxide thickness device 122 is 12nm-20nm; and the gate oxide thickness of the third gate oxide thickness device 123 is 5nm-8nm.

[0027] As an example, the gate oxide thickness of the multi-gate oxide device 120 is relatively large, allowing it to be fabricated using a process with a high number of nodes. Specifically, a high-voltage process (i.e., HV process) with a node count of 110nm / 90nm can be used to fabricate at least two gate oxide devices with different gate oxide thicknesses. Each gate oxide thickness corresponds to a functional device with a specific operating voltage. For instance, when the stacked chip structure is used in DDIC or TDDI, the functional devices corresponding to different operating voltages are the devices that drive the display panel, and these can be high-voltage devices (HV devices), medium-voltage devices (MV devices), or I / O devices.

[0028] In this example, a high-voltage process with 110nm / 90nm node counts can be used to fabricate a first gate oxide thickness device 121 with a gate oxide thickness of 60nm-90nm. For example, a first gate oxide thickness device 121 with a gate oxide thickness of 85nm can be fabricated, enabling the first gate oxide thickness device 121 to operate normally under a voltage of 20V-32V, thereby ensuring the voltage withstand performance of the first gate oxide thickness device 121. For example, when the stacked structure chip is used in DDIC or TDDI, the first gate oxide thickness device 121 with a gate oxide thickness of 60nm-90nm is a high-voltage device (HV device) used to process high-voltage signals.

[0029] In this example, a high-voltage process with 110nm / 90nm node counts can be used to fabricate a second gate oxide thickness device 122 with a gate oxide thickness of 12nm-20nm. For example, a second gate oxide thickness device 122 with a gate oxide thickness of 18nm can be fabricated, enabling the second gate oxide thickness device 122 to operate normally under a voltage of 5V-10V, thereby ensuring the voltage withstand performance of the second gate oxide thickness device 122. For example, when the stacked chip structure is used in DDIC or TDDI, the second gate oxide thickness device 122 with a gate oxide thickness of 12nm-20nm is a medium-voltage device (MV device) used to process medium-voltage signals.

[0030] In this example, a high-voltage process with 110nm / 90nm node counts can be used to fabricate a third gate oxide thickness device 123 with a gate oxide thickness of 5nm-8nm. For example, a third gate oxide thickness device 123 with a gate oxide thickness of 6nm can be fabricated, enabling the third gate oxide thickness device 123 to operate normally at 1.8V, 2.5V, or 3.3V to ensure its withstand voltage performance. For example, when the stacked chip structure is used in DDIC or TDDI, the third gate oxide thickness device 123 with a gate oxide thickness of 5nm-8nm serves as an I / O device for input or output signals.

[0031] In one embodiment, the gate oxide thickness of the single gate oxide device 220 is 1 nm to 3 nm.

[0032] As an example, the single-gate oxide device 220 has a relatively small gate oxide thickness, allowing it to be fabricated using a process with a smaller node count. Specifically, it can be fabricated using logic processes with node counts of 55nm / 40nm / 28nm / 22nm / 16nm, resulting in a gate oxide thickness of 1nm-3nm for the single-gate oxide device 220. This allows the single-gate oxide device 220 to be used with functional devices operating at lower voltages, meeting high-performance requirements. For instance, when the stacked chip structure is used in DDIC or TDDI, the functional devices operating at lower voltages are logic devices that control the operation of the display panel.

[0033] In this example, a logic process with a node count of 55nm / 40nm can be used to fabricate a fourth gate oxide thickness device 221 with a gate oxide thickness of 2nm-3nm. For example, a fourth gate oxide thickness device 221 with a gate oxide thickness of 2.5nm can be fabricated, enabling the fourth gate oxide thickness device 221 to operate normally at a voltage of 1.1V-1.2V. This ensures the voltage withstand capability of the fourth gate oxide thickness device 221 while meeting the performance requirements of high-speed operation and low power consumption. For example, when the stacked chip structure is used in DDIC or TDDI, the fourth gate oxide thickness device 221 with a gate oxide thickness of 2nm-3nm serves as a logic device for processing logic signals, capable of high-speed operation at a voltage of 1.1V-1.2V, and exhibiting good overall performance.

[0034] In this example, a logic process with node numbers of 28nm / 22nm / 16nm can be used to fabricate a fourth gate oxide thickness device 221 with a gate oxide thickness of 1nm-2nm. For example, a fourth gate oxide thickness device 221 with a gate oxide thickness of 1.5nm can be fabricated, enabling the fourth gate oxide thickness device 221 to operate normally at a voltage of 0.8V-0.9V. This ensures the voltage withstand capability of the fourth gate oxide thickness device 221 while meeting the performance requirements of high-speed operation and low power consumption. For example, when the stacked chip structure is used in DDIC or TDDI, the fourth gate oxide thickness device 221 with a gate oxide thickness of 1nm-2nm serves as a logic device for processing logic signals, enabling high-speed operation at a voltage of 0.8V-0.9V and resulting in better overall performance.

[0035] In one embodiment, the first wafer 100 further includes a plurality of first dielectric layers 130, a plurality of first metal layers 140, a first metal bonding structure 150, and a first pad 160; the plurality of first dielectric layers 130 and the plurality of first metal layers 140 are alternately disposed; the bottom first dielectric layer 130 is in contact with the front side of the first substrate 110; the bottom first metal layer 140 is in contact with the first pad 160, and the top first metal layer 140 is in contact with the first metal bonding structure 150; the second wafer 200 includes a plurality of second dielectric layers 230, a plurality of second metal layers 240, and a second metal bonding structure 250; the plurality of second dielectric layers 230 and the plurality of second metal layers 240 are alternately disposed; the bottom second dielectric layer 230 is in contact with the front side of the second substrate 210, and the top second metal layer 240 is in contact with the second metal bonding structure 250; the top first dielectric layer 130 is bonded to the top second dielectric layer 230, and the first metal bonding structure 150 is bonded to the second metal bonding structure 250.

[0036] The first dielectric layer 130 and the second dielectric layer 230 are dielectric layers of the first wafer 100 and the second wafer 200, respectively, and are structures in which insulating material is filled between different metal layers. The first metal layer 140 and the second metal layer 240 are metal layers of the first wafer 100 and the second wafer 200, respectively, and are structures used to realize signal interconnection. The first metal bonding structure 150 and the second metal bonding structure 250 are metal bonding structures of the first wafer 100 and the second wafer 200, respectively. The first pad 160 is the connection interface between the first wafer 100 and an external package (such as gold wire or copper wire bonding), and the first pad 160 is an aluminum pad.

[0037] As an example, the process of fabricating the first wafer 100 using a process technology with a large number of nodes is as follows: A multi-gate oxide device 120 can be fabricated on the front side of the first substrate 110, and multiple first dielectric layers 130 and multiple first metal layers 140 are alternately fabricated, such that the bottom first dielectric layer 130 is in contact with the front side of the first substrate 110. Next, a first via is formed in the first substrate 110, and a first pad 160 is provided within the first via, such that the first pad 160 is in contact with the bottom first metal layer 140. Alternatively, a first via is formed in the first substrate 110, and a first pad 160 is provided on the back side of the first substrate 110, such that the first pad 160 is in contact with the bottom first metal layer 140 through the filler metal disposed in the first via. A first metal bonding structure 150 is fabricated on the top first metal layer 140, such that the top first metal layer 140 is in contact with the first metal bonding structure 150.

[0038] As an example, the process of fabricating the second wafer 200 using a process with a smaller node count is as follows: A single-gate oxide device 220 can be fabricated on the front side of the second substrate 210, and multiple second dielectric layers 230 and multiple second metal layers 240 are alternately fabricated, such that the bottom second dielectric layer 230 is in contact with the front side of the second substrate 210. Next, a second metal bonding structure 250 is fabricated on the top second metal layer 240, so that the top second metal layer 240 is in contact with the second metal bonding structure 250.

[0039] As an example, after the first wafer 100 and the second wafer 200 are fabricated using different process technologies, the first dielectric layer 130 and the second dielectric layer 230 on the top layer can be dielectrically bonded, so that the insulating materials in the two dielectric layers are initially fixed through atomic diffusion, ensuring structural stability; and the first metal bonding structure 150 and the second metal bonding structure 250 are controlled to achieve metal bonding, specifically forming ohmic contacts through atomic expansion under specific conditions, thereby enabling the first wafer 100 and the second wafer 200 to achieve high-density interconnection, so as to ensure the structural stability and overall performance of the stacked chip.

[0040] In one embodiment, the plurality of first metal layers 140 have three or more layers; the plurality of second metal layers 240 have three or more layers.

[0041] In traditional processes, multi-layer stacked chips with a smaller number of nodes are directly fabricated using process technology, such as fabricating 7-8 metal layers. This approach has the following problems: First, process technology with a smaller number of nodes is inherently more expensive. The more metal layers there are, the finer the linewidth of the metal layers, and the higher the precision requirements, which also leads to a significant increase in cost. Second, the more metal layers there are, the higher the risk of failure due to interlayer alignment deviations, dielectric layer defects, or metal layer electromigration during the manufacturing process, resulting in lower cost and yield.

[0042] In this example, when the first wafer 100 and the second wafer 200 are fabricated using different process technologies, the corresponding first metal layer 140 and second metal layer 240 must each have three or more layers to meet the requirements of driving display panels or other scenarios. This stacking design has the following advantages: two wafers can be fabricated using process technologies with different node numbers, which effectively reduces costs compared to using a process technology with a smaller node number to process a single wafer; the number of metal layers that need to be processed on each wafer is smaller, resulting in thicker linewidths and lower precision requirements, further reducing costs; and the process technologies of the two wafers are decoupled, and the number of metal layers in each wafer is smaller, reducing the risk of failure caused by interlayer alignment deviations, dielectric layer defects, or metal layer electromigration, thereby improving cost and yield.

[0043] In one embodiment, among the multiple metal layers corresponding to the same wafer, the bottom metal layer has the smallest thickness and the top metal layer has the largest thickness.

[0044] As an example, among the multiple first metal layers 140 on the first wafer 100, during chip operation, the current flowing through the bottom first metal layer 140 is relatively small, so the thickness of the bottom first metal layer 140 is designed to be the smallest to meet performance requirements; while the current flowing through the top first metal layer 140 is relatively large, so the thickness of the top first metal layer 140 is designed to be the largest to reduce the resistance of the top first metal layer 140, enabling it to transmit large currents and meet signal transmission requirements. Similarly, in the design of the second wafer 200, the thickness of the bottom second metal layer 240 is the smallest, and the thickness of the top second metal layer 240 is the largest.

[0045] In one embodiment, the first dielectric layer 130 is a SiN dielectric layer or a SiO2 dielectric layer; the second dielectric layer 230 is a SiN dielectric layer or a SiO2 dielectric layer; and the first metal bonding structure 150 and the second metal bonding structure 250 are both copper bonding structures.

[0046] As an example, both the first dielectric layer 130 and the second dielectric layer 230 are SiN or SiO2 dielectric layers. This allows the top dielectric layer 130 to bond with the transition dielectric layer 270, forming a smooth bonding interface through high-precision grinding and etching, which is less prone to cracking and ensures the structural reliability of the final stacked chip. Furthermore, the bonding process is mature and cost-effective. Both the first metal bonding structure 150 and the second metal bonding structure 250 are copper bonding structures. This ensures tight bonding after bonding, reducing interconnect losses and signal delays, thus guaranteeing the overall performance of the final stacked chip. Moreover, the copper-copper bonding process is mature and cost-effective, balancing performance and cost requirements.

[0047] In one embodiment, all of the plurality of first metal layers 140 are copper metal layers; or, all of the plurality of first metal layers 140 are aluminum metal layers; or, a portion of the plurality of first metal layers 140 are aluminum metal layers and another portion are copper metal layers.

[0048] As an example, a plurality of first metal layers 140 are disposed on the first wafer 100. The plurality of first metal layers 140 are all copper metal layers. Since copper has a low resistivity, it can ensure its transmission efficiency, reduce signal delay and energy loss, and thus ensure its overall performance.

[0049] As an example, a plurality of first metal layers 140 are disposed on the first wafer 100. The plurality of first metal layers 140 are all aluminum metal layers. Since the aluminum metal layers are usually processed on the wafer using mature semiconductor manufacturing processes (such as sputtering deposition and dry etching), they have strong adhesion to the substrate and are not prone to interface peeling. The material cost and processing cost are both low, which can effectively reduce the manufacturing cost.

[0050] As an example, a plurality of first metal layers 140 are disposed on the first wafer 100, a portion of which are aluminum metal layers and another portion are copper metal layers, for example. Figure 1 The four first metal layers 140 closest to the first substrate 110 are aluminum metal layers, and the first metal layer 140 furthest from the first substrate 110 is a copper metal layer. This allows the aluminum metal layer to meet the low-cost requirement, while the copper metal layer can meet the high-voltage and high-current requirement, effectively reducing signal delay and loss, thereby ensuring overall performance and achieving a balance between cost and performance requirements.

[0051] In one embodiment, the plurality of second metal layers 240 are all copper metal layers.

[0052] As an example, the multiple second metal layers 240 on the second wafer 200 are all copper metal layers. Since copper has a low resistivity, it can ensure its transmission efficiency, reduce signal delay and energy loss, and thus ensure its overall performance.

[0053] This application provides a display driver chip with a stacked structure, such as... Figure 2 As shown, the chip includes the stacked structure chip in the above embodiment; the first wafer 100 integrates a medium-high voltage section 310 of a data driver, a medium-high voltage section 320 of a timing controller, a medium-high voltage section 330 of an I / O circuit, a medium-high voltage section 340 of a power management circuit, a medium-high voltage section 350 of a digital-to-analog converter circuit, and an ESD protection circuit 360; the second wafer 200 integrates a logic circuit 400, a low-voltage section 410 of a data driver, a low-voltage section 420 of a timing controller, a low-voltage section 430 of an I / O circuit, a low-voltage section 440 of a power management circuit, a low-voltage section 450 of a digital-to-analog converter circuit, a memory cell 460, a clock management circuit 470, and a high-speed interface circuit 480.

[0054] Among them, the display driver IC (hereinafter referred to as "DDIC") is a chip used to implement display driving.

[0055] The data driver is responsible for converting digital image signals into analog voltage signals that can directly drive the pixels of the display panel. The high-voltage section 310 of the data driver is the circuit unit responsible for processing high-voltage signals. In this embodiment, the high-voltage signal can be either a medium-voltage signal or a high-voltage signal. The low-voltage section 410 of the data driver is the circuit unit responsible for processing low-voltage signals.

[0056] The timing controller (TCON) is responsible for receiving external image data, parsing timing signals, and generating synchronization control signals required by the display panel (such as LCD and OLED) and driver chips. This ensures all modules operate at a unified pace, preventing image misalignment, tearing, or flickering. The high-voltage section 320 of the timing controller is the circuit unit responsible for processing high-voltage signals. The low-voltage section 420 of the timing controller is the circuit unit responsible for processing low-voltage signals.

[0057] An I / O circuit is responsible for data input and output. The high-voltage section 330 of the I / O circuit is the circuit unit responsible for processing medium- and high-voltage signals. The high-voltage section 330 of the I / O circuit is also the circuit unit responsible for processing low-voltage signals.

[0058] The power management circuit is used to convert and manage the power supply to the chip and display panel. The medium-high voltage section 340 of the power management circuit is the circuit unit used to process medium-high voltage signals. The low-voltage section 440 of the power management circuit is the circuit unit used to process low-voltage signals.

[0059] A digital-to-analog converter (DAC) is used to convert digital signals (such as grayscale data output by a TCON) into analog voltage signals. The high-voltage section 350 of the DAC is responsible for processing high-voltage signals. The low-voltage section 450 is responsible for processing low-voltage signals.

[0060] ESD (Electrostatic Discharge) protection circuits are primarily used to safely discharge instantaneous large currents / high voltages generated by static electricity to ground, preventing damage to sensitive components. Generally, the core components of the ESD protection circuit 360 (such as TVS diodes and ESD diode arrays) must be connected to the copper foil traces of the circuit board via pads to achieve effective discharge of electrostatic current. Since the pads of the stacked chip structure (i.e., the first pad 160) are all integrated on the first wafer 100, the ESD protection circuit 360 also needs to be integrated on the first wafer 100 to achieve a better protection effect.

[0061] The logic circuit 400 is a circuit that uses digital signals to perform arithmetic and logical operations on digital quantities, and is also known as a digital logic integrated circuit (IC).

[0062] Storage cell 460 is a cell used to store data. Storage cell 460 can be, but is not limited to, DRAM (Dynamic Random Access Memory), RRAM (Resistive Random Access Memory), MRAM (Magnetoresistive Random Access Memory), or PCRAM (Phase Change Random Access Memory).

[0063] The Clock Management Circuit 470 is the core unit responsible for generating, optimizing, and distributing clock signals. All digital logic relies on the "synchronous triggering" of the clock signals to ensure correct timing. The High-Speed ​​Interface Circuit 480 is an interface for implementing high-speed data transmission, used to receive data transmitted from external devices.

[0064] In this example, the logic circuit 400 interacts with the memory cell 460, the clock management circuit 470, and the high-speed interface circuit 480. The signal interaction process is achieved through low-voltage signals. Therefore, these circuits need to be integrated into the second wafer 200 to ensure its overall performance.

[0065] In this embodiment, the data driver, timing controller, I / O circuit, power management circuit, and digital-to-analog converter circuit all include medium-high voltage and low-voltage sections. The medium-high voltage sections of the above circuits and the ESD protection circuit 360 are integrated on a first wafer 100 capable of handling medium-high voltage signals. The above circuits include gate oxide devices 120 with different gate oxide thicknesses, allowing different gate oxide devices to be turned on or off based on medium-high voltage signals. The low-voltage section of the above circuits, as well as the logic circuit 400, memory cell 460, clock management circuit 470, and high-speed interface circuit 480 that communicate via low-voltage signals, are integrated on a second wafer 200. The above circuits include gate oxide devices 220 with the same gate oxide thickness, allowing them to be turned on or off based on low-voltage signals. In this example, since the pads of the stacked chip are all located on the first wafer 100, TSVs can be set on the first wafer 100 to enable direct interconnection and mutual trust between multiple wafers, so that the pads can communicate with the circuits of other wafers via the TSVs.

[0066] In this embodiment, the relevant circuits involving medium and high voltage signal processing are integrated on the first wafer 100, and the relevant circuits involving low voltage signal processing are integrated on the second wafer 200. The gate oxide thickness of the multi-gate oxide device 120 on the first wafer 100 is greater than the gate oxide thickness of the single-gate oxide device 220 on the second wafer 200. This allows the first wafer 100 to be fabricated using a process with a larger number of nodes, while the second wafer 200 can be fabricated using a process with a smaller number of nodes. This process decouples the process technologies of the first wafer 100 and the second wafer 200 to meet the goal of DDIC in balancing low cost and overall performance.

[0067] This application provides a touch and display integrated driver chip with a stacked structure, such as... Figure 3 As shown, the chip includes the stacked structure chip in the above embodiment; the first wafer 100 integrates the medium-high voltage section 310 of the data driver, the medium-high voltage section 320 of the timing controller, the medium-high voltage section 330 of the IO circuit, the medium-high voltage section 340 of the power management circuit, the medium-high voltage section 350 of the digital-to-analog converter circuit, the ESD protection circuit 360, and the medium-high voltage section 370 of the touch circuit; the second wafer 200 integrates the logic circuit 400, the low voltage section 410 of the data driver, the low voltage section 420 of the timing controller, the low voltage section 430 of the IO circuit, the low voltage section 440 of the power management circuit, the low voltage section 450 of the digital-to-analog converter circuit, the memory cell 460, the clock management circuit 470, the high-speed interface circuit 480, and the low voltage section 490 of the touch circuit.

[0068] The Touch and Display Driver Integration (TDDI) chip integrates display driving and touch control. It retains the display driving capabilities of the DDIC and additionally integrates touch front-end circuitry to achieve unified control of display and touch. The touch circuit is the core circuit for implementing touch functionality. Its core function is to accurately acquire the physical touch signals from the touch panel (such as a capacitive touchscreen) and convert them into recognizable electrical signals. The high-voltage section 370 of the touch circuit processes the high-voltage signals. The low-voltage section 490 of the touch circuit processes the low-voltage signals.

[0069] In this embodiment, the data driver, timing controller, I / O circuit, power management circuit, digital-to-analog converter circuit, and touch circuit all include medium-high voltage and low-voltage sections. The medium-high voltage sections and ESD protection circuit 360 of the above circuits are integrated on a first wafer 100 capable of handling medium-high voltage signals. The above circuits include gate oxide devices 120 with different gate oxide thicknesses, allowing different gate oxide devices to be turned on or off based on medium-high voltage signals. The low-voltage section of the above circuits, as well as the logic circuit 400, memory cell 460, clock management circuit 470, and high-speed interface circuit 480 communicating via low-voltage signals, are integrated on a second wafer 200. The above circuits include gate oxide devices 220 with the same gate oxide thickness, allowing them to be turned on or off based on low-voltage signals.

[0070] In this embodiment, circuits related to medium- and high-voltage signal processing are integrated on the first wafer 100, and circuits related to low-voltage signal processing are integrated on the second wafer 200. The gate oxide thickness of the multi-gate oxide device 120 on the first wafer 100 is greater than the gate oxide thickness of the single-gate oxide device 220 on the second wafer 200. This allows the first wafer 100 to be fabricated using a process technology with a higher node count, while the second wafer 200 can be fabricated using a process technology with a lower node count. This process decouples the process technologies of the first wafer 100 and the second wafer 200, thus satisfying the TDDI's goal of balancing low cost and overall performance. Compared to DDIC, TDDI additionally includes a touch circuit. The medium- and high-voltage portion 370 and the low-voltage portion 490 of the touch circuit are integrated on the first wafer 100 and the second wafer 200, respectively. The decoupling of the process technologies of the two wafers allows the final touch circuit to meet the requirements of both low cost and high performance.

[0071] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.

Claims

1. A stacked chip structure, characterized in that, It includes a first wafer and a second wafer stacked together, wherein the first wafer and the second wafer are bonded together; The first wafer includes a first substrate and a multi-gate oxide device disposed on the first substrate, wherein the multi-gate oxide device includes at least two gate oxide devices with different gate oxide thicknesses; The second wafer includes a second substrate and a single-gate oxide device disposed on the second substrate, wherein the single-gate oxide device includes a plurality of gate oxide devices with the same gate oxide thickness; The gate oxide thickness of the multi-gate oxide device is greater than that of the single-gate oxide device.

2. The stacked structure chip according to claim 1, characterized in that, The multi-gate oxide device includes a first gate oxide thickness device, a second gate oxide thickness device, and a third gate oxide thickness device; The gate oxide thickness of the first gate oxide thickness device is 60nm-90nm; The gate oxide thickness of the second gate oxide thickness device is 12nm-20nm; The gate oxide thickness of the third gate oxide thickness device is 5nm-8nm.

3. The stacked structure chip according to claim 1, characterized in that, The gate oxide thickness of the single-gate oxide device is 1nm-3nm.

4. The stacked structure chip according to claim 1, characterized in that, The first wafer further includes a plurality of first dielectric layers, a plurality of first metal layers, a first metal bonding structure, and a first pad; the plurality of first dielectric layers and the plurality of first metal layers are alternately arranged; the bottom first dielectric layer is in contact with the front side of the first substrate; the bottom first metal layer is in contact with the first pad, and the top first metal layer is in contact with the first metal bonding structure; The second wafer includes multiple second dielectric layers, multiple second metal layers, and a second metal bonding structure; Multiple second dielectric layers and multiple second metal layers are alternately disposed; the bottom second dielectric layer is in contact with the front side of the second substrate, and the top second metal layer is in contact with the second metal bonding structure; The first dielectric layer at the top layer is bonded to the second dielectric layer at the top layer, and the first metal bonding structure is bonded to the second metal bonding structure.

5. The stacked structure chip according to claim 4, characterized in that, The number of the plurality of first metal layers is three or more; the number of the plurality of second metal layers is three or more.

6. The stacked structure chip according to claim 4, characterized in that, The first dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; the second dielectric layer is a SiN dielectric layer or a SiO2 dielectric layer; both the first metal bonding structure and the second metal bonding structure are copper bonding structures.

7. The stacked structure chip according to claim 4, characterized in that, All of the first metal layers are copper metal layers; Alternatively, all of the first metal layers may be aluminum metal layers; Alternatively, one portion of the plurality of the first metal layers may be an aluminum metal layer and another portion may be a copper metal layer.

8. The stacked structure chip according to claim 4, characterized in that, All of the second metal layers are copper metal layers.

9. The stacked structure chip according to claim 4, characterized in that, Among the multiple metal layers corresponding to the same wafer, the bottom metal layer has the smallest thickness, and the top metal layer has the largest thickness.

10. A display driver chip employing a stacked structure, characterized in that, Includes the stacked structure chip as described in any one of claims 1-9; The first wafer integrates the medium- and high-voltage sections of the data driver, the medium- and high-voltage sections of the timing controller, the medium- and high-voltage sections of the I / O circuit, the medium- and high-voltage sections of the power management circuit, the medium- and high-voltage sections of the digital-to-analog converter circuit, and the ESD protection circuit. The second wafer integrates logic circuits, a low-voltage section of a data driver, a low-voltage section of a timing controller, a low-voltage section of an I / O circuit, a low-voltage section of a power management circuit, a low-voltage section of a digital-to-analog converter circuit, a memory cell, a clock management circuit, and a high-speed interface circuit.

11. A touch and display integrated driver chip employing a stacked structure, characterized in that, Includes the stacked structure chip as described in any one of claims 1-9; The first wafer integrates the medium-high voltage section of the data driver, the medium-high voltage section of the timing controller, the medium-high voltage section of the IO circuit, the medium-high voltage section of the power management circuit, the medium-high voltage section of the digital-to-analog converter circuit, the medium-high voltage section of the touch circuit, and the ESD protection circuit. The second wafer integrates logic circuits, low-voltage sections of data drivers, low-voltage sections of timing controllers, low-voltage sections of I / O circuits, low-voltage sections of power management circuits, low-voltage sections of digital-to-analog converter circuits, memory cells, clock management circuits, high-speed interface circuits, and low-voltage sections of touch circuits.

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