Integrated circuit structure

Abstract

Embodiments of the present disclosure provide an integrated circuit structure, relating to the field of semiconductor technology, for improving the accuracy of test results of gate-source capacitance, gate-drain capacitance and source-drain capacitance of a first transistor in the integrated circuit structure. The integrated circuit structure comprises a substrate, a standard cell and a first transistor. The standard cell and the first transistor are located on the same side of the substrate along a first direction, which is the thickness direction of the substrate. The standard cell comprises a first capacitor, a second capacitor and a third capacitor. The first capacitor comprises a first plate and a second plate, and the second plate is located on one side of the first plate along the first direction. The second capacitor comprises a third plate and a fourth plate, and the fourth plate is located on one side of the third plate along the first direction. The third plate is connected to the first plate. The third capacitor comprises a fifth plate and a sixth plate, and the sixth plate is located on one side of the fifth plate along the first direction. The fifth plate is connected to the second plate, and the sixth plate is connected to the fourth plate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to an integrated circuit structure. Background Technology

[0002] In the field of integrated circuit (IC) fabrication and testing, wafer-level electrical parameter testing (WAT) is a crucial step in ensuring IC performance and yield. Among these steps, accurate measurement of the capacitance parameters of the first transistor within the IC structure is paramount, especially the three-terminal capacitors used to characterize the switching characteristics of the first transistor: its input capacitance, output capacitance, and reverse transfer capacitance. These parameters directly determine the dynamic performance, switching speed, and power efficiency of the first transistor in circuit applications.

[0003] The input capacitance, output capacitance, and reverse transfer capacitance of the first transistor can be calculated from the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor. However, the measurement accuracy of the current gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor is poor. Utility Model Content

[0004] The purpose of this disclosure is to provide an integrated circuit structure for improving the accuracy of test results for the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of a first transistor within the integrated circuit structure.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: An integrated circuit structure is provided. The integrated circuit structure includes a substrate, a standard cell, and a first transistor. The standard cell and the first transistor are located on the same side of the substrate along a first direction, which is the thickness direction of the substrate.

[0006] The standard unit includes a first capacitor, a second capacitor, and a third capacitor. The first capacitor includes a first plate and a second plate, with the second plate located on one side of the first plate along a first direction. The second capacitor includes a third plate and a fourth plate, with the fourth plate located on one side of the third plate along the first direction. The third plate is connected to the first plate. The third capacitor includes a fifth plate and a sixth plate, with the sixth plate located on one side of the fifth plate along the first direction. The fifth plate is connected to the second plate, and the sixth plate is connected to the fourth plate.

[0007] In the above integrated circuit structure, the standard cell and the first transistor are located on the same side of the substrate along the first direction, so that the standard cell and the first transistor can be integrated.

[0008] When performing wafer-level electrical parameter testing on an integrated circuit structure, firstly, a capacitance test source meter can be connected sequentially to the second, third, and sixth plates via signal cables and pin clips (or probes) to measure the capacitance values ​​of the first, second, and third capacitors at various test frequencies. Then, the measured capacitance values ​​of the first, second, and third capacitors are compared with their theoretical capacitance values ​​to obtain the error parameters of the test system (i.e., the capacitance test source meter, signal cables, and pin clips, etc.) during the capacitance test. Finally, the capacitance test source meter can be connected sequentially to the gate, source, and drain of the first transistor via signal cables and pin clips (or probes) to measure the capacitance of the first transistor. The measured capacitance values ​​of the gate-source capacitance, the gate-drain capacitance, and the source-drain capacitance of the first transistor are obtained. The obtained error parameters are then used to perform real-time compensation and calculation on these measured capacitance values, yielding the actual capacitance values ​​of the first transistor. This process helps reduce the parasitic effects of the test system (i.e., capacitance test source meter, signal cables, and pin connectors) on the test results of the first transistor's gate-source capacitance, gate-drain capacitance, and source-drain capacitance, thereby improving the accuracy of the test results.

[0009] Furthermore, since the standard cell and the first transistor are integrated, they have the same manufacturing process and test path, which helps to ensure the consistency of the test environment for the standard cell and the first transistor during the capacitance test, and thus helps to further improve the accuracy of the test results of the gate-source capacitance, gate-drain capacitance and source-drain capacitance of the first transistor.

[0010] In some embodiments, in orthographic projection onto the substrate, at least two of the overlapping areas of the first and second electrodes, the third and fourth electrodes, and the fifth and sixth electrodes are the same. Alternatively, in orthographic projection onto the substrate, at least two of the overlapping areas of the first and second electrodes, the third and fourth electrodes, and the fifth and sixth electrodes are different.

[0011] In some embodiments, the first capacitor further includes a first dielectric portion located between a first plate and a second plate. The second capacitor further includes a second dielectric portion located between a third plate and a fourth plate. The third capacitor further includes a third dielectric portion located between a fifth plate and a sixth plate.

[0012] Wherein, at least two of the first dielectric portion, the second dielectric portion, and the third dielectric portion are made of the same material. And / or, at least two of the first dielectric portion, the second dielectric portion, and the third dielectric portion have the same dimension along the first direction.

[0013] In some embodiments, the integrated circuit structure further includes a first insulating layer located on one side of the substrate along a first direction. The first dielectric portion, the second dielectric portion, and the third dielectric portion are all located within the first insulating layer.

[0014] In some embodiments, the first capacitor further includes a first dielectric portion located between a first plate and a second plate. The second capacitor further includes a second dielectric portion located between a third plate and a fourth plate. The third capacitor further includes a third dielectric portion located between a fifth plate and a sixth plate.

[0015] The materials of at least two of the first dielectric portion, the second dielectric portion, and the third dielectric portion are different. And / or, the dimensions of at least two of the first dielectric portion, the second dielectric portion, and the third dielectric portion are different along the first direction.

[0016] In some embodiments, the integrated circuit structure further includes a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer is located on one side of the substrate along a first direction. A first dielectric portion is located within the first insulating layer. The second insulating layer is located on the side of the first insulating layer away from the substrate. The second dielectric portion is located within the second insulating layer. The third insulating layer is located on the side of the second insulating layer away from the first insulating layer. The third dielectric portion is located within the third insulating layer.

[0017] In some embodiments, the integrated circuit structure further includes a first insulating layer and a second insulating layer. The first insulating layer is located on one side of the substrate along a first direction, and the second insulating layer is located on the side of the first insulating layer away from the substrate.

[0018] The second dielectric portion includes a first sub-portion and a second sub-portion stacked along a first direction. The first dielectric portion is located within a first insulating layer, the first sub-portion is located within the first insulating layer, and the second sub-portion is located within a second insulating layer.

[0019] In some embodiments, the integrated circuit structure further includes a third insulating layer located on the side of the second insulating layer away from the first insulating layer. The third dielectric portion includes a third sub-portion, a fourth sub-portion, and a fifth sub-portion stacked along a first direction. The third sub-portion is located within the first insulating layer, the fourth sub-portion is located within the second insulating layer, and the fifth sub-portion is located within the third insulating layer.

[0020] In some embodiments, the standard unit further includes a first connecting portion, through which the third electrode plate is connected to the first electrode plate.

[0021] In some embodiments, the first electrode plate, the third electrode plate, and the first connecting portion are disposed on the same layer and form an integral structure.

[0022] In some embodiments, the standard unit further includes a second connecting portion, through which the sixth electrode plate is connected to the fourth electrode plate.

[0023] In some embodiments, the fourth electrode plate, the sixth electrode plate, and the second connecting portion are disposed on the same layer and form an integral structure.

[0024] In some embodiments, the second connection portion includes a first connection sub-portion, a second connection sub-portion, and a first conductive post, wherein the first connection sub-portion is connected to the second connection sub-portion via the first conductive post. The second connection sub-portion is located on one side of the first connection sub-portion along a first direction, and the first conductive post is located between the first connection sub-portion and the second connection sub-portion. The first connection sub-portion is connected to a fourth electrode plate, and the second connection sub-portion is connected to a sixth electrode plate.

[0025] The integrated circuit structure also includes a third insulating layer, a portion of which is located between the first and second connector portions. A first conductive post penetrates the third insulating layer along a first direction.

[0026] In some embodiments, the standard unit further includes a third connecting portion. The third connecting portion includes a third connecting sub-part, a fourth connecting sub-part, and a second conductive post, with the third connecting sub-part connected to the fourth connecting sub-part via the second conductive post. The fourth connecting sub-part is located on one side of the third connecting sub-part along a first direction, and the second conductive post is located between the third and fourth connecting sub-parts. The third connecting sub-part is connected to a second electrode plate, and the fourth connecting sub-part is connected to a fifth electrode plate.

[0027] In some embodiments, the integrated circuit structure further includes a first insulating layer located between the third and fourth connector portions. A second conductive post penetrates the first insulating layer along a first direction.

[0028] In some embodiments, the integrated circuit structure further includes a first insulating layer, a second insulating layer, and a third insulating layer stacked along a first direction. The first insulating layer, the second insulating layer, and the third insulating layer are all located between the third connector portion and the fourth connector portion. A second conductive post penetrates the first insulating layer, the second insulating layer, and the third insulating layer along the first direction. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0030] Figure 1 A plane of a local region of an integrated circuit structure according to some embodiments Figure 1 ; Figure 2 This is a wafer-level electrical parameter test diagram of a first transistor within an integrated circuit structure according to some embodiments; Figure 3 A plane of a local region of an integrated circuit structure according to some embodiments Figure 2 ; Figure 4 This is an equivalent circuit diagram of a standard cell within an integrated circuit structure according to some embodiments; Figure 5 A plane of a local region of an integrated circuit structure according to some embodiments Figure 3 ; Figure 6 This is a test diagram of wafer-level electrical parameters of an integrated circuit structure according to some embodiments; Figure 7 A plane of a local region of an integrated circuit structure according to some embodiments Figure 4 ; Figure 8 for Figure 5 The integrated circuit structure shown is a cross-sectional view along section line A1-A1; Figure 9 A plane of a local region of an integrated circuit structure according to some embodiments Figure 5 ; Figure 10 for Figure 9 The integrated circuit structure shown is a cross-sectional view along section line A2-A2; Figure 11 A plane of a local region of an integrated circuit structure according to some embodiments Figure 6 ; Figure 12 for Figure 11 The diagram shows a cross-sectional view of the integrated circuit structure along section line A3-A3. Detailed Implementation

[0031] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "some embodiments" or "example" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0034] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0035] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0036] As used herein, “vertical” includes the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “vertical” includes absolute verticality and approximate verticality, where an acceptable range of deviation for approximate verticality could, for example, be within 5°.

[0037] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0038] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0039] like Figure 1 As shown, some embodiments of this disclosure provide an integrated circuit structure 10. The integrated circuit structure 10 may include a substrate 1 and a first transistor T1, the first transistor T1 being located on one side of the substrate 1 along a first direction Z, where the first direction Z is the thickness direction of the substrate 1.

[0040] For example, the material of substrate 1 may include one or more (two or more) of silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), and gallium nitride (GaN).

[0041] For example, the first transistor T1 may include a gate, a source, and a drain.

[0042] like Figure 2 As shown, Figure 2 This diagram shows the wafer-level electrical parameter test results for the first transistor T1 within an integrated circuit structure 10 according to some embodiments. In the field of manufacturing and testing integrated circuit structures 10, wafer-level electrical parameter testing (WAT) is a crucial step in ensuring chip performance and yield. Among these, accurate measurement of the capacitance parameters of the first transistor T1 within the integrated circuit structure 10 is essential, particularly the three-terminal capacitors used to characterize the switching characteristics of the first transistor T1, namely the input capacitance (Ciss), output capacitance (Coss), and reverse transfer capacitance (Crss) of the first transistor T1. The input capacitance, output capacitance, and reverse transfer capacitance of the first transistor T1 directly determine its dynamic performance, switching speed, and power efficiency in circuit applications.

[0043] The input capacitance Ciss of the first transistor T1 is equal to Cgs + Cgd, where Cgs represents the gate-source capacitance of the first transistor T1, and Cgd represents the gate-drain capacitance of the first transistor T1. The output capacitance Coss of the first transistor T1 is equal to Cds + Cgd, where Cds represents the source-drain capacitance of the first transistor T1, and Cgd represents the gate-drain capacitance of the first transistor T1. The reverse propagation capacitance Crss of the first transistor T1 is equal to Cgd, where Cgd represents the gate-drain capacitance of the first transistor T1.

[0044] Therefore, the input capacitance, output capacitance, and reverse transfer capacitance of the first transistor T1 can be obtained by testing the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1.

[0045] When testing the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1, a capacitance test source meter can be connected sequentially to the gate, source, and drain of the first transistor T1 via signal cables and pin clips (or probes) to test these capacitance values.

[0046] For example, please continue reading Figure 1 and Figure 2 The integrated circuit structure 10 may also include a first pad P1, a second pad P2 and a third pad P3. The first pad P1 may be connected to the gate of the pin card and the first transistor T1 respectively. The second pad P2 may be connected to the source of the pin card and the first transistor T1 respectively. The third pad P3 may be connected to the drain of the pin card and the first transistor T1 respectively.

[0047] In some embodiments, such as Figure 3 As shown, Figure 3 This is a plan view of a partial region of an integrated circuit structure 10 according to some embodiments. The integrated circuit structure 10 may also include a standard cell M. The standard cell M and the first transistor T1 are located on the same side of the substrate 1 along the first direction Z.

[0048] like Figure 4 and Figure 5 As shown, Figure 4 This is an equivalent circuit diagram of a standard cell M within an integrated circuit structure 10 according to some embodiments. Figure 5 This is a plan view of a partial region of an integrated circuit structure 10 according to some embodiments. A standard cell M may include a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0049] The first capacitor C1 may include a first plate C11 and a second plate C12, with the second plate C12 located on one side of the first plate C11 along the first direction Z.

[0050] The second capacitor C2 includes a third plate C21 and a fourth plate C22, with the fourth plate C22 located on one side of the third plate C21 along the first direction Z. The third plate C21 can be connected to the first plate C11.

[0051] The third capacitor C3 may include a fifth plate C31 and a sixth plate C32, with the sixth plate C32 located on one side of the fifth plate C31 along the first direction Z. The fifth plate C31 may be connected to the second plate C12, and the sixth plate C32 may be connected to the fourth plate C22.

[0052] In the aforementioned integrated circuit structure 10, the standard cell M and the first transistor T1 are located on the same side of the substrate 1 along the first direction Z, allowing the standard cell M and the first transistor T1 to be integrated. The first capacitor C1 in the standard cell M can simulate the gate-source capacitance Cgs of the first transistor T1, the second capacitor C2 in the standard cell M can simulate the source-drain capacitance Cds of the first transistor T1, and the third capacitor C3 in the standard cell M can simulate the gate-drain capacitance Cgd of the first transistor T1.

[0053] like Figure 6 As shown, and in combination Figure 4 and Figure 5 , Figure 6This diagram illustrates wafer-level electrical parameter testing of an integrated circuit structure 10 according to some embodiments. When performing wafer-level electrical parameter testing on the integrated circuit structure 10, firstly, a capacitance test source meter can be connected sequentially to the second plate C12, the third plate C21, and the sixth plate C32 via signal cables and pin clips (or probes) to measure the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 at various test frequencies. Then, the measured capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are compared with their theoretical capacitance values ​​to obtain the error parameters of the test system (i.e., the capacitance test source meter, signal cables, and pin clips, etc.) during the capacitance test. Finally, the capacitance test source meter can be connected sequentially to the gate, source, and drain of the first transistor T1 via signal cables and pin clips (or probes). Next, the measured capacitance values ​​of the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1 are obtained. Then, the obtained error parameters are used to compensate and calculate the measured capacitance values ​​of the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1 in real time, obtaining the actual capacitance values ​​of these three capacitance values. This helps reduce the parasitic effects of the test system (i.e., capacitance test source meter, signal cables, and pin cards, etc.) on the test results of the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1, thereby improving the accuracy of the test results.

[0054] Furthermore, since the standard cell M and the first transistor T1 are integrated, the standard cell M and the first transistor T1 have completely consistent manufacturing processes and test paths, which helps to ensure the consistency of the test environment of the standard cell M and the first transistor T1 during the capacitance test process. This, in turn, helps to further improve the accuracy of the test results of the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1.

[0055] For example, please continue reading Figure 6 and combined Figure 5In the integrated circuit structure 10, there are also a first pad P1, a second pad P2, and a third pad P3. The first pad P1 is connected to the gate of the pin card and the first transistor T1, the second pad P2 is connected to the source of the pin card and the first transistor T1, and the third pad P3 is connected to the drain of the pin card and the first transistor T1. In this case, the second plate C12 and the gate of the first transistor T1 can be connected to one of the first pads P1, the third plate C21 and the source of the first transistor T1 can be connected to one of the second pads P2, and the sixth plate C32 and the drain of the first transistor T1 can be connected to one of the third pads P3.

[0056] The multiple first pads P1 within the integrated circuit structure 10 are all made of the same material and have the same size, as are the multiple second pads P2 and the multiple third pads P3. When performing wafer-level electrical parameter testing on the integrated circuit structure 10, the pin card is connected to the corresponding first pad P1, second pad P2, and third pad P3 respectively. This allows for obtaining more accurate error parameters of the test system (i.e., capacitance test source meter, signal cable, pin card, first pad P1, second pad P2, and third pad P3, etc.) during capacitance testing. This helps to further reduce or eliminate parasitic effects of the test system on the test results of the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1, thereby further improving the accuracy of the test results of the gate-source capacitance, gate-drain capacitance, and source-drain capacitance of the first transistor T1.

[0057] For example, the first capacitor C1 can be a metal-insulator-metal (MIM) capacitor or a metal-oxide-semiconductor (MOS) capacitor, etc.

[0058] For example, the second capacitor C2 can be a metal-insulator-metal capacitor or a metal-oxide-semiconductor capacitor, etc.

[0059] For example, the third capacitor C3 can be a metal-insulator-metal capacitor or a metal-oxide-semiconductor capacitor, etc.

[0060] For example, the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be the same. Alternatively, the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be different.

[0061] For example, please continue reading Figure 5 In the orthographic projection onto the substrate 1, at least two of the overlapping areas of the first electrode C11 and the second electrode C12, the overlapping areas of the third electrode C21 and the fourth electrode C22, and the overlapping areas of the fifth electrode C31 and the sixth electrode C32 can be the same.

[0062] For example, in the orthographic projection onto the substrate 1, two of the overlapping areas of the first electrode C11 and the second electrode C12, the overlapping areas of the third electrode C21 and the fourth electrode C22, and the overlapping areas of the fifth electrode C31 and the sixth electrode C32 can be the same.

[0063] For example, please continue reading Figure 5 In the orthographic projection onto substrate 1, the overlapping areas of the first electrode C11 and the second electrode C12, the overlapping areas of the third electrode C21 and the fourth electrode C22, and the overlapping areas of the fifth electrode C31 and the sixth electrode C32 can all be the same.

[0064] Or, such as Figure 7 As shown, Figure 7 This is a plan view of a partial region of an integrated circuit structure 10 according to some embodiments. In a normal projection onto the substrate 1, at least two of the overlapping areas of the first electrode C11 and the second electrode C12, the overlapping areas of the third electrode C21 and the fourth electrode C22, and the overlapping areas of the fifth electrode C31 and the sixth electrode C32 may be different.

[0065] For example, in the orthographic projection onto the substrate 1, two of the overlapping areas of the first electrode C11 and the second electrode C12, the overlapping areas of the third electrode C21 and the fourth electrode C22, and the overlapping areas of the fifth electrode C31 and the sixth electrode C32 may be different.

[0066] For example, please continue reading Figure 7 In the orthographic projection onto the substrate 1, the overlapping areas of the first electrode C11 and the second electrode C12, the overlapping areas of the third electrode C21 and the fourth electrode C22, and the overlapping areas of the fifth electrode C31 and the sixth electrode C32 can all be different.

[0067] In some embodiments, such as Figure 8 As shown, Figure 8 for Figure 5The integrated circuit structure 10 shown is a cross-sectional view along section line A1-A1. The first capacitor C1 may further include a first dielectric portion C13, located between the first plate C11 and the second plate C12. The second capacitor C2 may further include a second dielectric portion C23, located between the third plate C21 and the fourth plate C22. The third capacitor C3 may further include a third dielectric portion C33, located between the fifth plate C31 and the sixth plate C32.

[0068] The materials of at least two of the first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 may be the same. And / or, the dimensions of at least two of the first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 along the first direction Z may be the same.

[0069] For example, the materials of the first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 can be the same.

[0070] Alternatively, please continue reading Figure 8 The materials of the first dielectric part C13, the second dielectric part C23, and the third dielectric part C33 can all be the same.

[0071] For example, the dimensions of two of the first medium portion C13, the second medium portion C23, and the third medium portion C33 along the first direction Z can be the same.

[0072] Alternatively, please continue reading Figure 8 The dimensions of the first dielectric part C13, the second dielectric part C23, and the third dielectric part C33 along the first direction Z can all be the same.

[0073] For example, please continue reading Figure 8 The integrated circuit structure may also include a first insulating layer 31, which is located on one side of the substrate 1 along the first direction Z.

[0074] The first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 can all be located within the first insulating layer 31.

[0075] In other embodiments, such as Figure 9 , Figure 10 , Figure 11 and Figure 12 As shown, Figure 9 This is a plan view of a partial region of an integrated circuit structure 10 according to some embodiments. Figure 10 for Figure 9 The integrated circuit structure 10 shown is a cross-sectional view along section line A2-A2. Figure 11 This is a plan view of a partial region of an integrated circuit structure 10 according to some embodiments. Figure 12for Figure 11 The integrated circuit structure 10 shown is a cross-sectional view along section line A3-A3. The first capacitor C1 may further include a first dielectric portion C13, located between the first plate C11 and the second plate C12. The second capacitor C2 may further include a second dielectric portion C23, located between the third plate C21 and the fourth plate C22. The third capacitor C3 may further include a third dielectric portion C33, located between the fifth plate C31 and the sixth plate C32.

[0076] The materials of at least two of the first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 may be different. And / or, the dimensions of at least two of the first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 along the first direction Z may be different.

[0077] For example, the materials of the first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 may be different.

[0078] Alternatively, please continue reading Figure 10 and Figure 12 The materials of the first dielectric part C13, the second dielectric part C23, and the third dielectric part C33 can all be different.

[0079] For example, the dimensions of two of the first dielectric portion C13, the second dielectric portion C23, and the third dielectric portion C33 along the first direction Z may be different.

[0080] Alternatively, please continue reading Figure 10 The dimensions of the first dielectric section C13, the second dielectric section C23, and the third dielectric section C33 along the first direction Z can all be different.

[0081] For example, please continue reading Figure 10 and Figure 12 The integrated circuit structure 10 may further include a first insulating layer 31, a second insulating layer 32, and a third insulating layer 33. The first insulating layer 31 may be located on one side of the substrate 1 along the first direction Z, the second insulating layer 32 may be located on the side of the first insulating layer 31 away from the substrate 1, and the third insulating layer 33 may be located on the side of the second insulating layer 32 away from the first insulating layer 31.

[0082] For example, please continue reading Figure 12 The first dielectric portion C13 may be located within the first insulating layer 31, the second dielectric portion C23 may be located within the second insulating layer 32, and the third dielectric portion C33 may be located within the third insulating layer 33.

[0083] For example, please continue reading Figure 10 The first dielectric portion C13 may be located within the first insulating layer 31.

[0084] The second dielectric portion C23 may include a first sub-portion C231 and a second sub-portion C232 stacked along the first direction Z. The first sub-portion C231 may be located within the first insulating layer 31, and the second sub-portion C232 may be located within the second insulating layer 32.

[0085] The third dielectric portion C33 may include a third sub-portion C331, a fourth sub-portion C332, and a fifth sub-portion C333 stacked along the first direction Z. The third sub-portion C331 may be located within the first insulating layer 31, the fourth sub-portion C332 may be located within the second insulating layer 32, and the fifth sub-portion C333 may be located within the third insulating layer 33.

[0086] The above combination Figure 5 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 The following describes the relationship between the overlapping areas of the first plate C11 and the second plate C12 in the first capacitor C1, the overlapping areas of the third plate C21 and the fourth plate C22 in the second capacitor C2, and the overlapping areas of the fifth plate C31 and the sixth plate C32 in the third capacitor C3, as well as the relationship between the thickness and material of the first dielectric portion C13 in the first capacitor C1, the second dielectric portion C23 in the second capacitor C2, and the third dielectric portion C33 in the third capacitor C3.

[0087] The capacitance value of a capacitor can be calculated using the formula C=ε0εr*S / T. It can be seen that the capacitance value of a capacitor is related to the overlapping area S of the plates, the thickness T of the dielectric portion (i.e., the dimension of the dielectric portion along the first direction Z), and the dielectric constant εr of the dielectric portion. The capacitance value of the capacitor can be adjusted by controlling the overlapping area S of the plates, the thickness T of the dielectric portion (i.e., the dimension of the dielectric portion along the first direction Z), and the dielectric constant εr of the dielectric portion.

[0088] Taking the first capacitor C1 as an example, the capacitance value of the first capacitor C1 can be adjusted by controlling the overlapping area of ​​the first plate C11 and the second plate C12 in the first capacitor C1 in the orthogonal projection onto the substrate 1, as well as the thickness (i.e., the dimension of the first dielectric portion C13 along the first direction Z) and the material of the first dielectric portion C13 in the first capacitor C1.

[0089] By using the above settings, the adjustment range of the capacitance value of the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be increased, making the capacitance values ​​of the first capacitor C1, the second capacitor C2, and the third capacitor C3 closer to the capacitance value of the first transistor T1, which is beneficial to improving the measurement accuracy of the capacitance value of the first transistor T1.

[0090] In some embodiments, please continue reading Figure 5 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The standard unit M may also include a first connecting part 41, through which the third electrode plate C21 is connected to the first electrode plate C11.

[0091] For example, please continue reading Figure 5 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The first electrode plate C11, the third electrode plate C21 and the first connecting part 41 can be arranged in the same layer and form an integral structure.

[0092] In the aforementioned integrated circuit structure 10, the first electrode plate C11, the third electrode plate C21, and the first connecting part 41 are arranged on the same layer and form an integral structure. This can simplify the manufacturing process of the integrated circuit structure 10 and thus help reduce the manufacturing cost of the integrated circuit structure 10.

[0093] On the other hand, it can reduce the contact resistance between the first electrode C11, the third electrode C21 and the first connecting part 41, which is beneficial to improving the electrical performance of the integrated circuit structure 10.

[0094] In some embodiments, please continue reading Figure 5 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The standard unit M may also include a second connecting part 42, through which the sixth electrode plate C32 is connected to the fourth electrode plate C22.

[0095] For example, please continue reading Figure 5 , Figure 7 , Figure 8 and Figure 11 The fourth electrode plate C22, the sixth electrode plate C32, and the second connecting part 42 can be arranged in the same layer and form an integral structure.

[0096] In the aforementioned integrated circuit structure 10, the fourth electrode plate C22, the sixth electrode plate C32, and the second connecting part 42 are arranged on the same layer and form an integral structure. On the one hand, this can simplify the manufacturing process of the integrated circuit structure 10, thereby helping to reduce the manufacturing cost of the integrated circuit structure 10.

[0097] On the other hand, it can reduce the contact resistance between the fourth electrode C22, the sixth electrode C32, and the second connection part 42, which is beneficial to improving the electrical performance of the integrated circuit structure 10.

[0098] Alternatively, please continue reading Figure 9 and Figure 10 The second connecting portion 42 may include a first connecting sub-portion 421, a second connecting sub-portion 422, and a first conductive post 423. The first connecting sub-portion 421 is connected to the second connecting sub-portion 422 via the first conductive post 423. The second connecting sub-portion 422 may be located on one side of the first connecting sub-portion 421 along the first direction Z, and the first conductive post 423 may be located between the first connecting sub-portion 421 and the second connecting sub-portion 422. The first connecting sub-portion 421 may be connected to the fourth electrode plate C22, and the second connecting sub-portion 422 may be connected to the sixth electrode plate C32. For example, please continue reading Figure 9 and Figure 10 The integrated circuit structure 10 may further include a third insulating layer 33, a portion of which is located between the first connecting sub-part 421 and the second connecting sub-part 422. The first conductive post 423 may penetrate the third insulating layer 33 along a first direction Z.

[0099] In some embodiments, please continue reading Figure 5 , Figure 7 and Figure 9 The standard unit M may further include a third connecting portion 43. The third connecting portion 43 may include a third connecting sub-portion 431, a fourth connecting sub-portion 432, and a second conductive post 433. The third connecting sub-portion 431 is connected to the fourth connecting sub-portion 432 via the second conductive post 433. The fourth connecting sub-portion 432 may be located on one side of the third connecting sub-portion 431 along the first direction Z, and the second conductive post 433 may be located between the third connecting sub-portion 431 and the fourth connecting sub-portion 432.

[0100] The third connecting part 431 can be connected to the second electrode plate C12, and the fourth connecting part 432 can be connected to the fifth electrode plate C31.

[0101] For example, please continue reading Figure 5 and Figure 7 and combined Figure 8In the case where the integrated circuit structure 10 also includes a first insulating layer 31, the first insulating layer 31 may be located between the third connecting sub-part 431 and the fourth connecting sub-part 432, and the second conductive post 433 penetrates the first insulating layer 31 along the first direction Z.

[0102] Alternatively, please continue reading Figure 12 and combined Figure 11 The integrated circuit structure 10 may further include a first insulating layer 31, a second insulating layer 32, and a third insulating layer 33 stacked along the first direction Z. The first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 may all be located between the third connecting sub-part 431 and the fourth connecting sub-part 432, and the second conductive post 433 penetrates the first insulating layer 31, the second insulating layer 32, and the third insulating layer 33 along the first direction Z.

[0103] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An integrated circuit structure, characterized in that, It includes a substrate, a standard cell, and a first transistor; the standard cell and the first transistor are located on the same side of the substrate along a first direction, the first direction being the thickness direction of the substrate; The standard unit includes: The first capacitor includes a first plate and a second plate; the second plate is located on one side of the first plate along the first direction. The second capacitor includes a third plate and a fourth plate; the fourth plate is located on one side of the third plate along the first direction; the third plate is connected to the first plate. The third capacitor includes a fifth plate and a sixth plate; the sixth plate is located on one side of the fifth plate along the first direction; the fifth plate is connected to the second plate, and the sixth plate is connected to the fourth plate.

2. The integrated circuit structure according to claim 1, characterized in that, In a projection onto the substrate, at least two of the overlapping areas of the first and second electrodes, the third and fourth electrodes, and the fifth and sixth electrodes are the same; or, In a projection onto the substrate, at least two of the overlapping areas of the first and second electrodes, the third and fourth electrodes, and the fifth and sixth electrodes are different.

3. The integrated circuit structure according to claim 1, characterized in that, The first capacitor further includes a first dielectric portion, which is located between the first electrode plate and the second electrode plate; The second capacitor further includes a second dielectric portion located between the third plate and the fourth plate; The third capacitor further includes a third dielectric portion, which is located between the fifth plate and the sixth plate; Wherein, at least two of the first dielectric portion, the second dielectric portion, and the third dielectric portion are made of the same material; and / or, At least two of the first medium portion, the second medium portion, and the third medium portion have the same dimensions along the first direction.

4. The integrated circuit structure according to claim 3, characterized in that, The integrated circuit structure further includes a first insulating layer, which is located on one side of the substrate along the first direction; The first dielectric portion, the second dielectric portion, and the third dielectric portion are all located within the first insulating layer.

5. The integrated circuit structure according to claim 1, characterized in that, The first capacitor further includes a first dielectric portion, which is located between the first electrode plate and the second electrode plate; The second capacitor further includes a second dielectric portion located between the third plate and the fourth plate; The third capacitor further includes a third dielectric portion, which is located between the fifth plate and the sixth plate; Wherein, at least two of the first dielectric portion, the second dielectric portion, and the third dielectric portion are made of different materials; and / or, At least two of the first medium portion, the second medium portion, and the third medium portion have different dimensions along the first direction.

6. The integrated circuit structure according to claim 5, characterized in that, The integrated circuit structure also includes: A first insulating layer is located on one side of the substrate along the first direction; the first dielectric portion is located within the first insulating layer; The second insulating layer is located on the side of the first insulating layer away from the substrate; the second dielectric portion is located within the second insulating layer; The third insulating layer is located on the side of the second insulating layer away from the first insulating layer; the third dielectric portion is located within the third insulating layer.

7. The integrated circuit structure according to claim 5, characterized in that, The second medium portion includes a first sub-portion and a second sub-portion stacked along the first direction; The integrated circuit structure also includes: A first insulating layer is located on one side of the substrate along the first direction; a first dielectric portion is located within the first insulating layer; a first sub-portion is located within the first insulating layer. The second insulating layer is located on the side of the first insulating layer away from the substrate; the second sub-part is located within the second insulating layer.

8. The integrated circuit structure according to claim 7, characterized in that, The third dielectric portion includes a third sub-portion, a fourth sub-portion, and a fifth sub-portion stacked along the first direction; the third sub-portion is located within the first insulating layer, and the fourth sub-portion is located within the second insulating layer; The integrated circuit structure further includes a third insulating layer, which is located on the side of the second insulating layer away from the first insulating layer; the fifth sub-part is located within the third insulating layer.

9. The integrated circuit structure according to any one of claims 1-8, characterized in that, The standard unit further includes a first connecting part; the third electrode plate is connected to the first electrode plate through the first connecting part.

10. The integrated circuit structure according to claim 9, characterized in that, The first electrode plate, the third electrode plate, and the first connecting portion are disposed in the same layer and form an integral structure.

11. The integrated circuit structure according to any one of claims 1-8, characterized in that, The standard unit further includes a second connecting part; the sixth electrode plate is connected to the fourth electrode plate through the second connecting part.

12. The integrated circuit structure according to claim 11, characterized in that, The fourth electrode plate, the sixth electrode plate, and the second connecting part are disposed on the same layer and form an integral structure.

13. The integrated circuit structure according to claim 11, characterized in that, The second connection portion includes a first connection sub-part, a second connection sub-part, and a first conductive post. The first connection sub-part is connected to the second connection sub-part via the first conductive post. The second connection sub-part is located on one side of the first connection sub-part along the first direction, and the first conductive post is located between the first connection sub-part and the second connection sub-part. The first connection sub-part is connected to the fourth electrode plate, and the second connection sub-part is connected to the sixth electrode plate. The integrated circuit structure further includes a third insulating layer, a portion of which is located between the first connecting sub-part and the second connecting sub-part; the first conductive post penetrates the third insulating layer along the first direction.

14. The integrated circuit structure according to any one of claims 1-8, characterized in that, The standard unit also includes a third connecting part; The third connecting portion includes a third connecting sub-portion, a fourth connecting sub-portion, and a second conductive post. The third connecting sub-portion is connected to the fourth connecting sub-portion via the second conductive post. The fourth connecting sub-portion is located on one side of the third connecting sub-portion along the first direction, and the second conductive post is located between the third connecting sub-portion and the fourth connecting sub-portion. The third connecting part is connected to the second electrode plate, and the fourth connecting part is connected to the fifth electrode plate.

15. The integrated circuit structure according to claim 14, characterized in that, The integrated circuit structure further includes a first insulating layer located between the third connecting sub-part and the fourth connecting sub-part; the second conductive post penetrates the first insulating layer along the first direction.

16. The integrated circuit structure according to claim 14, characterized in that, The integrated circuit structure further includes a first insulating layer, a second insulating layer, and a third insulating layer stacked along the first direction; The first insulating layer, the second insulating layer, and the third insulating layer are all located between the third connecting part and the fourth connecting part; the second conductive post penetrates the first insulating layer, the second insulating layer, and the third insulating layer along the first direction.

Images