Silicon-on-insulator substrate

Abstract

A silicon-on-insulator (SOI) substrate is disclosed. The silicon-on-insulator (SOI) substrate includes a substrate, a buried dielectric layer, a first dielectric sidewall, and a second dielectric sidewall. The substrate includes a first substrate layer and a second substrate layer positioned above the first substrate layer. The buried dielectric layer is positioned below the first substrate layer and in contact with a bottom of the first substrate layer. The first dielectric sidewall surrounds a sidewall of the first substrate layer. The second dielectric sidewall surrounds a sidewall of the second substrate layer.

Description

Technical Field

[0001] This disclosure relates to a silicon-on-insulator substrate. Background Technology

[0002] Integrated circuits are formed on semiconductor wafers. The lithography patterning process uses ultraviolet light to transfer the desired mask pattern onto a photoresist layer on the semiconductor wafer. An etching process can then be used to transfer the pattern to layers beneath the photoresist. This process is repeated multiple times using different patterns to create various conductive, resistive, and / or insulating layers on the wafer substrate, thus fabricating useful semiconductor devices. Utility Model Content

[0003] Some embodiments disclosed herein provide a silicon-on-insulator (SiI) substrate. The SiI substrate includes a substrate, a buried dielectric layer, a first dielectric sidewall, and a second dielectric sidewall. The substrate includes a first substrate layer and a second substrate layer located above the first substrate layer. The buried dielectric layer is located below the first substrate layer and contacts the bottom of the first substrate layer. The first dielectric sidewall surrounds the sidewall of the first substrate layer. The second dielectric sidewall surrounds the sidewall of the second substrate layer.

[0004] Other embodiments disclosed herein provide a silicon-on-insulator (SiI) substrate. The SiI substrate includes a buried dielectric layer and dielectric sidewalls. The buried dielectric layer is located within the substrate. The dielectric sidewalls extend from the buried dielectric layer to the upper surface of the substrate. The dielectric sidewalls surround a first substrate region and a second substrate region located above the first substrate region. The area of ​​the second substrate region differs from the area of ​​the first substrate region.

[0005] Further embodiments disclosed herein provide a silicon-on-insulator (SiI) substrate. The SiI substrate includes a substrate, a plurality of source / drain electrodes, a gate dielectric layer, and a gate electrode. The substrate includes a buried dielectric layer and vertical dielectric sidewalls. The buried dielectric layer is located within the substrate. The vertical dielectric sidewalls extend from the buried dielectric layer to the upper surface of the substrate. The vertical dielectric sidewalls surround a first substrate region and a second substrate region located above the first substrate region. The surface area of ​​the second substrate region is different from that of the first substrate region. The source / drain electrodes are located in the second substrate region. The gate dielectric layer is located on the second substrate region. The gate electrode is located on the gate dielectric layer. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1A This is a perspective view of a silicon-on-insulator (SOI) substrate according to some embodiments of the present disclosure; Figure 1B yes Figure 1A Top view; Figure 1C It is along Figure 1B Y-axis cross-sectional view of line CC; Figure 1D It is along Figure 1B Y-axis cross-sectional view of line DD; Figure 1E It is along Figure 1B X-axis cross-sectional view of line EE; Figure 1F It is along Figure 1B X-axis cross-sectional view of line FF;

[0008] Figure 2 A flowchart illustrating a method of manufacturing an SOI substrate according to some embodiments is shown;

[0009] Figure 3A This is a perspective view of a substrate in which a sacrificial layer is formed. Figure 3B It is along Figure 3A Y-axis cross-sectional view of line BB;

[0010] Figure 4A This is a perspective view of a substrate after a substrate layer has been deposited to embed a sacrificial layer, or in an alternative embodiment after ion implantation in the substrate to form a sacrificial layer. Figure 4B It is along Figure 4A Y-axis cross-sectional view of line BB;

[0011] Figure 5A This is a perspective view of the substrate after etching through-holes down through the silicon layer to the sacrificial layer and then laterally etching to remove the sacrificial layer; Figure 5B It is along Figure 5A Y-axis cross-sectional view of line BB; Figure 5C It is along Figure 5A Y-axis cross-sectional view of line CC;

[0012] Figure 6A This is a perspective view of the substrate after the substrate support has been oxidized; Figure 6B It is along Figure 6A Y-axis cross-sectional view of line BB; Figure 6C It is along Figure 6A Y-axis cross-sectional view of line CC;

[0013] Figure 7A This is a perspective view of the substrate after the embedded dielectric layer has been formed in the etched area; a first dielectric sidewall is formed around the first substrate area. Figure 7B It is along Figure 7A Y-axis cross-sectional view of line BB; Figure 7C It is along Figure 7A Y-axis cross-sectional view of line CC;

[0014] Figure 8AThis is a perspective view of the substrate after another substrate layer has been deposited on top of the first substrate layer; Figure 8B It is along Figure 8A Y-axis cross-sectional view of line BB; Figure 8C It is along Figure 8A Y-axis cross-sectional view of line CC;

[0015] Figure 9A This is a perspective view of the substrate after etching to form trenches that expose the first dielectric sidewalls; Figure 9B It is along Figure 9A Y-axis cross-sectional view of line BB; Figure 9C It is along Figure 9A Y-axis cross-sectional view of line CC;

[0016] Figure 10A This is a perspective view of the substrate after dielectric material has been deposited into the trenches to form the second dielectric sidewalls and to obtain the SOI substrate. Figure 10B yes Figure 1A Top view; Figure 10C It is along Figure 10A Y-axis cross-sectional view of line CC; Figure 10D It is along Figure 10A Y-axis cross-sectional view of line DD;

[0017] Figures 11A to 11C These are Y-axis cross-sectional views of different embodiments of the SOI substrate, in which the thickness of the first substrate region can be varied;

[0018] Figures 12A to 12C These are Y-axis cross-sectional views of different embodiments of the SOI substrate, in which the thickness of the second substrate region can be varied;

[0019] Figures 13A to 13C These are Y-axis cross-sectional views of different embodiments of the SOI substrate, in which the ratio of the thickness of the second substrate region to the thickness of the first substrate region can be changed;

[0020] Figures 14A to 14C These are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these views, the horizontal dimensions of the trenches (i.e., length and width, or Y-axis and X-axis) can vary. In addition, different layers in the vertical direction can exist within the trenches.

[0021] Figures 15A to 15D These are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these views, the position of the trenches can be moved along the Y-axis and / or X-axis. Similarly, different layers in the vertical direction can exist within the trenches.

[0022] Figures 16A to 16DThese are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these views, the depth of the trench can be varied, which will change the shape of the first substrate region and / or the second substrate region.

[0023] Figure 17 A Y-axis cross-sectional view illustrating examples of different semiconductor devices that can be formed on an SOI substrate is shown; and

[0024] Figure 18 A flowchart illustrating a method for manufacturing a semiconductor device, particularly a semiconductor device on an SOI substrate, according to some embodiments is shown.

[0025] 100:Substrate

[0026] 102,122: Upper surface

[0027] 104, 124: Lower surface

[0028] 105: Thickness / Height

[0029] 107: Altitude

[0030] 110,184: Body area

[0031] 112: Active Zone

[0032] 114,140: Dielectric sidewalls / dielectric structure

[0033] 119,171,191: Length

[0034] 120: Embedded dielectric layer

[0035] 121,143,153,157,159,217: Thickness

[0036] 125,127,145,201,203: Depth

[0037] 126: Side surface

[0038] 130, 150: Dielectric sidewalls

[0039] 133: Overlap

[0040] 160: First substrate layer

[0041] 123, 128, 129, 155, 165, 175, 185, 195: Height / Depth

[0042] 170: First substrate region

[0043] 173,193: Width

[0044] 180: Second substrate layer

[0045] 182: Sidewall area

[0046] 190: Second substrate region

[0047] 200: Sacrifice Layer

[0048] 210,428: Through hole

[0049] 212: Embedded volume

[0050] 214: Substrate support

[0051] 216: Trench

[0052] 300, 500: Method

[0053] 305, 310, 315, 320, 325, 330, 335, 340, 345, 350, 355, 360, 505, 510, 515, 520, 525, 530, 535, 540, 545: Steps 400, 401, 402: Transistors

[0054] 403: Semiconductor Devices

[0055] 410: Gate dielectric layer

[0056] 412: Gate electrode

[0057] 414: Spacer

[0058] 416: S / D electrode

[0059] 418: Fins

[0060] 420: STI Zone / Isolation Zone

[0061] 422: Semiconductor Channel

[0062] 424: STI area

[0063] 426: Interlayer dielectric layer

[0064] BB, CC, DD, EE, FF: lines

[0065] X, Y, Z: Axes Detailed Implementation

[0066] The following disclosure provides numerous different embodiments or examples for implementing the various features of this disclosure. Specific examples of components and configurations described below are for the purpose of simplifying this disclosure; of course, these are exemplary and not limiting. The drawings are not drawn to scale. Unless otherwise expressly stated, elements with the same reference numerals refer to the same elements and are considered to have the same material composition and the same thickness range. Unless otherwise expressly stated, embodiments in which multiple instances of any described element are repeated are explicitly considered. While some embodiments are not explicitly disclosed but are known in the art, embodiments of non-essential elements are explicitly considered to be omitted.

[0067] Additionally, for ease of description, spatial relative terms (e.g., "below," "below," "lower than," "above," "above," and the like) may be used herein to describe the relationship between one component or feature and another, as illustrated in the accompanying drawings. Besides the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and thus the spatial relative descriptive terms used herein may be interpreted accordingly.

[0068] The accompanying figures provide views of the substrate across three different axes. The “Y-axis cross-sectional view” is arbitrarily designated to correspond to length, such that the length and depth / height of the substrate shown extend into the page. The “X-axis cross-sectional view” is arbitrarily designated to correspond to width, such that the width and depth / height of the substrate shown extend into the page. These terms should not be construed as implying that the length must have a greater value than the width.

[0069] The numerical values ​​in this disclosure and its claims should be understood to include the same values ​​when reduced to the same number of significant figures, and values ​​that differ from the stated values ​​by less than the usual experimental error. Measurement techniques are used to determine these values. All ranges disclosed in this disclosure include the listed endpoints.

[0070] The term "approximately" can be configured to include any numerical value that is variable without altering the underlying function. When used with a range, "approximately" also reveals a range defined by the absolute values ​​of its two endpoints; for example, "approximately 2 to approximately 4" also reveals a range of "2 to 4". The term "approximately" can refer to plus or minus 10% of a specified number.

[0071] This disclosure relates to structures composed of different layers. When the terms “on” or “above” are used to refer to two different layers (including a substrate), they simply indicate that one layer is on or above the other. These terms do not require that the two layers be in direct contact with each other and allow other layers to be located between the two layers. For example, all layers of a structure can be considered to be “on” or “above” the substrate, even if these layers are not all in direct contact with the substrate. The term “direct” can be used to indicate that two layers are in direct contact with each other without any layer between them. Additionally, when referring to performing processing steps on or above the substrate, this should be understood to mean that, depending on the context, these steps are also performed on any layers that may be present on the substrate.

[0072] This disclosure relates to silicon-on-insulator (SOI) substrates and methods for manufacturing and using such SOI substrates. The substrate is a layered semiconductor-insulator-semiconductor substrate, such as a silicon-silicon dioxide substrate, rather than a bulk semiconductor substrate. Semiconductor devices constructed on the upper silicon layer are electrically isolated from the bulk silicon, thus reducing parasitic capacitance and improving power consumption. Additionally, crosstalk caused by capacitive, inductive, and / or conductive coupling between individual devices on the same substrate can be reduced. This disclosure discloses an SOI substrate comprising an insulating structure located beneath and surrounding all sides of the upper silicon layer. This can be advantageous in high-voltage equipment (operating voltages of 5 volts or higher), allowing for high voltage withstand and omnidirectional isolation. Such substrates can also be manufactured in-plant and adapted to the specific needs of equipment.

[0073] Figures 1A to 1F These are various views of the silicon-on-insulator (SOI) substrate 100 disclosed herein. Figure 1A It is a perspective view. Figure 1B It is a top view. Figure 1C It is along Figure 1B Y-axis cross-section of line CC. Figure 1D It is along Figure 1B Y-axis cross-section of line DD. Figure 1E It is along Figure 1B X-axis cross-sectional view of line EE. Figure 1F It is along Figure 1B X-axis cross-sectional view of line FF.

[0074] Please refer to the following first. Figure 1A and Figure 1CThe substrate 100 includes a body region 110 separated from the active region 112 by a dielectric structure 114. The active region 112 is located within the dielectric structure 114. As shown here, the dielectric structure 114 is analogous to the five sides of a cube. The dielectric structure 114 includes a buried dielectric layer 120 in the XY plane and vertical dielectric sidewalls 130 forming four sides extending upward along the Z-axis from the buried dielectric layer 120 to the upper surface 102 of the substrate. As shown, the vertical dielectric sidewalls 130 can be considered to include a first dielectric sidewall 140 and a second dielectric sidewall 150. The first dielectric sidewall 140 contacts the buried dielectric layer 120 and is located below the second dielectric sidewall 150. The second dielectric sidewall 150 extends from the first dielectric sidewall 140 to the upper surface 102 of the substrate. Figure 1C As shown, the thickness 143 of the first dielectric sidewall 140 is different from the thickness 153 of the second dielectric sidewall 150. Figure 1B In the top view, the position of the first dielectric sidewall 140 is indicated by a dashed line.

[0075] Next, in Figure 1C In this context, the active region 112 can be divided into a first substrate region 170 located in the second substrate region 190. A first dielectric sidewall 140 surrounds the first substrate region 170, and a second dielectric sidewall 150 surrounds the second substrate region 190. As in... Figure 1D and Figure 1F Clearly visible, the vertical dielectric sidewall 130 completely isolates the active region 112 from the body region 110 of the substrate.

[0076] Figure 2 A flowchart illustrating a method 300 configured for manufacturing an SOI substrate according to some embodiments is shown. Some steps of this method are also... Figures 3A to 10C The figures are illustrated below. These features provide different views for better understanding. It is worth noting that only Y-axis cross-sectional views are shown in these figures, and for these exemplary figures, it can be assumed that the X-axis cross-sectional views are similar to the Y-axis cross-sectional views. Although the method steps are discussed below in terms of forming a single active region, these discussions should also be broadly interpreted as applicable to forming multiple active regions simultaneously on a substrate. Other structures can also be formed simultaneously. It is worth noting that not all steps described in the flowcharts are necessary.

[0077] Please refer to the following first. Figure 3A and Figure 3BThe method begins with a substrate 100. The substrate can be, for example, a wafer made of a semiconductor material. This semiconductor material can include silicon, such as silicon in crystalline form (Si). In alternative embodiments, the substrate can be made of other elemental semiconductors, such as germanium, silicon carbide (SiC), silicon germanium, or silicon germanium carbide. Alternatively, the substrate can include compound semiconductors such as gallium arsenide (GaAs), gallium phosphide, gallium carbide, indium arsenide (InAs), indium phosphide (InP), gallium arsenide phosphide, indium gallium phosphide, cadmium telluride, or cadmium sulfide. In a particular embodiment, the substrate is silicon. The substrate 100 has an upper surface 102 and a lower surface 104, and a thickness 105 between the two surfaces.

[0078] Next, as Figure 2 In step 320, a sacrificial layer 200 is formed in the substrate 100, and a first substrate layer 160 exists above the sacrificial layer 200. This structure is expected to be obtained through at least two different methods.

[0079] In one of the methods, such as Figure 2 Step 305 and as follows Figure 3A and Figure 3B As shown, a sacrificial layer 200 is formed on the upper surface 102 of the substrate. This step is typically performed by doping the substrate with a dopant of opposite charge. For example, if the substrate is a p-type substrate, the sacrificial layer will be formed by doping with an n-type dopant, and vice versa.

[0080] Doping can be performed via ion implantation or other suitable methods. In short, in ion implantation, an ion implanter is configured to implant atoms into a silicon lattice, thereby altering the lattice's conductivity at the implantation site. An ion implanter typically includes an ion source, an electron beamline, and a processing chamber. The ion source generates the desired ions. The electron beamline organizes the ions into a beam with high purity in terms of ion mass, energy, and species. A mask (e.g., a patterned photoresist layer or a hard mask layer) is used to expose the desired area of ​​the substrate. The semiconductor wafer substrate is then irradiated in the processing chamber using the ion beam. The ion beam strikes the exposed area on the wafer substrate, and the ions can be implanted into the substrate to the desired depth as dopants. Alternatively, the substrate can be partially etched, followed by overlay deposition of dopants, and then annealing, where the dopants react with the exposed silicon underneath.

[0081] Common n-type dopants used for silicon substrates may include nitrogen (N), phosphorus (P), arsenic (As), bismuth (Bi), or tantalum (Ta). Common p-type dopants used for silicon substrates may include boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0082] In some embodiments, the dopant is at approximately 1 × 10 19 cm -2 Or inject at a higher concentration, such as approximately 1 × 10⁻⁶.19 cm -2 To approximately 1×10 21 cm -2 In certain embodiments, dopant can be injected with energy from about 5 keV to about 20 keV to form a sacrificial layer on the surface. Other ranges specified above fall within the scope of this disclosure. Any suitable injection angle can be used.

[0083] Then, as Figure 2 Step 310 and as follows Figure 4A and Figure 4B As shown, a first substrate layer 160 is deposited above the upper surface of the substrate. This step can be performed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods. Notably, the first substrate layer 160 will have the same lattice quality as the substrate. The first substrate layer has a height or depth 165, and the first substrate layer 160 can now also be considered as part of the substrate 100. This two-step process is the first way to obtain the structure of step 320. If desired, the upper surface 102 of the substrate / first substrate layer can be planarized to obtain a horizontal surface. This step can be performed by, for example, chemical mechanical polishing (CMP), where the surface of the wafer is planarized using the relative motion between the wafer and a rotating polishing pad on which slurry is applied. Downward pressure is applied to push the wafer against the polishing pad and abrades the raised components to obtain a surface with low surface roughness.

[0084] The second method for obtaining the structure is shown in step 320. (See also...) Figure 4A and Figure 4B It begins at a substrate 100 having a height of 107, where the height 107 is equal to the sum of heights 105 and 165. Figure 2 In step 315, ion implantation is performed to form a sacrificial layer 200 in the substrate 100. Figure 4B In this process, a sacrificial layer is formed between depths 201 and 203. Then, the first substrate layer 160 is defined as the substrate portion located above the sacrificial layer 200.

[0085] In a particular embodiment, the dopant can be transmitted through approximately 1 × 10⁻⁶ 19 cm -2 Or inject at a higher concentration, such as approximately 1 × 10⁻⁶. 19 cm -2 To approximately 1×10 21 cm -2In certain embodiments, dopant can be implanted with energy ranging from about 20 keV to about 2500 keV, depending on the substrate thickness and the desired depth of the sacrificial layer. Other ranges specified above are also within the scope of this disclosure. Any suitable implantation angle can be used.

[0086] Then, after forming a sacrificial layer below the first substrate layer, the process continues as follows: Figure 2 As shown in step 325, and as Figure 5A As shown, a plurality of through-holes 210 are formed around the first substrate region 170 of the first substrate layer 160. Figure 5B and Figure 5C As shown, via 210 extends downwards to sacrificial layer 200. This step can be performed by appropriately patterning, etching, and removing the mask. Then, in Figure 2 In step 330, the sacrificial layer is etched away to form the buried volume 212. The sacrificial layer may have high etch selectivity. This step can be performed using a dry etching process. Specifically, a selective gas etchant can be used to perform lateral etching.

[0087] The first substrate region 170 is supported above the embedded volume 212 by a plurality of substrate supports 214, which bond the first substrate region 170 to the first substrate layer 160. It is worth noting that although the via 210 and the substrate supports 214 are shown herein as having a rectangular shape, they can also have any shape; for example, the via can be circular.

[0088] Next, as Figure 2 Step 335 and such Figures 6A to 6C As shown, multiple substrate supports 214 are converted into a dielectric material. For example, the substrate supports may originally be silicon, but can be converted into a dielectric material through thermal oxidation. This step can be accomplished, for example, by first applying a mask (e.g., a nitride hard mask) to the first substrate layer 160 and patterning the mask to expose only the substrate supports. Then, thermal oxidation can be performed to convert the silicon of the substrate supports into silicon dioxide, which is a dielectric material. Although not shown here, the exposed surfaces of the buried volume and the lower surface of the first substrate region can also be converted into a dielectric material. The mask is then removed.

[0089] Next, as Figure 2 Step 340 and Figures 7A to 7C As shown, the embedded volume and multiple vias are filled with a first dielectric material to form an embedded dielectric layer 120 and a first dielectric sidewall 140 surrounding the first substrate region 170. As shown, the first dielectric material and the dielectric material converted from the substrate support are the same, but not necessarily the same.

[0090] The buried dielectric layer can be made of any suitable electrically insulating material. For example, in a particular embodiment, the buried dielectric layer is formed of an oxide (e.g., silicon dioxide) and may be referred to as a buried oxide layer or a BOX (buried oxide layer). However, the buried dielectric layer can also be formed of a nitride, such as silicon nitride.

[0091] Any suitable deposition process can be used. For example, using CVD, a silicon-containing source gas can serve as a silicon precursor that reacts with an oxygen-containing source gas. Exemplary silicon precursors include, but are not limited to, tetraethyl orthosilicate (TEOS), trimethylsilane, tetramethylsilane, and hexachlorodisilane (HCDS). Ozone (O3) can be configured to provide oxygen atoms for the reaction. These gases will react at temperatures of about 300°C to about 500°C or higher to deposit silicon dioxide. The precursor can be blown under the first substrate region to fill the buried volume.

[0092] like Figure 7B As shown, the first dielectric sidewall 140 extends from the buried dielectric layer 120 to the upper surface 102 of the substrate / first substrate layer. For example... Figure 7C As shown, the first dielectric sidewall 140 is ideally solid and ideally does not contain any holes. Therefore, the active region 112 within the first dielectric sidewall is electrically isolated from the body region 110 outside the first dielectric sidewall. Planarization can be performed if necessary.

[0093] Continuing, as Figure 2 Steps 345 and Figures 8A to 8C As shown, a second substrate layer 180 is formed over the substrate / first substrate layer 160. This step can be performed by CVD, PVD, or other suitable methods. The second substrate layer 180 has a height or depth 185 and can also be considered part of the substrate 100. Planarization can be performed if necessary.

[0094] It is worth noting that the second substrate layer 180 does not have a uniform lattice quality. Here, the second substrate layer 180 can be considered to include a second substrate region 190 located above the first substrate region 170. The second substrate layer 180 also includes a sidewall region 182 surrounding the second substrate region 190 and located above the first dielectric sidewall 140. Finally, the second substrate layer 180 also includes a body region 184 located outside the sidewall region 182. The second substrate region 190 has a lattice quality similar to that of the first substrate region 170, and the body region 184 has a lattice quality similar to that of the substrate / first substrate layer 160. However, since the sidewall region 182 is formed or grown on the first dielectric sidewall 140, the lattice quality of the sidewall region 182 is different from that of the second substrate region 190.

[0095] Then, as Figure 2 Step 350 and Figures 9A to 9C As shown, a trench 216 is formed around the second substrate region 190 of the second substrate layer 180. The trench 216 is formed above the first dielectric sidewall 140, and as shown, the sidewall region 182, which has a different lattice quality compared to the second substrate region 190, is removed. Figure 9B As shown, in some specific embodiments, trench 216 has a thickness 217 greater than the thickness 143 of the first dielectric sidewall 140. However, this step is not necessary. For example, trenches can be formed by patterning a mask, then performing dry etching or other etching processes, and subsequently removing the mask.

[0096] Next, as Figure 2 Step 355 and Figures 10A to 10D As shown, trench 216 is filled with a second dielectric material to form a second dielectric sidewall 150 around the second substrate region 190. The combination of the second dielectric sidewall 150 and the first dielectric sidewall 140 forms a vertical dielectric sidewall 130. It should be noted that the first dielectric material and the second dielectric material can be the same material or different materials. In a particular embodiment, both the first dielectric material and the second dielectric material are silicon dioxide. Planarization can be performed if necessary.

[0097] like Figure 10C As shown. The second dielectric sidewall 150 contacts the first dielectric sidewall 140 and extends upward to the upper surface 102 of the substrate / second substrate layer. In some specific embodiments, the thickness 153 of the second dielectric sidewall is greater than the thickness 143 of the first dielectric sidewall. However, this is not always the case. The second dielectric sidewall 150 overlaps with the first dielectric sidewall 140. The dashed line indicates the boundary between the first substrate region 170 and the second substrate region 190. It should be noted that in actual SOI substrates, the first substrate region 170 and the second substrate region 190 are made of the same material and may not be visually distinguishable from each other.

[0098] like Figure 10D As shown, the second dielectric sidewall 150 is ideally solid and ideally does not contain any holes. Therefore, in conjunction with the embedded dielectric layer 120, the active region 112 within the vertical dielectric sidewall is electrically isolated from the body region 110 outside the vertical dielectric sidewall.

[0099] exist Figure 2 In step 360, the upper surface 102 of the SOI substrate can be planarized to obtain a horizontal surface. This step can be performed, for example, by CMP. The resulting SOI substrate 100 is as follows: Figures 10A to 10D As shown.

[0100] Please see Figure 10BA top view is shown. It illustrates the length 171 and width 173 of a first substrate region 170, and the length 191 and width 193 of a second substrate region 190. In certain embodiments, the lengths 171, 191 and the widths 173, 193 can vary independently between about 0.1 micrometers (μm) and about 1000 μm. In some other embodiments, the length 171 and width 173 of the first substrate region 170 are equal to each other (i.e., the first substrate region is square). In other additional embodiments, the length 191 and width 193 of the second substrate region 190 are equal to each other (i.e., the second substrate region is square). In still other embodiments, the length 171 and width 173 of the first substrate region 170 are both greater than the length 191 and width 193 of the second substrate region 190. Thus, in certain embodiments, the surface area of ​​the second substrate region 190 is different from the surface area of ​​the first substrate region 170. As can be seen in the top view, the surface area is the product of the length and width. In some embodiments, the surface area of ​​the second substrate region 190 is larger than the surface area of ​​the first substrate region 170. In some embodiments, the surface area of ​​the second substrate region 190 is smaller than the surface area of ​​the first substrate region 170. See also... Figure 10D In a particular embodiment, the thickness 121 of the embedded dielectric layer 120 may be between about 0.1 μm and about 10 μm. Other ranges and values ​​of the measurements are also within the scope of this disclosure.

[0101] The depths / heights 175 and 195 of the first substrate region 170 and the second substrate region 190 can be varied according to requirements, such as... Figures 11A to 11C As shown. The depth is measured relative to the upper surface 102 of the SOI substrate, and the height is measured relative to the upper surface 122 of the buried dielectric layer 120. Figure 11A As shown, the depth 175 of the first substrate region 170 is less than the depth 195 of the second substrate region 190. For example... Figure 11B As shown, the depth 175 of the first substrate region 170 is approximately the same as the depth 195 of the second substrate region 190. Figure 11C As shown, the depth 175 of the first substrate region 170 is greater than the depth 195 of the second substrate region 190. The relative depths 145 and 155 of the first dielectric sidewall 140 and the second dielectric sidewall 150 also change in the same manner. In a particular embodiment, the depth / height 175 and 195 of the first substrate region 170 and the second substrate region 190 are approximately 0.1 micrometers (μm) to approximately 10 micrometers, respectively. However, other ranges and values ​​are also within the scope of this disclosure.

[0102] The depth / height of the buried dielectric layer 120 in the SOI substrate 100 can also be varied according to requirements, such as Figures 12A to 12CAs shown in the figures, the SOI substrate 100 has a thickness 105 between its upper surface 102 and lower surface 104. The thickness 105 of the SOI substrate 100 is the same in all three figures. The thickness 121 of the buried dielectric layer 120 is the same in all three figures. Figure 12A The depth / height 123 of the upper surface 122 of the embedded dielectric layer 120 is greater than Figure 12B The depth / height 128 of the upper surface 122 of the embedded dielectric layer 120. Figure 12B The depth / height 128 of the upper surface 122 of the embedded dielectric layer 120 is greater than Figure 12C The depth / height 129 of the upper surface 122 of the embedded dielectric layer 120. The thickness 105 of the SOI substrate 100 can also be changed according to requirements.

[0103] The ratio of the depth / height 195 of the second substrate region 190 to the depth / height 175 of the first substrate region 170 can be varied according to requirements, such as... Figures 13A to 13C As shown. The depth 127 of the dielectric layer 120 is the same in all three figures. Figure 13A As shown, the depth 195 of the second substrate region 190 is less than the depth 175 of the first substrate region 170; therefore, the ratio of depth 195 to depth 175 is less than 1. Figure 13B As shown, the depth 195 of the second substrate region 190 is approximately the same as the depth 175 of the first substrate region 170; therefore, the ratio of depth 195 to depth 175 is close to 1. Figure 13C As shown, the depth 195 of the second substrate region 190 is greater than the depth 175 of the first substrate region 170; therefore, the ratio of depth 195 to depth 175 is greater than 1. In a particular embodiment, the ratio of the depth 195 of the second substrate region 190 to the depth 175 of the first substrate region 170 is from about 0.1 to about 100. However, other ranges and values ​​are also within the scope of this disclosure.

[0104] The thickness of the second dielectric sidewall 150 can be varied according to requirements, such as... Figures 14A to 14C As shown. Figure 14A The thickness is 153 less than Figure 14B The thickness is 157. In Figure 14A and Figure 14B In the first dielectric sidewall 140, the thicknesses 153 and 157 of the second dielectric sidewall 150 are both greater than the thickness 143. Similarly, Figure 14C The thickness is 159 less than Figure 14A The thickness is 153. In Figure 14C In the middle, part of the sidewall region 182 (see Figure 8BThe first dielectric sidewall 140 still exists around the second dielectric sidewall 150. Here, the thickness 159 of the second dielectric sidewall 150 is less than the thickness 143 of the first dielectric sidewall 140. The first dielectric sidewall 140 and the second dielectric sidewall 150 always overlap. This maintains the electrical isolation between the active region 112 and the body region 110.

[0105] In a particular embodiment, the thicknesses 153 and 143 of the second dielectric sidewall 150 and the first dielectric sidewall 140 are approximately 0.1 micrometers (μm) to approximately 10 micrometers, respectively. However, other ranges and values ​​are also within the scope of this disclosure.

[0106] like Figure 14A and Figure 14B As shown, in a particular embodiment, the overlap 133 between the first dielectric sidewall 140 and the second dielectric sidewall 150 is at least 0.040 micrometers (i.e., 40 nanometers). Other non-zero values ​​and ranges are also within the scope of this disclosure.

[0107] In the aforementioned figures, the second dielectric sidewall 150 is depicted as being located in the middle above the first dielectric sidewall 140. However, this is not always the case. Figures 15A to 15D Different embodiments of the second dielectric sidewall 150 being offset relative to the first dielectric sidewall 140 along the Y-axis are illustrated, for example, this could occur due to an overlap offset of the lithography mask. Figure 15A As shown, the second dielectric sidewall 150 moves in the negative direction (i.e., to the left) along the Y-axis; therefore, a portion of the sidewall region 182 is depicted. Figure 15B As shown, the second dielectric sidewall 150 is shifted along the Y-axis in the positive direction (i.e., to the right), and a portion of the sidewall region 182 is also depicted. Figure 15C As shown, the thickness 153 of the second dielectric sidewall 150 is less than the thickness 143 of the first dielectric sidewall 140. Furthermore, the second dielectric sidewall 150 moves in the negative direction along the Y-axis. Figure 15D As shown, the second dielectric sidewall 150 moves in the positive direction along the Y-axis. It is worth noting that in these four figures, the second dielectric sidewall 150 still fully overlaps with the first dielectric sidewall 140 to ensure electrical isolation.

[0108] like Figures 16A to 16D As shown, the depth / height 155 of the second dielectric sidewall 150 can be changed. Figure 16A An embodiment is illustrated in which the second dielectric sidewall 150 is located above and in contact with the first dielectric sidewall 140. Here, the length 171 of the first substrate region 170 is greater than the length 191 of the second substrate region 190.

[0109] However, in Figure 16BIn this case, there is no first dielectric sidewall. Instead, the second dielectric sidewall 150 contacts the upper surface 122 of the buried dielectric layer 120; therefore, the length 171 of the first substrate region 170 is approximately equal to the length 191 of the second substrate region 190. Similarly, in Figure 16C In this embodiment, there is no first dielectric sidewall. Instead, the second dielectric sidewall 150 contacts the side surface 126 of the buried dielectric layer 120. In other words, the length 119 of the buried dielectric layer 120 is approximately equal to the length 171 of the first substrate region 170 and the length 191 of the second substrate region 190. In this embodiment, the depth / height 155 of the second dielectric sidewall 150 is greater than the depth 123 of the upper surface 122 of the buried dielectric layer 120, but less than the depth 125 of the lower surface 124 of the buried dielectric layer. Figure 16D As shown, the depth / height 155 of the second dielectric sidewall 150 is greater than the depth 125 of the lower surface 124 of the embedded dielectric layer 120. Please return to Figures 9A to 9C For example, trenches 216 can be formed by etching deeper, down to and possibly beyond the buried dielectric layer 120, to create a more advanced dielectric layer. Figures 16B to 16D The structure shown. Then, in some embodiments, [the following is performed]. Figure 2 The etching step 350 is a multi-step process that can use different etchants to remove the sidewall region 182 and embed the dielectric layer 120 (made of different materials).

[0110] The embedded dielectric layer 120 and dielectric sidewalls 130, 140, 150 can be made of any suitable electrical insulating material and can be the same or different materials. Suitable examples of electrically insulating materials (i.e., dielectric materials) may include oxides, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium dioxide (ZrO2), or hafnium dioxide (HfO2); nitrides, such as silicon nitride (SiN) or silicon oxynitride (SiON); silicates such as hafnium silicate (HfSiO4) or zirconium silicate (ZrSiO4); silicon carbide; polycrystalline silicon; phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), borosilicate glass (BSG), high-k dielectric materials, or low-k dielectric materials.

[0111] It should also be noted that some related steps are not explicitly described in the above discussion. For example, a pattern / structure can be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer to form a mask, and then etching through the mask to transfer the pattern to the given layer.

[0112] Generally, photoresist layers can be applied by methods such as spin coating, spray coating, roll coating, dip coating, or extrusion coating. Typically, in spin coating, the substrate is placed on a rotating platform, which may include vacuum chucks to hold the substrate in place. The photoresist layer composition is then applied to the center of the substrate. The speed of the rotating platform is then increased to evenly spread the photoresist layer from the center of the substrate to its periphery. The rotation speed of the platen is then fixed, thereby controlling the final thickness of the photoresist layer.

[0113] Next, the photoresist composition is baked or cured to remove the solvent and harden the photoresist layer. In some specific embodiments, baking is performed at a temperature of about 90°C to about 110°C. A hot plate, oven, or similar equipment can be used for baking. Thus, a photoresist layer is formed on the substrate.

[0114] The photoresist layer is then patterned by exposing it to radiation, which can be any wavelength of light carrying the desired mask pattern. In a particular embodiment, EUV light with a wavelength of approximately 13.5 nm is used for patterning because this step allows for smaller feature sizes. This exposes certain portions of the photoresist layer to radiation while leaving other portions unexposed. This exposure causes some portions of the photoresist to become soluble in the developer, while others remain insoluble.

[0115] Additional photoresist baking steps (post-exposure bake, or PEB) can be performed after exposure to radiation. For example, this step may help release acid leaving groups (ALGs) or other molecules that are important in chemically amplified photoresists.

[0116] The photoresist layer is then developed using a developer. The developer can be an aqueous solution or an organic solvent. The soluble portions of the photoresist layer dissolve and are washed away during the development step, leaving the photoresist pattern (i.e., the mask). A common example of a developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Generally, any suitable developer can be used. Sometimes, post-development baking or "hard baking" can be performed to stabilize the developed photoresist pattern, thereby achieving optimal performance in subsequent steps.

[0117] Next, the portion of the given layer located beneath the patterned photoresist mask is now exposed. Etching is performed to transfer the photoresist pattern to the given layer beneath the patterned photoresist mask. After use, the mask can be removed, for example, at elevated temperatures using various solvents such as N-methyl-pyrrolidone (NMP) or alkaline media or other stripping agents, or by dry etching using oxygen plasma.

[0118] Generally, any etching step described herein may be performed using wet etching, dry etching, or plasma etching processes (e.g., reactive ion etching (RIE) or inductively coupled plasma (ICP)) or combinations thereof, as appropriate. Etching can be anisotropic. Depending on the material, etchants may include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), fluorinated carbon, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BCl3), ammonia (NH3), bromine (Br2), etc., or various proportions thereof. For example, hydrofluoric acid and ammonium fluoride can be used for wet etching of silicon dioxide. Alternatively, various mixtures of CHF3, O2, CF4 and / or H2 can be used for dry etching of silicon dioxide.

[0119] The resulting SOI substrate can then be used in the production of semiconductor devices. Figure 17 This is a Y-axis cross-sectional view showing several different types of semiconductor devices on the SOI substrate 100.

[0120] The first semiconductor device (starting from the left) is a planar transistor 400. As shown, a gate dielectric layer 410 exists on the substrate 100. A gate electrode 412 is located on the gate dielectric layer 410, and one or more dielectric spacers 414 exist around the gate electrode 412. The gate electrode 412 is located between two source / drain (S / D) electrodes 416.

[0121] The second semiconductor device is a FinFET transistor 401. The substrate 100 may be formed to include at least one fin 418. Two shallow trench isolation (STI) regions 420 are shown on either side of the fin. A gate dielectric layer 410 is present on three sides of the fin 418. A gate electrode 412 is located on the gate dielectric layer 410 and also surrounds the three sides of the fin 418. The S / D electrode is positioned along the X-axis and is not visible in this cross-sectional view.

[0122] The third semiconductor device is a gate-all-around (GAA) transistor 402. Two STI regions 420 are shown on either side of the semiconductor fin 418. Multiple semiconductor channels 422 are also located above the fin 418. Gate electrodes 412 surround the semiconductor channels. The S / D electrodes are positioned along the X-axis and are not visible in this cross-sectional view.

[0123] The fourth (rightmost) semiconductor device is a laterally diffused metal oxide semiconductor (LDMOS) device 403. This structure is similar to a planar transistor and includes a gate electrode 412 located on a gate dielectric layer 410, one or more dielectric spacers 414 surrounding the gate electrode 412, and two source / drain (S / D) electrodes 416. Additionally, an STI region 424 exists in the drift region between the gate electrode 412 and the S / D electrode 416.

[0124] In each device, via 428 extends through the interlayer dielectric (ILD) layer 426 to reach the gate electrode 412 and the S / D electrode 416. Other semiconductor devices or structures may also be formed on or within the active region 112 of the SOI substrate.

[0125] Figure 18 This is a flowchart of a method 500 for forming a semiconductor device on an SOI substrate according to some embodiments, and the method is combined with Figure 17 Note: Although the method steps are discussed below for forming a single device, this description should be broadly interpreted as applicable to the simultaneous formation of multiple devices. The method also describes the formation of planar transistors or LDMOS transistors, but can be appropriately configured to form other devices. Other structures can also be formed simultaneously. It should be noted that not all steps described in the flowchart are necessary.

[0126] This method begins Figure 18 In step 505, the SOI substrate 100 is received. Then, in step 510, one or more isolation regions 420 are formed in the active region 112 of the substrate 100. The isolation regions can be, for example, shallow trench isolation (STI) regions or deep trench isolation (DTI) regions. The isolation regions are formed by patterning the substrate, etching isolation trenches, and filling the trenches with a dielectric material. The dielectric material can be deposited using CVD, PVD, or spin-coating processes known in the art, or it can be grown by oxidation. If necessary, the dielectric material can be deposited to a height above the upper surface 102 and then recessed back to the desired height.

[0127] Next, in Figure 18 In step 515, a gate dielectric layer 410 is formed on the substrate 100. Again, the gate dielectric layer can be formed using CVD, PVD, atomic layer deposition (ALD), ion implantation, or other suitable deposition processes. Thermal oxidation can also be used. The gate dielectric layer 410 is formed between the isolation regions 420. Then, in step 520, a gate electrode 412 is formed on the gate dielectric layer 410. This step can be performed using CVD, PVD, or other suitable processes. In a particular embodiment, the gate precursor layer is made of polysilicon. Next, in... Figure 18 In step 525, the STI region 424 can be formed to one side of the gate electrode. This helps to reduce hot carrier injection. Figure 18 In step 530, at least one dielectric gate spacer 414 may be formed on the sidewall of the gate electrode 412. For example, from a top view (not shown), a gate spacer may surround all sides of the gate electrode. The gate spacer 414 is vertical and has a relatively narrow width. The gate spacer 414 may be made of a dielectric material and is configured for electrical isolation of the gate electrode. The gate spacer 414 may be fabricated by CVD, PVD, ALD, or other deposition techniques. Then, in step 535, source / drain (S / D) electrodes 416 are formed on opposite sides of the gate electrode 412. The source / drain (S / D) electrodes 416 may be formed by doping the silicon substrate using ion implantation or other suitable methods, or by patterning and depositing a suitable metal. Next, in Figure 18 In step 540, an interlayer dielectric (ILD) layer 426 is formed over the substrate 100. Then, in step 545, vias 428 are formed on the gate electrode 412 and the two S / D electrodes 416.

[0128] Such semiconductor devices can be incorporated into larger semiconductor packages and larger devices. These packages can further include various interconnect structures configured for communication with other semiconductor devices. The semiconductor device can be configured in power management devices; BCD (Bipolar-CMOS-DMOS) circuits configured to drive discrete high-voltage components; image signal processors (ISPs); liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), active-matrix OLEDs (AMOLEDs), or quantum dot LEDs (QLEDs) display panels; image sensors can be configured in systems such as mobile phones and facial recognition systems, or as motion sensors for automotive applications, security applications, energy efficiency, etc.

[0129] The SOI substrate disclosed herein offers several advantages. Complete electrical isolation provides better device performance and the ability to withstand higher voltages, which is highly beneficial for high-voltage applications. The SOI substrate can be manufactured using in-house processes. The ability to use different dielectric materials reduces parasitic capacitance and provides design flexibility.

[0130] Therefore, some embodiments disclosed herein relate to a method configured for forming a silicon-on-insulator (SOI) substrate. A sacrificial layer is formed in the substrate, and a first substrate layer is formed above the sacrificial layer. A plurality of vias extending to the sacrificial layer are formed around a first substrate region of the first substrate layer. The sacrificial layer is etched away to form a buried volume, wherein the first substrate region is connected to the first substrate layer by a plurality of substrate supports. The substrate supports are then converted into a dielectric material. The buried volume and the plurality of vias are subsequently filled with the first dielectric material to form a buried dielectric layer and a first dielectric sidewall around the first substrate region. A second substrate layer is formed above the first substrate layer. A trench is formed around a second substrate region of the second substrate layer. The trench is filled with a second dielectric material to form a second dielectric sidewall around the second substrate region. In some embodiments, the sacrificial layer and the first substrate layer are formed by: forming a sacrificial layer in the upper surface of the substrate; and depositing the first substrate layer above the upper surface of the substrate. In some embodiments, the sacrificial layer and the first substrate layer are formed by: implanting a plurality of ions into the substrate to form a sacrificial layer, wherein the first substrate layer is a layer of the substrate located above the sacrificial layer. In some embodiments, the method further includes planarizing the second substrate layer after forming the second dielectric sidewall. In some embodiments, the first dielectric material is deposited by chemical vapor deposition. In some embodiments, a selective gas etchant is used to etch away the sacrificial layer. In some embodiments, the substrate support is converted into a dielectric material by oxidation. In some embodiments, the first and second dielectric materials are silicon dioxide. In some embodiments, the depth of the second substrate region is greater than the depth of the first substrate region. In some embodiments, the surface area of ​​the second substrate region is smaller than the surface area of ​​the first substrate region. In some embodiments, the thickness of the second dielectric sidewall is greater than the thickness of the first dielectric sidewall. In some embodiments, the second substrate region is located above the middle of the first substrate region, not along the width and length of the second substrate region. In some embodiments, a trench formed around the second substrate region extends downward to the first dielectric sidewall. In some embodiments, forming the trench around the second substrate region removes the first dielectric sidewall.

[0131] Other embodiments disclosed herein relate to silicon-on-insulator (SOI) substrates. A buried dielectric layer is located within the substrate. Dielectric sidewalls extend from the buried dielectric layer to the upper surface of the substrate. The dielectric sidewalls surround a first substrate region and a second substrate region located above the first substrate region. The area of ​​the second substrate region differs from the area of ​​the first substrate region (when measured from a top view). In some embodiments, the area of ​​the second substrate region is smaller than the area of ​​the first substrate region. In some embodiments, the second substrate region is not located above the middle of the first substrate region along its width and length. In some embodiments, the dielectric sidewalls include a first dielectric sidewall located below the second dielectric sidewall, and the thickness of the first dielectric sidewall differs from the thickness of the second dielectric sidewall.

[0132] Methods for forming semiconductor devices are also described in the embodiments disclosed herein. A silicon-on-insulator (SOI) substrate is received, and the SOI substrate has the structure described above. A source / drain electrode is formed in a second substrate region. A gate dielectric layer is formed on the second substrate region. A gate electrode is formed on the gate dielectric layer. Such semiconductor devices on SOI substrates are also disclosed. In some embodiments, the method further includes forming an isolation region in the second substrate region.

[0133] The embodiments disclosed herein further describe a silicon-on-insulator (SiI) substrate. The SiI substrate includes a substrate, a buried dielectric layer, a first dielectric sidewall, and a second dielectric sidewall. The substrate includes a first substrate layer and a second substrate layer located above the first substrate layer. The buried dielectric layer is located below the first substrate layer and contacts the bottom of the first substrate layer. The first dielectric sidewall surrounds the sidewall of the first substrate layer. The second dielectric sidewall surrounds the sidewall of the second substrate layer. In some embodiments, the top surface of the second substrate layer is coplanar with the top surface of the second dielectric sidewall. In some embodiments, the depth of the second substrate layer is greater than the depth of the first substrate layer. In some embodiments, the surface area of ​​the second substrate layer is greater than the surface area of ​​the first substrate layer. In some embodiments, the thickness of the second dielectric sidewall is greater than the thickness of the first dielectric sidewall. In some embodiments, the first substrate layer includes the second substrate layer located above the middle of the first substrate layer, not along the width and length of the second substrate layer.

[0134] The embodiments disclosed herein further describe a silicon-on-insulator (SiI) substrate. The SiI substrate includes a substrate, a plurality of source / drain electrodes, a gate dielectric layer, and a gate electrode. The substrate includes a buried dielectric layer and vertical dielectric sidewalls. The buried dielectric layer is located within the substrate. The vertical dielectric sidewalls extend from the buried dielectric layer to the upper surface of the substrate. The vertical dielectric sidewalls surround a first substrate region and a second substrate region located above the first substrate region. The surface area of ​​the second substrate region is different from that of the first substrate region. The source / drain electrodes are located within the second substrate region. The gate dielectric layer is located on the second substrate region. The gate electrode is located on the gate dielectric layer.

[0135] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other fabrications and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A silicon-on-insulator substrate, characterized in that, include: A substrate includes a first substrate layer and a second substrate layer located above the first substrate layer; An embedded dielectric layer is located below the first substrate layer and in contact with a bottom of the first substrate layer; A first dielectric sidewall surrounds one sidewall of the first substrate layer; and A second dielectric sidewall surrounds one sidewall of the second substrate layer.

2. The silicon-on-insulator substrate as described in claim 1, characterized in that, The top surface of the second substrate layer is coplanar with the top surface of the second dielectric sidewall.

3. The silicon-on-insulator substrate as described in claim 1, characterized in that, The depth of the second substrate layer is greater than the depth of the first substrate layer.

4. The silicon-on-insulator substrate as described in claim 1, characterized in that, The surface area of ​​the second substrate layer is greater than the surface area of ​​the first substrate layer.

5. The silicon-on-insulator substrate as described in claim 1, characterized in that, The thickness of the second dielectric sidewall is greater than the thickness of the first dielectric sidewall.

6. The silicon-on-insulator substrate as claimed in claim 1, characterized in that, The first substrate layer includes the second substrate layer which is located above the middle of the first substrate layer, not along a width and a length of the second substrate layer.

7. A silicon-on-insulator substrate, characterized in that, include: An embedded dielectric layer is located in a substrate; and A dielectric sidewall extends from the embedded dielectric layer to an upper surface of the substrate. The dielectric sidewall surrounds a first substrate region and a second substrate region located above the first substrate region; The area of ​​the second substrate region is different from the area of ​​the first substrate region.

8. The silicon-on-insulator substrate as described in claim 7, characterized in that, The area of ​​the second substrate region is smaller than the area of ​​the first substrate region.

9. The silicon-on-insulator substrate as claimed in claim 7, characterized in that, The second substrate region is located above the middle of the first substrate region, not along a width and a length of the second substrate region.

10. A silicon-on-insulator substrate, characterized in that, include: A substrate, comprising: A dielectric layer is embedded in the substrate; as well as A vertical dielectric sidewall extends from the embedded dielectric layer to an upper surface of the substrate. The vertical dielectric sidewall surrounds a first substrate region and a second substrate region located above the first substrate region; The surface area of ​​the second substrate region is different from the surface area of ​​the first substrate region; Multiple source / drain electrodes are located in the second substrate region; A gate dielectric layer is located on the second substrate region; and A gate electrode is located on the gate dielectric layer.

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