Dual-modulation phototransistor and electronic device

Abstract

The utility model relates to the technical field of semiconductor storage, disclose a kind of dual regulation photoelectric transistor and electronic device, dual regulation photoelectric transistor includes substrate layer, first doped layer, second doped layer, source electrode layer, drain electrode layer, insulating dielectric layer, photosensitive layer and gate electrode layer;Substrate layer is spaced apart and is provided with the first doped area and the second doped area of patterning on it;First doped layer is located in first doped area;Second doped layer is located in second doped area;Channel region is formed between first doped layer and second doped layer;Source electrode layer is located on first doped layer;Drain electrode layer is located on second doped layer;Insulating dielectric layer is located on channel region;Photosensitive layer is located on insulating dielectric layer;Gate electrode layer is located on photosensitive layer. Only the photogenerated carrier generated by photosensitive layer is used to realize storage function, simplify device structure;Through insulating dielectric layer fixed photogenerated carrier, improve the storage stability of device, optimize performance, improve application value.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor storage technology, and in particular to a dual-controlled phototransistor and electronic device. Background Technology

[0002] Optoelectronic memory is a technology that utilizes optical principles and the photoelectric effect to store and retrieve data, combining the characteristics of optical and electronic storage. The rapid development of neural networks has further spurred research into optoelectronic memory devices. Currently, research on optoelectronic memory devices is still in its early stages, with three main mechanisms being studied: photochromic mechanisms, photo-assisted tunneling mechanisms, and defect-trapped photogenerated carrier mechanisms.

[0003] However, existing optoelectronic storage devices require high-voltage driving to achieve the function of capturing charge carriers. Moreover, during long-term use, material defects will gradually release the captured charge carriers, resulting in unstable storage performance and affecting the application value of optoelectronic storage devices.

[0004] Furthermore, most reported optoelectronic memory devices are based on two-dimensional semiconductor, oxide semiconductor, and organic semiconductor transistors, which are still in the research stage and difficult to rapidly achieve industrial applications. Therefore, it is necessary to develop novel optoelectronic memory devices based on mature silicon-based transistors. Utility Model Content

[0005] In view of the shortcomings of the prior art, the purpose of this utility model is to provide a dual-controlled silicon-based phototransistor and electronic device, which aims to solve the problems that existing photoelectric storage devices require high energy consumption to drive, have unstable storage performance, and thus have low application value.

[0006] The technical solution of this utility model is as follows: A dual-controlled phototransistor, comprising: A substrate layer, wherein patterned first doped regions and second doped regions are disposed at intervals on the substrate layer; A first doped layer is disposed in the first doped region; A second doped layer is disposed in the second doped region; and a channel region is formed between the first doped layer and the second doped layer. The source electrode layer is disposed on the first doped layer; A drain electrode layer is disposed on the second doped layer; An insulating dielectric layer is disposed on the channel region; A photosensitive layer is disposed on the insulating dielectric layer; A gate electrode layer is disposed on the photosensitive layer.

[0007] The dual-controlled phototransistor, wherein the photosensitive layer is a wide-bandgap semiconductor layer, and the photosensitive layer includes any one of an inorganic metal oxide layer, an inorganic metal nitride layer, an inorganic non-metal nitride layer, and an organic polymer layer.

[0008] In the dual-controlled phototransistor, the photosensitive layer is any one of gallium oxide, boron nitride, aluminum nitride, and zinc oxide.

[0009] In the dual-controlled phototransistor, the insulating dielectric layer is any one of a silicon dioxide layer, an aluminum oxide layer, a hafnium oxide layer, an aluminum nitride layer, a boron nitride layer, and an insulating polymer layer.

[0010] The dual-controlled phototransistor wherein the doping types of the first doped layer and the second doped layer are opposite to the doping type of the substrate layer.

[0011] The dual-controlled phototransistor, wherein the substrate is a P-type silicon wafer or an N-type silicon wafer.

[0012] The dual-controlled phototransistor, wherein the source electrode layer is any one of an indium tin oxide layer, a molybdenum alloy layer, a titanium alloy layer, a copper alloy layer, a chromium alloy layer, a gold layer, a nickel alloy layer, an aluminum alloy layer, and a graphene layer; and / or, the drain electrode layer is any one of an indium tin oxide layer, a molybdenum alloy layer, a titanium alloy layer, a copper alloy layer, a chromium alloy layer, a gold layer, a nickel alloy layer, an aluminum alloy layer, and a graphene layer.

[0013] In the aforementioned dual-controlled phototransistor, the gate electrode layer is any one of a platinum electrode layer, a gold electrode layer, or a palladium electrode layer.

[0014] In the dual-controlled phototransistor, the heights of the drain electrode layer, the source electrode layer, and the insulating dielectric layer are equal.

[0015] This application also discloses an electronic device comprising a dual-controlled phototransistor as described in any of the preceding descriptions.

[0016] Compared with the prior art, the embodiments of this utility model have the following beneficial effects: The dual-controlled phototransistor disclosed in this invention combines an insulating dielectric layer and a photosensitive layer on a substrate. When energized, the photosensitive layer generates photogenerated carriers under ultraviolet light irradiation. Simultaneously, under a fixed positive or negative gate voltage, the photogenerated carriers move directionally and accumulate at the interface between the photosensitive layer and the insulating dielectric layer, thus storing the signal. Furthermore, the insulating dielectric layer has no charge, therefore it does not interfere with the photogenerated carriers, improving the stability of their accumulation. It is evident that the phototransistor disclosed in this invention stores all volumetric charge from the photosensitive layer, eliminating the need for a floating gate layer, simplifying the device structure, saving costs, and improving device stability, thereby enhancing the application value of the phototransistor. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a dual-controlled phototransistor in one embodiment of the present invention; Figure 2 This is the transfer curve of the phototransistor after exposure to 254nm ultraviolet light in one embodiment of the present invention; Figure 3 This is a state diagram of the phototransistor during 2000 erase-write cycles in one embodiment of the present invention.

[0019] Among them, 10 is the substrate layer; 20 is the first doped layer; 30 is the second doped layer; 40 is the source electrode layer; 50 is the drain electrode layer; 60 is the insulating dielectric layer; 70 is the photosensitive layer; and 80 is the gate electrode layer. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Variations in the shapes shown in the accompanying drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the accompanying drawings, but include changes in shape that may occur during manufacturing.

[0022] As used herein, the term “and / or” includes any one of the relevant items listed and any combination of any two or more items.

[0023] Although terms such as “first,” “second,” and “third” may be used herein to describe individual components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Therefore, without departing from the teachings of the examples described herein, the first component, assembly, region, layer, or part referred to as the second component, assembly, region, layer, or part may also be referred to as the second component, assembly, region, layer, or part.

[0024] For ease of description, spatial relational terms such as “above,” “upper,” “below,” and “lower” are used herein to describe the relationship between one element and another, as shown in the accompanying drawings. Such spatial relational terms are intended to encompass not only the orientation depicted in the drawings but also different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as being “above” or “upper” relative to another element will subsequently be “below” or “lower” relative to that other element. Therefore, the term “above” includes both “above” and “below” orientations depending on the spatial orientation of the device. The device may also be positioned in other ways, and the spatial relational terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing various examples only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms “comprising,” “including,” and “having” enumerate the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0026] There are three main mechanisms in the research of mainstream optoelectronic storage devices in the current technology: photochromic mechanism, photo-assisted tunneling mechanism, and defect trapping photogenerated carrier mechanism.

[0027] (1) Photochromic mechanism. Photochromic materials are usually small organic molecules that undergo reversible photochemical reactions under different light irradiations, resulting in bonded and non-bonded isomers. These two isomers have different resistances, thus producing different electrical states. However, if they are embedded in organic semiconductors for large-scale application, it will affect the performance of the organic semiconductors because it changes the composition of the organic semiconductors. However, if they are synthesized into thin films on their own and used, their complex synthesis and poor stability will prevent them from being applied on a large scale.

[0028] (2) Optical-assisted tunneling. The optical-assisted tunneling structure borrows from the conventional flash memory structure and replaces its channel layer with a photosensitive layer. However, it cannot avoid the requirement to use a high gate voltage (programming voltage), which results in its high power consumption.

[0029] (3) Defect-captured photogenerated carriers. This mechanism is currently the mainstream mechanism in optoelectronic storage device design. This mechanism involves intentionally or unintentionally introduced defect states at the active layer or its interface. After illumination, photogenerated carriers are generated within the material, and some are captured by the defects. After illumination ends, the defects do not immediately release these photogenerated carriers but instead bind them, forming a certain bias voltage. However, this mechanism has a short storage time because the defects gradually release the captured photogenerated carriers over time. Furthermore, the defects themselves are complex and difficult to control, making it difficult to guarantee uniformity.

[0030] The current mainstream research trend in optoelectronic memories is to utilize defect mechanisms to form storage capabilities. Two-dimensional materials such as graphene, boron nitride, and disulfides or ditellurides of transition metals (such as molybdenum disulfide and tungsten disulfide) are used to form two-dimensional van der Waals heterostructures. Defect states at the interface are then used to trap charge carriers, achieving signal storage. This direction mainly focuses on multi-state storage capabilities and the high carrier mobility offered by two-dimensional materials. However, the defect trapping mechanism represented by this mainstream device type, as well as the other two mechanisms, share some common problems: The organic molecules in the photochromic mechanism require high voltage to drive them, and the tunneling mechanism also inevitably brings high voltage. The photogenerated carriers trapped by defects require high gate voltage to be released on a large scale. Therefore, the operating voltage of the currently reported optoelectronic memory devices is generally greater than 20V, which cannot be integrated into conventional CMOS circuits, and also introduces high power consumption.

[0031] Organic molecules in the photochromic mechanism require high light intensity to successfully break and form chemical bonds; due to the physical size of the material itself and the inability to apply particularly high voltage, a high light power density is required to generate enough photogenerated carriers for tunneling; and defects also require the material to generate enough photogenerated carriers at a high light power density in order to meet the requirements for the number of captured carriers.

[0032] Therefore, existing optoelectronic storage devices still have drawbacks such as high power consumption and unstable storage performance.

[0033] See Figure 1 In one embodiment of this utility model application, a dual-controlled phototransistor is disclosed, comprising a substrate layer 10, a first doped layer 20, a second doped layer 30, a source electrode layer 40, a drain electrode layer 50, an insulating dielectric layer 60, a photosensitive layer 70, and a gate electrode layer 80. The substrate layer 10 has patterned first and second doped regions spaced apart. The first doped layer 20 is disposed in the first doped region; the second doped layer 30 is disposed in the second doped region; and a channel region is formed between the first doped layer 20 and the second doped layer 30. The source electrode layer 40 is disposed on the first doped layer 20; the drain electrode layer 50 is disposed on the second doped layer 30; the insulating dielectric layer 60 is disposed in the channel region; the photosensitive layer 70 is disposed on the insulating dielectric layer 60; and the gate electrode layer 80 is disposed on the photosensitive layer 70.

[0034] The dual-controlled phototransistor disclosed in this embodiment is a metal-oxide-semiconductor field-effect transistor. An insulating dielectric layer 60 and a photosensitive layer 70 are combined and disposed on a substrate layer 10. When energized, the photosensitive layer 70 generates photogenerated carriers under ultraviolet light irradiation. Simultaneously, under a fixed positive or negative gate voltage, the photogenerated carriers move directionally and accumulate at the interface between the photosensitive layer 70 and the insulating dielectric layer 60, thus storing the signal. Furthermore, the insulating dielectric layer 60 has no charge, therefore it does not interfere with the photogenerated carriers, improving the stability of the photogenerated carrier accumulation.

[0035] As can be seen, the volumetric charge storage in the phototransistor disclosed in this embodiment all originates from the photosensitive layer 70, eliminating the need for a floating gate layer. This simplifies the device structure, saves costs, and improves the device's stability, thereby enhancing the application value of the phototransistor. It has promising applications in machine learning, neuromorphic computing, image data processing and storage, as well as light-controlled logic circuits and computing.

[0036] Specifically, in another embodiment of this application, the photosensitive layer 70 is disclosed as an amorphous gallium oxide (Ga2O3) wide-bandgap semiconductor layer prepared by magnetron sputtering under oxygen-bearing conditions. More specifically, the photosensitive layer 70 includes any one of an inorganic metal oxide layer, an inorganic metal nitride layer, an inorganic non-metal nitride layer, and an organic polymer layer. In another embodiment of this application, the photosensitive layer 70 is disclosed as any one of a gallium oxide layer, a boron nitride layer, an aluminum nitride layer, and a zinc oxide layer.

[0037] Specifically, as another embodiment of this application, the insulating dielectric layer 60 is disclosed to be any one of a silicon dioxide layer, an aluminum oxide layer, a hafnium oxide layer, an aluminum nitride layer, a boron nitride layer, and an insulating polymer layer.

[0038] Specifically, as another embodiment of this application, it is disclosed that the doping types of the first doped layer 20 and the second doped layer 30 are opposite to the doping type of the substrate layer 10.

[0039] Specifically, as another embodiment of this application, the substrate layer 10 is disclosed to be a P-type silicon wafer or an N-type silicon wafer.

[0040] Specifically, as another embodiment of this application, the source electrode layer 40 is disclosed as any one of indium tin oxide, molybdenum alloy, titanium alloy, copper alloy, chromium alloy, gold, nickel alloy, aluminum alloy, and graphene; or, the drain electrode layer 50 is any one of indium tin oxide, molybdenum alloy, titanium alloy, copper alloy, chromium alloy, gold, nickel alloy, aluminum alloy, and graphene. Alternatively, the source electrode layer 40 and the drain electrode layer 50 are made of the same material, both being any one of indium tin oxide, molybdenum alloy, titanium alloy, copper alloy, chromium alloy, gold, nickel alloy, aluminum alloy, and graphene.

[0041] Specifically, as another embodiment of this application, the gate electrode layer 80 is disclosed to be any one of a platinum electrode layer, a gold electrode layer, or a palladium electrode layer.

[0042] Specifically, as another embodiment of this application, the heights of the drain electrode layer 50, the source electrode layer 40, and the insulating dielectric layer 60 are disclosed to be equal, which is beneficial to forming a flat surface to form a flat photosensitive layer 70, and facilitates the manufacture of a stable device structure.

[0043] Specifically, the principle of optoelectronic storage is as follows: Taking the electronically conductive metal-oxide-semiconductor field-effect transistor of this application as an example, under a fixed negative gate voltage, ultraviolet light is applied, and photosensitive layer 70 generates photogenerated carriers. Because a negative gate voltage is applied, an electric field is generated in photosensitive layer 70 from insulating dielectric layer 60 to gate electrode layer 80. The generated photogenerated electrons move towards insulating dielectric layer 60, and after a certain number accumulate, a certain negative bias voltage is formed, causing the transfer curve to shift to the left.

[0044] Under a fixed forward gate voltage, ultraviolet light irradiation is applied, and photogenerated carriers are generated in the photosensitive layer 70. Because a forward gate voltage is applied, an electric field is generated in the photosensitive layer 70 from the gate electrode layer 80 to the insulating dielectric layer 60. The generated photogenerated holes move towards the insulating dielectric layer 60. After a certain number accumulate, a certain forward bias voltage is formed, causing the transfer curve to shift to the right.

[0045] Under specific readout voltage conditions, a leftward shift in the transfer curve indicates an increase in current; a rightward shift indicates a decrease in current. Without applied light, the current remains stable. Therefore, the dual-controlled phototransistor disclosed in this embodiment achieves signal storage functionality.

[0046] In this embodiment, the storage function relies on the combined action of the photosensitive layer 70 and the insulating dielectric layer 60; neither can be omitted. The key to the storage capacity lies in the interface between the photosensitive layer 70 and the insulating dielectric layer 60.

[0047] Detailed description of amorphous gallium oxide (GaO) as the photosensitive layer 70, prepared by magnetron sputtering. During the growth of this amorphous GaO, a certain amount of oxygen is introduced, resulting in a low concentration of oxygen defects. When exposed to ultraviolet light, the GaO material grown in this way significantly suppresses the persistent photoconductivity caused by defects due to its low oxygen defect concentration.

[0048] The continuous photoconductivity effect can prevent photogenerated carriers generated under ultraviolet radiation from recombining in a timely manner, which seriously affects storage performance.

[0049] Therefore, in this embodiment, suppressing the continuous photoconductivity effect can stably gather photogenerated carriers, thereby improving the storage performance of the device. It can be concluded that amorphous gallium oxide wide-bandgap semiconductor grown by magnetron sputtering with oxygen is irreplaceable as the photosensitive layer 70.

[0050] Furthermore, the insulating dielectric layer 60 disclosed in this embodiment assists in fixing the generated photogenerated charge carriers. The insulating dielectric layer 60 is made of silicon dioxide (SiO2), for example. It needs to have high insulation properties to impede the flow of charge carriers and prevent the formation of current paths. Secondly, it needs high radiation resistance. Ideally, it should not have any charge (whether mobile or fixed). If there is fixed charge, the less the better, while mobile charge should be avoided as much as possible. More importantly, it should not generate charge under ultraviolet radiation to avoid affecting the accuracy and stability of the device's storage performance.

[0051] Therefore, in this embodiment, the storage capacity of the phototransistor is only related to the photogenerated carriers generated in the photosensitive layer 70, and other possibilities that could generate charge and affect storage performance are avoided as much as possible. Thus, unlike traditional storage devices that utilize movable charges in the insulating dielectric layer 60 as charge carriers, the charge storage mentioned in this embodiment originates from the photosensitive layer 70 and is stored at the interface between the photosensitive layer 70 and the insulating dielectric layer 60. This storage interface is more advantageous than other technologies that require a floating gate as the storage location. Since a floating gate layer is not needed, the device structure and manufacturing process are simpler, saving costs. Furthermore, due to the reduction of additional process steps, the device is less susceptible to contamination, which is more conducive to improving device stability.

[0052] Specifically, as another embodiment of this application, the specific fabrication process of the dual-controlled phototransistor is disclosed as follows: (1) A clean silicon wafer with a certain thickness of oxide layer is subjected to photolithography-etching process to complete the patterning of the doped region and to form a substrate layer 10 with a first doped region and a second doped region. (2) P element is doped using high temperature thermal diffusion process to form first doped layer 20 and second doped layer 30; (3) Pattern the channel region and etch the intrinsic SiO2 on the substrate layer 10; (4) High-quality SiO2 is grown by thermal oxidation process to form an insulating dielectric layer 60; (5) Using photolithography-etching process, the insulating dielectric layer 60 above the first doped layer 20 and the second doped layer 30 is etched to form contact holes; (6) The source and drain electrodes are patterned by photolithography, and metal Al / Ti is prepared by magnetron sputtering. Then, the source electrode layer 40 and drain electrode layer 50 are prepared by a dissolution process. (7) A Ga2O3 layer with low oxygen defect concentration is prepared by introducing oxygen through magnetron sputtering, which is used to prepare the photosensitive layer 70. (8) The gate electrode is patterned by photolithography and metal Pt is prepared by magnetron sputtering. The gate electrode layer 80 is formed by dissolution process. (9) The photosensitive layer 70 is etched using a photolithography-etching process to expose the source electrode layer 40 and the drain electrode layer 50 covered by the photosensitive layer 70.

[0053] The phototransistor fabricated according to the above process was tested, and the transfer characteristic curves obtained under the condition of 254nm wavelength ultraviolet light and a fixed drain voltage of 1V are shown below. Figure 2 As shown, the write and erase gate voltages are -5V and 5V, respectively, and the read (drain-source) voltage is 1V. It can be seen that under 254nm light irradiation, applying a negative gate voltage for the write operation shifts the transfer curve to the right; applying a positive gate voltage for the erase operation under 254nm light irradiation shifts the transfer curve to the left. The phototransistor has high sensitivity and realizes the signal storage function.

[0054] The stability of the phototransistor fabricated according to the above preparation process was tested, and the results are as follows: Figure 3 As shown in the figure, the gray dots are marked with "0", representing the current during erasure, and the red dots are marked with "1", representing the current during writing. The writing and erasing voltages are 5V and -5V, respectively, and the read voltage is 3V. It can be seen that during 2000 erase and write cycles, the number of captured photogenerated carriers does not change significantly, indicating that the phototransistor's signal storage function is stable.

[0055] This application also discloses an electronic device comprising a dual-controlled phototransistor as described in any of the preceding descriptions.

[0056] In summary, this application discloses a dual-controlled phototransistor, comprising a substrate layer 10, a first doped layer 20, a second doped layer 30, a source electrode layer 40, a drain electrode layer 50, an insulating dielectric layer 60, a photosensitive layer 70, and a gate electrode layer 80. The substrate layer 10 has patterned first and second doped regions spaced apart. The first doped layer 20 is disposed in the first doped region; the second doped layer 30 is disposed in the second doped region; and a channel region is formed between the first doped layer 20 and the second doped layer 30. The source electrode layer 40 is disposed on the first doped layer 20; the drain electrode layer 50 is disposed on the second doped layer 30; the insulating dielectric layer 60 is disposed in the channel region; the photosensitive layer 70 is disposed on the insulating dielectric layer 60; and the gate electrode layer 80 is disposed on the photosensitive layer 70. The photosensitive layer 70 generates photogenerated carriers under ultraviolet light irradiation. The insulating dielectric layer 60 has no charge and therefore does not interfere with the photogenerated carriers, improving the stability of photogenerated carrier aggregation. The elimination of the need for a floating gate layer simplifies the device structure, saves costs, improves device stability, and enhances the application value of phototransistors.

[0057] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0058] It should be noted that this utility model uses a dual-controlled phototransistor and electronic device as an example to introduce the specific structure and working principle of this utility model. However, the application of this utility model is not limited to dual-controlled phototransistors and electronic devices, and can also be applied to the production and use of other similar workpieces.

[0059] It should be understood that this invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this invention is limited only by the appended claims.

[0060] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A dual-controlled phototransistor, characterized in that, include: A substrate layer, wherein patterned first doped regions and second doped regions are disposed at intervals on the substrate layer; A first doped layer is disposed in the first doped region; A second doped layer is disposed in the second doped region; and a channel region is formed between the first doped layer and the second doped layer. The source electrode layer is disposed on the first doped layer; A drain electrode layer is disposed on the second doped layer; An insulating dielectric layer is disposed on the channel region; A photosensitive layer is disposed on the insulating dielectric layer; A gate electrode layer is disposed on the photosensitive layer.

2. The dual-modulation phototransistor according to claim 1, characterized in that, The photosensitive layer is a wide bandgap semiconductor layer, and the photosensitive layer includes any one of an inorganic metal oxide layer, an inorganic metal nitride layer, an inorganic non-metal nitride layer, and an organic polymer layer.

3. The dual-modulation phototransistor according to claim 2, characterized in that, The photosensitive layer is any one of gallium oxide, boron nitride, aluminum nitride, and zinc oxide.

4. The dual-modulation phototransistor according to claim 1, characterized in that, The insulating dielectric layer is any one of the following: silicon dioxide layer, aluminum oxide layer, hafnium oxide layer, aluminum nitride layer, boron nitride layer, and insulating polymer layer.

5. The dual-modulation phototransistor according to claim 1, characterized in that, The doping types of the first doped layer and the second doped layer are opposite to those of the substrate layer.

6. The dual-modulation phototransistor according to claim 1, characterized in that, The substrate is a P-type silicon wafer or an N-type silicon wafer.

7. The dual-modulation phototransistor according to claim 1, characterized in that, The source electrode layer is any one of indium tin oxide, molybdenum alloy, titanium alloy, copper alloy, chromium alloy, gold, nickel alloy, aluminum alloy, and graphene; and / or, the drain electrode layer is any one of indium tin oxide, molybdenum alloy, titanium alloy, copper alloy, chromium alloy, gold, nickel alloy, aluminum alloy, and graphene.

8. The dual-modulation phototransistor according to claim 1, characterized in that, The gate electrode layer is any one of a platinum electrode layer, a gold electrode layer, or a palladium electrode layer.

9. An electronic device, characterized in that, Including the dual-controlled phototransistor as described in any one of claims 1 to 8.

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