Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a plurality of photosensitive pixels, an interconnect structure, a memory region, and an image signal processor. The plurality of photosensitive pixels are located in the substrate. The interconnect structure is on a first side of the substrate. The memory region includes a plurality of memory cells disposed in the interconnect structure, wherein the plurality of photosensitive pixels are coupled to the plurality of memory cells through the interconnect structure. The image signal processor is coupled to the plurality of memory cells via the interconnect structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Utility Model Content

[0004] According to some embodiments disclosed herein, a semiconductor structure includes a substrate, a plurality of photosensitive pixels, an interconnect structure, a memory region, and an image signal processor. The plurality of photosensitive pixels are located in the substrate. The interconnect structure is located on a first side of the substrate. The memory region includes a plurality of memory cells disposed in the interconnect structure, wherein the plurality of photosensitive pixels are coupled to the plurality of memory cells via the interconnect structure. The image signal processor is coupled to the plurality of memory cells via the interconnect structure.

[0005] According to some embodiments disclosed herein, the semiconductor structure includes a substrate, a plurality of photosensitive pixels, memory cell transistors, an image signal processor, and an interconnect structure having a plurality of conductive lines and a plurality of conductive vias. The plurality of photosensitive pixels are disposed in the substrate. The memory cell transistors are disposed on the substrate. The image signal processor is disposed on the substrate. The interconnect structure is disposed on the substrate. The interconnect structure includes a plurality of memory cells, wherein the interconnect structure couples the plurality of photosensitive pixels to the plurality of memory cells via the memory cell transistors. The image signal processor is coupled to the plurality of memory cells.

[0006] According to some embodiments disclosed herein, a semiconductor structure includes a plurality of photosensitive pixels, an interconnect structure, a memory region, and an image signal processor. The plurality of photosensitive pixels include a plurality of pixel transistors and a photosensitive detection area. The interconnect structure is located above the photosensitive detection area. The memory region includes memory transistors disposed on a substrate and a plurality of memory cells disposed in the interconnect structure, wherein the interconnect structure couples the plurality of photosensitive pixels to the plurality of memory cells via the memory transistors. The image signal processor is coupled to the plurality of memory cells. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying items. Figure 1The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A schematic cross-sectional view depicting an instance portion of an instance CIS system having memory units and providing neuromorphic computing capabilities according to some embodiments.

[0009] Figure 2A A plan view or layout diagram of an example CMOS image sensor according to some embodiments;

[0010] Figure 2B The illustration shows the photosensitive detection area along some embodiments of a CMOS image sensor. Figure 2A Cross-sectional view of the cutting line L-L' in the photosensitive detection area;

[0011] Figure 2C This is a schematic diagram depicting a plurality of pixel transistors according to some embodiments;

[0012] Figure 3 This is a schematic cross-sectional view of a portion of an instance memory cell region according to some embodiments;

[0013] Figure 4A Depicts an example of a vertically serial memory array according to some embodiments;

[0014] Figure 4B Depicts an instance of a horizontally serialized memory array according to some embodiments;

[0015] Figure 4C Depicts examples of vertical and horizontal serial memory arrays according to some embodiments;

[0016] Figure 4D Depicts an instance of a horizontally serialized memory array according to some embodiments;

[0017] Figure 5A A schematic cross-sectional view depicting an example portion of another instance CIS system providing memory units and neuromorphic computing capabilities according to some embodiments;

[0018] Figure 5B A schematic cross-sectional view depicting an example portion of another instance CIS system providing memory units and neuromorphic computing capabilities according to some embodiments;

[0019] Figures 6 to 8A schematic cross-sectional view depicting an example substrate having (a plurality of) memory cell transistors on a substrate, a first interconnect structure having a first memory array on the substrate, and a second interconnect structure having a second memory array below the substrate, according to some embodiments.

[0020] Figure 9 The illustrations depict examples of artificial perception applications of CIS systems that provide memory units and neuromorphic computing capabilities according to some embodiments.

[0021] Figure 10 Block diagrams depicting example applications of a CIS system that provides memory units and neuromorphic computing capabilities according to some embodiments.

[0022] Figure 11 A flowchart depicting an example method for manufacturing a CIS system with neuromorphic computing capabilities according to some embodiments;

[0023] Figures 12 to 19 The illustration depicts an example substrate having (a plurality of) memory cell transistors on a substrate, a first interconnect structure having a first memory array on the substrate, and a second interconnect structure having a second memory array below the substrate, according to some embodiments.

[0024] [Symbol Explanation]

[0025] 100: CIS System

[0026] 102: Semiconductor substrate

[0027] 104: Photosensitive pixel area

[0028] 106: Memory cell area

[0029] 108: ISP Zone

[0030] 110: Memory cell area, interconnect structure

[0031] 112: Pixel transistor

[0032] 120: CMOS image sensor

[0033] 122: Photosensitive detection area

[0034] 122U: Unit photosensitive detection area

[0035] 124: Optical isolation zone

[0036] 125: Photodiode layer

[0037] 126: Physically isolated area

[0038] 127: First side

[0039] 128: Pad Electrode

[0040] 129: Second side

[0041] 130: BLC area

[0042] 131: Color Filter

[0043] 132: Microlens

[0044] 134: Pad Dielectric Layer

[0045] 136: First isolation structure

[0046] 138: Second isolation structure

[0047] 140: Dielectric materials

[0048] 141: Third isolation structure

[0049] 142: Path Transistor

[0050] 144: Reset transistor

[0051] 146: Source Follower Transistor

[0052] 148: Select Transistor

[0053] 302: Interconnection Structure

[0054] 303:Substrate

[0055] 304: Memory Unit

[0056] 306: Interconnecting metal wire

[0057] 308:VIA

[0058] 310: First source / drain region

[0059] 312: Second source / drain region

[0060] 314: Bottom electrode

[0061] 316: Gate dielectric layer

[0062] 318: Metal gate layer

[0063] 320: Data Storage Structure

[0064] 322: Top electrode

[0065] 400: Vertical Serial Memory Array

[0066] 401: Direction

[0067] 402: First electrode layer

[0068] 404: First data storage structure

[0069] 406: Second electrode layer

[0070] 408: Second Data Storage Structure

[0071] 410: Third electrode layer

[0072] 412: Third Data Storage Structure

[0073] 414: Fourth electrode layer

[0074] 416: First memory unit

[0075] 418: Second Memory Unit

[0076] 420: Third memory unit

[0077] 430: Horizontal Serial Memory Array

[0078] 431: Direction

[0079] 432: First electrode

[0080] 434: First Data Storage Structure

[0081] 436: Second electrode

[0082] 438: Second Data Storage Structure

[0083] 440: Third electrode

[0084] 442: Third Data Storage Structure

[0085] 444: Fourth electrode

[0086] 446: Fourth Data Storage Structure

[0087] 448: Fifth Electrode

[0088] 450: First memory unit

[0089] 452: Second memory unit

[0090] 454: Third memory unit

[0091] 456: Fourth memory unit

[0092] 457~459: Direction

[0093] 460: Vertical and Horizontal Serial Memory Array

[0094] 461: Vertical and Horizontal Serial Memory Arrays

[0095] 462: First electrode

[0096] 463: First electrode

[0097] 464: First data storage structure

[0098] 465: First Data Storage Structure

[0099] 466: Second electrode

[0100] 467: Second electrode

[0101] 468: Second Data Storage Structure

[0102] 469: Third electrode

[0103] 470: Third electrode

[0104] 471: Second Data Storage Structure

[0105] 472: Third Data Storage Structure

[0106] 473: Fourth electrode

[0107] 474: Fourth electrode

[0108] 475: Third Data Storage Structure

[0109] 476: Fourth Data Storage Structure

[0110] 477: Fifth Electrode

[0111] 478: Fifth Electrode

[0112] 479: Sixth electrode

[0113] 480: Fifth Data Storage Structure

[0114] 481: Fourth Data Storage Structure

[0115] 482: Sixth electrode

[0116] 483: Seventh Electrode

[0117] 484: Sixth Data Storage Structure

[0118] 485: First Memory Unit

[0119] 486: Seventh Electrode

[0120] 487: Second Memory Unit

[0121] 488: First Memory Unit

[0122] 489: Third Memory Unit

[0123] 490: Second memory unit

[0124] 491: Fourth memory unit

[0125] 492: Third memory unit

[0126] 494: Fourth memory unit

[0127] 496: Fifth memory unit

[0128] 498: Sixth Memory Unit

[0129] 500: CIS System

[0130] 502: First Semiconductor Wafer

[0131] 503:Substrate

[0132] 504: Second semiconductor wafer

[0133] 505:Substrate

[0134] 506: First interconnect structure

[0135] 508: Second Interconnect Structure

[0136] 520: CIS System

[0137] 522: First Semiconductor Wafer

[0138] 524: Second semiconductor wafer

[0139] 526: Third Semiconductor Wafer

[0140] 528:Substrate

[0141] 530: First interconnect structure

[0142] 532: Second Interconnect Structure

[0143] 534:Substrate

[0144] 536:Substrate

[0145] 538: Third Interconnect Structure

[0146] 540:TSV

[0147] 602:Substrate

[0148] 604: Memory Cell Transistor

[0149] 606: First interconnect structure

[0150] 608: Second interconnect structure

[0151] 610: First Memory Array

[0152] 612: Second Memory Array

[0153] 702:Substrate

[0154] 704: Memory Cell Transistor

[0155] 706: First interconnect structure

[0156] 708: Second interconnect structure

[0157] 710: First Memory Array

[0158] 712: Second Memory Array

[0159] 802:Substrate

[0160] 804: Memory Cell Transistor

[0161] 806: First interconnect structure

[0162] 808: Second Interconnect Structure

[0163] 810: First Memory Array

[0164] 812: Second Memory Array

[0165] 902: Memory Unit

[0166] 904: Weight

[0167] 906: Output

[0168] 908: Summation Output

[0169] 1000: CIS System

[0170] 1002: pixels

[0171] 1003: Column Scanner

[0172] 1004: Memory Unit

[0173] 1006: Summation Amplifier

[0174] 1007: Output of Neuromorphic Computation

[0175] 1008: Comparator

[0176] 1009: Ramp signal

[0177] 1010: Ramp Generator

[0178] 1011: Comparison Signal

[0179] 1012: Counter

[0180] 1013: Count value

[0181] 1014: Memory Device

[0182] 1100: Method

[0183] 1110~1146: Square

[0184] 1202:Substrate

[0185] 1204: Memory Cell Transistor

[0186] 1206: First interconnect structure

[0187] 1208: Second Interconnect Structure

[0188] 1210: First Memory Array

[0189] 1212: Second Memory Array

[0190] 1302:Substrate

[0191] 1304: Memory Cell Transistor

[0192] 1306: First interconnect structure

[0193] 1308: Second Interconnect Structure

[0194] 1310: First Memory Array

[0195] 1312: Second Memory Array

[0196] 1402:Substrate

[0197] 1404: Memory Cell Transistor

[0198] 1406: First interconnect structure

[0199] 1408: Second Interconnect Structure

[0200] 1410: First Memory Array

[0201] 1412: Second Memory Array

[0202] 1502:Substrate

[0203] 1504: Memory Cell Transistor

[0204] 1506: First interconnect structure

[0205] 1508: Second Interconnect Structure

[0206] 1510: First Memory Array

[0207] 1512: Second Memory Array

[0208] 1602:Substrate

[0209] 1604: Memory Cell Transistor

[0210] 1606: First interconnect structure

[0211] 1608: Second Interconnect Structure

[0212] 1610: First Memory Array

[0213] 1612: Second Memory Array

[0214] 1702:Substrate

[0215] 1704: Memory Cell Transistor

[0216] 1706: First interconnect structure

[0217] 1708: Second Interconnect Structure

[0218] 1710: First Memory Array

[0219] 1712: Second Memory Array

[0220] 1802:Substrate

[0221] 1804: Memory Cell Transistor

[0222] 1806: First interconnect structure

[0223] 1808: Second Interconnect Structure

[0224] 1810: First Memory Array

[0225] 1812: Second Memory Array

[0226] 1902:Substrate

[0227] 1904: Memory Unit Transistor

[0228] 1906: First Interconnection Structure

[0229] 1908: Second Interconnect Structure

[0230] 1910: First Memory Array

[0231] 1912: Second Memory Array Detailed Implementation

[0232] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting.

[0233] For simplicity, this document may not describe in detail the known techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionality not described in detail herein. Specifically, the various processes in the manufacture of semiconductor devices are well known; therefore, for simplicity, many known processes will be mentioned only briefly herein, or omitted entirely without providing well-known process details. Upon a full reading of this disclosure, those skilled in the art will readily understand that the structures disclosed herein can be used with a variety of techniques and incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the illustrations may represent multiple components.

[0234] Furthermore, for ease of description, spatial relative terms such as “above,” “overlapping,” “on top,” “upper,” “top,” “below,” “under,” “below,” “lower,” “bottom,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. When using spatial relative terms such as those listed above to describe a first element relative to a second element, the first element may be directly on the other element, or there may be intermediate elements or layers present.

[0235] Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate any relationship between the various embodiments and / or configurations discussed.

[0236] It should be noted that references to "an embodiment," "an example embodiment," "exemplary embodiment," "illustrative," "example," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment does not necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will be able to influence such feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not).

[0237] It should be understood that the phrases or terms used herein are for descriptive purposes only and not for limitation, and therefore the terms or phrases used herein should be interpreted by those skilled in the art based on the teachings herein.

[0238] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Throughout the specification, unless otherwise indicated, the same reference numerals in the different figures refer to the same or similar components formed using the same or similar materials(s) by the same or similar methods.

[0239] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or portions, which should not be limited by these terms. These terms may be used only to distinguish one element, component, area, layer, or portion from another. Unless the context clearly indicates otherwise, the terms such as “first,” “second,” and “third” used herein do not imply any order or sequence.

[0240] As used herein, the terms “approximately,” “substantially,” “substantially,” and “about” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms can refer to the exact occurrence of the event or situation, or the situation being close to its occurrence. For example, when used in conjunction with a numerical value, these terms can refer to a range of variation less than or equal to ±10% of that value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the two values ​​can be considered “substantially” the same or equal. For example, "substantially" parallel can mean an angle variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "substantially" perpendicular can mean an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0241] Semiconductor image sensors are used to sense incident visible or invisible radiation, such as visible light and infrared light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications, such as digital cameras, mobile phones, tablet computers, and goggles. These image sensors utilize an array of pixels that absorb (e.g., sense) incident radiation and convert it into an electrical signal. An example of an image sensor is a backside-illuminated (BSI) image sensor, which detects radiation from the "backside" of the substrate of the BSI image sensor.

[0242] A backside illuminated (BSI) image sensor is a type of CIS device. A BSI image sensor includes a pixel region having an array of pixels or radiation sensing regions formed on a substrate (e.g., a semiconductor substrate). In this disclosure, the terms "radiation sensing region" and "pixel" are used interchangeably. Pixels are used to convert photons from incident radiation into electrical signals. The electrical signals are then distributed to processing components attached to the BSI image sensor. For this purpose, the pixel region is covered with interconnect structures in a multi-level metallization layer, which are used to distribute the electrical signals generated within the pixel to the appropriate processing components. The multi-level metallization layer is formed on a first surface of the substrate (referred to as the "front" surface of the substrate). The pixel region is formed on a second surface of the substrate opposite the front surface of the substrate. This second surface of the substrate is referred to herein as the "rear" surface of the substrate. The pixel region includes a mesh structure providing optical isolation between adjacent pixels. Further, the pixel region includes a color filter layer. The material of the color filter layer can be selected such that light with a desired wavelength passes through the color filter layer, while light with other wavelengths is absorbed by the color filter layer.

[0243] This document describes systems, methods, techniques, and articles that can provide high-speed image computing using CIS circuits. The described systems, methods, techniques, and articles enable high-speed image computing using CIS circuits that provide neuromorphic computing capabilities. The described systems, methods, techniques, and articles can provide neuromorphic computing at the front side of the wafer, the back side of the wafer, or both the front and back sides of the wafer. The described systems, methods, techniques, and articles can provide neuromorphic computing by integrating horizontal and / or vertical serial memory cells into the CIS circuit. The described systems, methods, techniques, and articles can provide multiple memory cells for the CIS circuit, which can be programmed using quantized weights in image-sensing neurons. The described systems, methods, techniques, and articles can provide CIS circuits with horizontal and / or vertical serial MRAM and / or RRAM memory cells and neuromorphic computing capabilities, providing high-speed image processing and efficient power consumption.

[0244] Figure 1A schematic cross-sectional view depicting a portion of an example CIS system 100 having memory cells and providing neuromorphic computing capabilities according to some embodiments is shown. The example CIS system 100 includes a semiconductor substrate 102 having a photosensitive pixel region 104 containing a plurality of photosensitive pixels, a memory cell region 106, and an image signal processor region (ISP region 108) disposed on the semiconductor substrate 102. The example CIS system 100 also includes an interconnect structure 110 with a multi-level metallization layer embedded in an ILD layer of the multi-level metallization layer, disposed above the semiconductor substrate 102, interconnecting components (e.g., transistors) of the photosensitive pixel region 104, the memory cell region 106, and the ISP region 108 to form a CIS system with neuromorphic computing capabilities.

[0245] Interconnect structure 110 provides routing and electrical connections between device elements formed in and / or above the substrate. Interconnect structure 110 may include one or more conductive features, in this example including metal lines and / or vias (VIAs) formed in a multi-level metallization layer. The conductive features can be electrically connected to active and / or passive devices on the substrate via contacts (not shown). In some embodiments, the interconnect structure may be formed using single and / or dual damascene processes, VIA-preferred processes, or metal-preferred processes.

[0246] Semiconductor substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a semiconductor wafer, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0247] The photosensitive pixel area 104 illustrates one of the multiple photosensitive pixel areas in the CIS system 100, which is part of a larger CMOS image sensor and includes multiple pixel transistors 112 and a photosensitive detection area 122. Figure 2AA plan view or layout diagram of an example CMOS image sensor 120 according to some embodiments is depicted. The example CMOS image sensor 120 includes a photosensitive detection region 122 (in which a plurality of unit photosensitive detection regions are arranged in a matrix) and an optical isolation region 124 surrounding the photosensitive detection region 122. Further, the optical isolation region 124 is surrounded by a physical isolation region 126. In some embodiments, the CMOS image sensor 120 includes a plurality of pad electrodes 128 for wiring to an external circuit system. The example CMOS image sensor 120 further includes one or more black level calibration (BLC) regions 130 that block incident light and provide a reference dark voltage current.

[0248] Figure 2B The illustration shows the photosensitive detection area 122 of a CMOS image sensor 120 according to some embodiments. Figure 2A A cross-sectional view of the cut line L-L' in the photosensitive detection region 122. The photosensitive detection region 122 includes a plurality of unit photosensitive detection regions 122U, each of which includes a photodiode layer 125 formed in a semiconductor substrate 102 (having a first side 127 and an opposite second side 129), a color filter 131 disposed above the second side 129 and substantially aligned with the photodiode layer 125, and a microlens 132 disposed above and aligned with the color filter 131. In some embodiments, a pad dielectric layer 134 is disposed between the color filter 131 and the microlens 132. The CMOS image sensor 120 also includes a first isolation structure 136 for laterally separating adjacent color filters 131. Example CMOS image sensor 120 includes a second isolation structure 138, which is a deep trench isolation structure filled with one or more dielectric materials 140, disposed in the semiconductor substrate 102 to laterally separate adjacent photodiode layers 125. Furthermore, the CMOS image sensor 120 includes a pass transistor 142 coupled to a photodiode layer 125 disposed on a first side 127 of the semiconductor substrate 102. In some embodiments, a third isolation structure 141 (which is a doped region implanted with, for example, boron) is disposed between and aligned with the second isolation structure 138 and the first side 127, and serves as an electrical isolation structure. In some embodiments, each unit photosensitive detection area 122U has a square or rectangular shape in a plan view and is surrounded by the first isolation structure 136, the second isolation structure 138, and the third isolation structure 141.

[0249] The unit photosensitive detection area 122U also includes floating diffusion (FD) regions coupled to multiple pixel transistors (not shown). Figure 2CThis is a schematic diagram depicting a plurality of pixel transistors 112 according to some embodiments. The plurality of pixel transistors 112 includes a pass transistor 142, a reset transistor 144, a source follower transistor 146, and a select transistor 148.

[0250] During operation of the photosensitive pixel region 104, charge accumulates in response to incident radiation. A pass transistor 142 selectively transfers the accumulated charge at the photodiode layer 125 of the photosensitive detection region 122 to the floating diffused region (FD). The pass transistor 142 is gated by a pass signal TX and includes a pair of first source / drain regions. One of the first source / drain regions is formed by the floating diffused region (FD), while the other is formed by a doped region of the photosensitive pixel region 104. Depending on the context, the source / drain regions may be referred to individually or collectively as the source or drain. A reset transistor 144 is gated by a reset signal RST and electrically coupled from the floating diffused region to an applied reset voltage V. rst The terminal. The reset transistor 144 is used to electrically couple the floating diffuse node FD to the reset voltage V. rst To reset the floating diffused FD region to the reset voltage V rst The source follower transistor 146 is gated by the charge at the floating diffused region (FD), and the select transistor 148 is gated by the select signal SEL. Further, the source follower transistor 146 and the select transistor 148 are connected in series from the terminal to which the power supply voltage VDD is applied to the output terminal OUT. The source follower transistor 146 is used to buffer and amplify the voltage at the floating diffused region (FD). The select transistor 148 is used to selectively transfer the buffered and amplified voltage from the source follower transistor 146 to the output terminal OUT.

[0251] Figure 3 This is a schematic cross-sectional view of a portion of an instance memory cell region 106. The instance memory cell region 106 includes an interconnect structure 302 disposed above a substrate 303 and memory cells 304 disposed within the interconnect structure 302. The interconnect structure 302 includes multiple stacked interconnect metal layers, including interconnect metal lines 306 and VIAs 308 disposed within the ILD layers. The instance memory cell region 106 further includes memory cell transistors formed in the substrate 303. The memory cell transistors include a first source / drain region 310 coupled to a select line SL via interconnect metal lines 306 and VIAs 308, and a second source / drain region 312 coupled to a bottom electrode 314 of the memory cell 304 via interconnect metal lines 306 and VIAs 308. The memory cell transistors further include a gate dielectric layer 316 formed above the substrate 303 and a metal gate layer 318 formed above the gate dielectric layer 316. The metal gate layer 318 is coupled to the word line WL via interconnect metal lines 306 and VIA 308.

[0252] The conductive material used for the metal wires and / or VIAs can be formed from conductive materials such as copper (Cu), aluminum (Al), tungsten (W), nickel, cobalt, silver, combinations thereof, or other suitable materials, and can be formed using electrochemical plating processes, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), similar processes, or combinations thereof. After the conductive material is formed, a planarization process, such as chemical mechanical polishing (CMP), can be used to remove excess conductive material. The interconnect structure may include one or more metal layers and one or more intermetallic dielectric (IMD) layers.

[0253] Memory cell 304 may include a bottom electrode 314, a data storage structure 320 disposed above the bottom electrode 314, and a top electrode 322 disposed above the data storage structure 320. The top electrode 322 may be coupled to bit line BL via interconnect metal lines 306 and VIA 308. In some embodiments, the bottom electrode 314 and the top electrode 322 may comprise titanium (Ti), tantalum (Ta), hafnium (Hf), tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), platinum (Pt), gold (Au), silver (Ag), copper (Cu), zirconium (Zr), aluminum (Al), lead (Pb), tungsten (W), iridium (Ir), cobalt (Co), zinc (Zn), molybdenum (Mo), gallium (Ga), germanium (Ge), palladium (Pd), indium tin oxide (ITO), indium zinc oxide (IZO), or other suitable materials. The bottom electrode and the top electrode may be formed of a monolayer film, a composite film, or a doped film.

[0254] In some embodiments, the data storage structure 320 is a magnetic tunnel junction (MTJ) or a spin valve. In such cases, the memory cell 304 is referred to as a magnetic memory cell, and the memory cell region 106 formed by an array of such memory cells 304 is referred to as a magnetoresistive random access memory (MRAM) device.

[0255] In some alternative embodiments, the data storage structure 320 includes a material with variable resistance to undergo a reversible phase change between a high-resistance state and a low-resistance state. In various embodiments, high-k dielectric materials such as titanium oxide (TiO), tantalum oxide (TaO), hafnium (HfO), titanium oxynitride (TiON), tantalum oxynitride (TaON), ruthenium (RuO), silicon oxide (SiO), silver oxide (AgO), copper oxide (CuO), zirconium oxide (ZrO), tungsten oxide (WO), iridium oxide (IrO), cobalt oxide (CoO), zinc oxide (ZnO), molybdenum oxide (MoO), palladium oxide (PdO), indium oxide (InO), gallium oxide (GaO), lead oxide (PbO), aluminum oxide (AlO), stannous oxide (SnO), germanium oxide (GeO), boron monoxide (BO), BNO, and other suitable compounds can be used. In various embodiments, other semiconductor materials may be used, such as nickel oxide (NiO), strontium titanate (Sr(Zr)TiO3), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), or the like.

[0256] In this case, memory cell 304 is referred to as a resistive memory cell, and memory cell region 106 formed by an array of such memory cells 304 is referred to as a resistive random access memory (ReRAM / RRAM) device. Depending on the voltage applied to the electrodes, data storage structure 320 will undergo a reversible change between a high-resistance state associated with a first data state (e.g., "0" or "RESET") and a low-resistance state associated with a second data state (e.g., "1" or "SET"). Once the resistance state is set, the RRAM cell will remain in the resistive state until another voltage is applied to cause a RESET operation (resulting in a high-resistance state) or a SET operation (resulting in a low-resistance state).

[0257] In some further embodiments, the data storage structure 320 comprises a phase-changing material, such as Ge2Sb2Te5, and the memory cell region 106 made of an array of such data storage structures 320 is referred to as a PCRAM device. Other suitable types of structures for the data storage structure 320 and / or other types of memory cells for the memory cell 304 may be used.

[0258] Figure 4A , Figure 4B , Figure 4C ,and Figure 4D This is a schematic cross-sectional view of different instance configurations of memory cell area 106. Figure 4AAn example vertical serial memory array 400 is depicted. In the example vertical serial memory array 400, data flows serially from one memory cell to another in direction 401. The example vertical serial memory array 400 includes multiple electrode layers disposed in different metal layers and multiple data storage structures disposed between two electrode layers. In this example, the first metal layer M is illustrated. x The first electrode layer 402 at the first data storage layer S1, the first data storage structure 404 at the first data storage layer S1, and the second metal layer M x+1 The second electrode layer 406 at the second data storage layer S2, the second data storage structure 408 at the second data storage layer S2, and the third metal layer M x+2 The third electrode layer 410 at the third data storage layer S3, the third data storage structure 412 at the third data storage layer S3, and the fourth metal layer M x+3 The fourth electrode layer 414 at that location.

[0259] The example vertical serial memory array 400 includes multiple (three in this example) serial memory cells for serially transferring content from one memory cell in an interconnect hierarchy to another memory cell in a higher or lower interconnect hierarchy (e.g., a first data storage structure 404 is in a first interconnect hierarchy, a second data storage structure 408 is in a second interconnect hierarchy above the first interconnect hierarchy, and a third data storage structure 412 is in a third interconnect hierarchy above the second interconnect hierarchy). The multiple serial memory cells include a first memory cell 416, a second memory cell 418, and a third memory cell 420. The first memory cell 416 is used to serially transfer content to the second memory cell 418, and the second memory cell 418 is used to serially transfer content to the third memory cell 420.

[0260] The first memory cell 416 has a first electrode layer 402 as the bottom electrode, a first data storage structure 404 as the data storage structure of the memory cell, and a second electrode layer 406 as the top electrode of the memory cell. The second memory cell 418 has a second electrode layer 406 as the bottom electrode, a second data storage structure 408 as the data storage structure, and a third electrode layer 410 as the top electrode of the memory cell. The third memory cell 420 has a third electrode layer 410 as the bottom electrode, a third data storage structure 412 as the data storage structure, and a fourth electrode layer 414 as the top electrode of the memory cell.

[0261] Figure 4BAn example of a horizontally serial memory array 430 is depicted. In the example of the horizontally serial memory array 430, data flows serially from one memory cell to another in direction 431. The example of the horizontally serial memory array 430 includes multiple electrodes and multiple data storage structures disposed between two electrodes. In this example, the first metal layer M is illustrated. x The first electrode 432 at the first data storage layer S1, the first data storage structure 434 at the first data storage layer S1, and the second metal layer M x+1 The second electrode 436 at the first data storage layer S1, the second data storage structure 438 at the first data storage layer S1, and the first metal layer M x The third electrode 440 at the first data storage layer S1, the third data storage structure 442 at the first data storage layer S1, and the second metal layer M x+1 The fourth electrode 444 at the first data storage layer S1, the fourth data storage structure 446 at the first data storage layer S1, and the first metal layer M x The fifth electrode at location 448.

[0262] The instance-level serial memory array 430 includes multiple (four in this instance) serial memory cells used to serially transfer content from one memory cell in an interconnect hierarchy to another memory cell in the same interconnect hierarchy (e.g., first data storage structure 434, second data storage structure 438, third data storage structure 442, and fourth data storage structure 446 are in the same interconnect hierarchy). The multiple serial memory cells include a first memory cell 450, a second memory cell 452, a third memory cell 454, and a fourth memory cell 456. The first memory cell 450 serially transfers content to the second memory cell 452. The second memory cell 452 serially transfers content to the third memory cell 454. The third memory cell 454 serially transfers content to the fourth memory cell 456.

[0263] The first memory cell 450 has a first electrode 432 as a bottom electrode, a first data storage structure 434 as a data storage structure for the memory cell, and a second electrode 436 as a top electrode for the memory cell. The second memory cell 452 has a second electrode 436 as a bottom electrode, a second data storage structure 438 as a data storage structure, and a third electrode 440 as a top electrode for the memory cell. The third memory cell 454 has a third electrode 440 as a bottom electrode, a third data storage structure 442 as a data storage structure, and a fourth electrode 444 as a top electrode for the memory cell. The fourth memory cell 456 has a fourth electrode 444 as a bottom electrode, a fourth data storage structure 446 as a data storage structure, and a fifth electrode 448 as a top electrode for the memory cell.

[0264] Figure 4C An example of a vertical and horizontal serial memory array 460 is depicted. In the example of the vertical and horizontal serial memory array 460, data flows serially from one memory cell to another in direction 457. The example of the vertical and horizontal serial memory array 460 includes multiple electrodes and multiple data storage structures disposed between two electrodes. In this example, the first metal layer M is illustrated. x The first electrode 462 at the first data storage layer S1, the first data storage structure 464 at the first data storage layer S1, and the second metal layer M x+1 The second electrode 466 at the second data storage layer S2, the second data storage structure 468 at the second data storage layer S2, and the third metal layer M x+2 The third electrode 470 at the second data storage layer S2, the third data storage structure 472 at the second data storage layer S2, and the second metal layer M x+1 The fourth electrode 474 at the first data storage layer S1, the fourth data storage structure 476 at the first data storage layer S1, and the first metal layer M x The fifth electrode 478 at the first data storage layer S1, the fifth data storage structure 480 at the first data storage layer S1, and the second metal layer M x+1 The sixth electrode 482 at the first data storage layer S1, the sixth data storage structure 484 at the first data storage layer S1, and the first metal layer M x The seventh electrode at point 486.

[0265] The example vertical and horizontal serial memory array 460 includes multiple (six in this example) serial memory cells for serially transferring content from one memory cell to another. The multiple serial memory cells include a first memory cell 488, a second memory cell 490, a third memory cell 492, a fourth memory cell 494, a fifth memory cell 496, and a sixth memory cell 498. The first memory cell 488 serially transfers content to the second memory cell 490. The second memory cell 490 serially transfers content to the third memory cell 492. The third memory cell 492 serially transfers content to the fourth memory cell 494. The fourth memory cell 494 serially transfers content to the fifth memory cell 496. The fifth memory cell 496 serially transfers content to the sixth memory cell 498.

[0266] The first memory cell 488 has a first electrode 462 as a bottom electrode, a first data storage structure 464 as a data storage structure for the memory cell, and a second electrode 466 as a top electrode for the memory cell. The second memory cell 490 has a second electrode 466 as a bottom electrode, a second data storage structure 468 as a data storage structure, and a third electrode 470 as a top electrode for the memory cell. The third memory cell 492 has a third electrode 470 as a bottom electrode, a third data storage structure 472 as a data storage structure, and a fourth electrode 474 as a top electrode for the memory cell. The fourth memory cell 494 has a fourth electrode 474 as a bottom electrode, a fourth data storage structure 476 as a data storage structure, and a fifth electrode 478 as a top electrode for the memory cell. The fifth memory cell 496 has a fifth electrode 478 as a bottom electrode, a fifth data storage structure 480 as a data storage structure, and a sixth electrode 482 as a top electrode for the memory cell. The sixth memory cell 498 has a sixth electrode 482 as the bottom electrode, a sixth data storage structure 484 as the data storage structure, and a seventh electrode 486 as the top electrode of the memory cell.

[0267] Figure 4D Another example of a vertical and horizontal serial memory array 461 is depicted. In example vertical and horizontal serial memory array 461, data flows serially from one memory cell to another in direction 459. Example vertical and horizontal serial memory array 461 includes multiple electrodes and multiple data storage structures disposed between two electrodes. In this example, the first metal layer M is illustrated. x The first electrode 463 at the first data storage layer S1, the first data storage structure 465 at the first data storage layer S1, and the second metal layer M x+1 The second electrode 467 at the third metal layer, the third electrode 469 at the third metal layer, the second data storage structure 471 at the second data storage layer, the fourth electrode 473 at the fourth metal layer, the third data storage structure 475 at the second data storage layer, the fifth electrode 477 at the third metal layer, and the second electrode M at the third metal layer. x+1 The sixth electrode 479 at the first data storage layer S1, the fourth data storage structure 481 at the first data storage layer S1, and the first metal layer M x The seventh electrode at point 483.

[0268] The example vertical and horizontal serial memory array 461 includes multiple (four in this example) serial memory cells for serially transferring content from one memory cell to another. The multiple serial memory cells include a first memory cell 485, a second memory cell 487, a third memory cell 489, and a fourth memory cell 491. The first memory cell 485 serially transfers content to (multiple) intermediate memory cells (not shown), and finally to the second memory cell 487. The second memory cell 487 serially transfers content to the third memory cell 489. The third memory cell 489 serially transfers content to (multiple) intermediate memory cells (not shown), and finally to the fourth memory cell 491.

[0269] The first memory cell 485 has a first electrode 463 as a bottom electrode, a first data storage structure 465 as a data storage structure for the memory cell, and a second electrode 467 as a top electrode for the memory cell. The second memory cell 487 has a third electrode 469 as a bottom electrode, a second data storage structure 471 as a data storage structure, and a fourth electrode 473 as a top electrode for the memory cell. The third memory cell 489 has a fourth electrode 473 as a bottom electrode, a third data storage structure 475 as a data storage structure, and a fifth electrode 477 as a top electrode for the memory cell. The fourth memory cell 491 has a sixth electrode 479 as a bottom electrode, a fourth data storage structure 481 as a data storage structure, and a seventh electrode 483 as a top electrode for the memory cell.

[0270] Reference Return Figure 1 The ISP area 108 may contain an ISP that transmits the image signal captured by the CMOS image sensor 120 to a display device such as a digital TV. The ISP can also remove noise from the input image signal, deinterleave the image signal when it is interleaved, or scale the image signal. Together with the CMOS image sensor 120, the ISP area 108 defines the image quality and speed performance of a camera subsystem, such as in a mobile phone. The ISP area 108 may contain multiple multiprocessors that work with the serial memory array in the memory cell area 106. Together with the memory cell area 106, the ISP area 108 provides neuromorphic computing capabilities to the CIS system.

[0271] Figure 5AA schematic cross-sectional view depicting an example portion of another example CIS system 500 providing memory units and neuromorphic computing capabilities according to some embodiments is shown. The example CIS system 500 includes a first semiconductor wafer 502 bonded to a second semiconductor wafer 504. The first semiconductor wafer 502 and the second semiconductor wafer 504 are front-to-front bonded. The first semiconductor wafer 502 and the second semiconductor wafer 504 can be interconnected by various wafer bonding processes having various parameters. In some examples, the wafer bonding process may include direct wafer bonding (fusion bonding), anodic bonding, thermocompression bonding, adhesive bonding, eutectic bonding, and plasma-assisted bonding.

[0272] The first semiconductor wafer 502 includes a substrate 503 having a photosensitive pixel region 104, a memory cell region 106, and a first interconnect structure 506 disposed above the substrate 503. The first interconnect structure 506 interconnects components (e.g., transistors) of the photosensitive pixel region 104 and the memory cell region 106.

[0273] The second semiconductor wafer 504 includes a substrate 505 with an ISP region 108 disposed on a semiconductor substrate 102 and a second interconnect structure 508 disposed above the substrate 505. The second interconnect structure 508 interconnects the components (e.g., transistors) of the ISP region 108 with the components of the photosensitive pixel region 104 and the memory cell region 106 via a first interconnect structure 506.

[0274] Figure 5B A schematic cross-sectional view depicts an example portion of another example CIS system 520 providing memory units and neuromorphic computing capabilities according to some embodiments. The example CIS system 520 includes a first semiconductor wafer 522 coupled to a second semiconductor wafer 524 and a third semiconductor wafer 526 coupled to the second semiconductor wafer 524. The first semiconductor wafer 522 and the second semiconductor wafer 524 are front-to-front bonded, and the third semiconductor wafer 526 and the second semiconductor wafer 524 are back-to-front bonded. The first semiconductor wafer 522 and the second semiconductor wafer 524 can be coupled using various wafer bonding processes with various parameters. Similarly, the second semiconductor wafer 524 and the third semiconductor wafer 526 can be coupled using various wafer bonding processes with various parameters. In some embodiments, the wafer bonding process may include direct wafer bonding (fusion bonding), anodic bonding, thermocompression bonding, adhesive bonding, eutectic bonding, and plasma-assisted bonding.

[0275] The first semiconductor wafer 522 includes a substrate 528 having a photosensitive detection region 122 and a first interconnect structure 530 disposed above the substrate 528. The first interconnect structure 530 interconnects the photosensitive detection region 122 with the second interconnect structure 532.

[0276] The second semiconductor wafer 524 includes a substrate 534 having a memory cell region 106, a plurality of pixel transistors 112 disposed above the substrate 534, and a second interconnect structure 532 disposed above the substrate 534. The second interconnect structure 532 interconnects the components (e.g., transistors) of the memory cell region 106 with the components of the plurality of pixel transistors 112, and interconnects the photosensitive detection region 122 with the memory cell region 106 and the plurality of photosensitive detection regions 122 via a first interconnect structure 530. One or more through-silicon vias (TSVs 540) penetrate the substrate 534 of the second semiconductor wafer 524 to connect the second interconnect structure 532 to the third interconnect structure 538 of the third semiconductor wafer 526.

[0277] The third semiconductor wafer 526 includes a substrate 536 having an ISP region 108 disposed on a substrate 536, and a third interconnect structure 538 disposed above the substrate 536. The third interconnect structure 538 interconnects the components (e.g., transistors) of the ISP region 108. The third interconnect structure 538 also interconnects the components of the ISP region 108 with the components of the memory cell region 106 and the photosensitive detection region 122 via (a plurality of) TSVs 540 and a second interconnect structure 532.

[0278] In various embodiments, the memory cell region may include memory cells in an interconnect structure above a substrate containing memory cell transistors, and memory cells in an interconnect structure below a substrate containing memory cell transistors. Figure 6 , Figure 7 ,and Figure 8 It is a schematic cross-sectional view depicting various memory cell configurations, wherein the memory cell region includes memory cells in an interconnect structure on a substrate containing memory cell transistors, and memory cells in an interconnect structure below the substrate containing memory cell transistors.

[0279] Figure 6 A substrate 602 having multiple memory cell transistors 604 on a substrate, a first interconnect structure 606 above the substrate, and a second interconnect structure 608 below the substrate is depicted. The first interconnect structure 606 includes a first memory array 610, and the second interconnect structure 608 includes a second memory array 612. The multiple memory cell transistors 604 are used to provide data to each of the first memory array 610 and the second memory array 612. In this example, each of the first memory array 610 and the second memory array 612 comprises a vertically serial memory array.

[0280] Figure 7A substrate 702 having multiple memory cell transistors 704 on a substrate, a first interconnect structure 706 on the substrate, and a second interconnect structure 708 below the substrate are depicted. The first interconnect structure 706 includes a first memory array 710, and the second interconnect structure 708 includes a second memory array 712. The memory cell transistors 704 are used to provide data to each of the first memory array 710 and the second memory array 712. In this example, each of the first memory array 710 and the second memory array 712 comprises a horizontally serial memory array.

[0281] Figure 8 A substrate 802 having memory cell transistors 804 on a substrate is depicted, a first interconnect structure 806 on the substrate, and a second interconnect structure 808 below the substrate. The first interconnect structure 806 includes a first memory array 810, and the second interconnect structure 808 includes a second memory array 812. The memory cell transistors 804 are used to provide data to each of the first memory array 810 and the second memory array 812. In this example, each of the first memory array 810 and the second memory array 812 includes vertically and horizontally serial memory arrays.

[0282] exist Figures 6 to 8 In this example, the first memory array and the second memory array are of the same type. In other examples, the first memory array may be of a first type, and the second memory array may be of a second type. For instance, the first memory array may contain a vertical serial memory array, and the second memory array may contain a horizontal serial memory array (see example...). Figure 12 The first memory array may contain a horizontal serial memory array, and the second memory array may contain a vertical serial memory array (see example). Figure 13 The first memory array may include a vertical serial memory array, and the second memory array may include both vertical and horizontal serial memory arrays (see example). Figure 14 The first memory array may include vertical and serial memory arrays, and the second memory array may include a vertical serial memory array (see example). Figure 15 The first memory array may include a horizontal serial memory array, and the second memory array may include both vertical and horizontal serial memory arrays (see example). Figure 16 The first memory array may include vertical and horizontal serial memory arrays, and the second memory array may include a horizontal serial memory array (see example). Figure 17 The first memory array may include vertical and horizontal serial memory arrays, and the second memory array may include vertical serial memory arrays and horizontal serial memory arrays (see example). Figure 18The first memory array may include a vertical serial memory array and a horizontal serial memory array, and the second memory array may include both vertical and horizontal serial memory arrays (see example). Figure 19 Other combinations can also be considered.

[0283] Figure 9 This illustration depicts an example of an artificial perception application of a CIS system providing memory cells and neuromorphic computing capabilities. Multiple memory cells 902 and multiple weights 904 from a serial memory array located in a metal interconnect route are depicted. The metal interconnect route electrically connects the multiple memory cells 902 to memory cell transistors. The contents of each memory cell 902 (e.g., state x) are shown. i Multiply by the associated weight 904 (e.g., w) i From the contents of each memory cell 902 (e.g., state x) i ) and its associated weight 904 (e.g., w i The product of ) produces a series of outputs 906. Summing these series of outputs 906 produces a summed output 908, such as the artificial sensing current ∑I. i .

[0284] The serial memory array is an N-bit serial memory. The N-bit serial memory has N+1 states, including (N, 0), (N-1, 1), ..., (0, N). The serial memory array has k-bit anti-parallel states and (Nk)-bit parallel states. Each state in the serial memory array has a weight w. i , where w i = k*R_high + (Nk)*R_low. Each signal x i The y-bit of the memory array can be switched by current-induced switching. The serial memory will then become m. i = (ky)*R_high+(N-k+y)*R_low. For MRAM resistors, R... MTJ1 <R MTJ2 <R MTJ3 <…… <R MTJn Regarding RRAM resistors, R RRAM1 <R RRAM2 <R RRAM3 <…… <R RRAMn The input signal current must start from the small resistance of the MRAM / RRAM and gradually increase to the large resistance. Multi-N-bit serial memory has an artificially sensed current ∑I. i .

[0285] Figure 10This block diagram illustrates an example application of a CIS system 1000 that provides memory cells and neuromorphic computing capabilities. The example CIS system 1000 includes multiple pixels 1002 (e.g., photosensitive pixel areas 104), multiple memory cells 1004 in one or more serial memory arrays, and a summing amplifier 1006 (e.g., as part of an ISP area 108). The multiple memory cells 1004 and the summing amplifier 1006 add neuromorphic computing capabilities to the CIS system 1000. A row scanner 1003 can be used to select pixels 1002 for storage in the memory cells 1004.

[0286] The example CIS system 1000 further includes multiple comparators 1008, a ramp generator 1010, multiple counters 1012, and multiple memory devices 1014 (e.g., SRAM). Comparators 1008 receive a neuromorphic computation output 1007 and a ramp signal 1009 from the ramp generator 1010, and output a comparison signal 1011 by comparing the received neuromorphic computation output 1007 with the ramp signal 1009. Counters 1012 are coupled to comparators 1008 to receive the comparison signal 1011. Counters 1012 output a count value 1013 based on the comparison signal. The count value 1013 is then stored in the memory device 1014. In embodiments disclosed herein, counters 1012 may be hybrid counters, where lower parts (e.g., least significant bits) and upper parts (e.g., most significant bits) are counted separately, thereby improving counting speed and saving counter power consumption. In the embodiments disclosed herein, a plurality of comparators 1008, a ramp generator 1010, a plurality of counters 1012, and a plurality of memory devices 1014 may be used as analog-to-digital converters (ADCs).

[0287] Figure 11 This is a flowchart of an example method for manufacturing a CIS system with neuromorphic computing capabilities according to some embodiments. The operations depicted may be performed in a different order or not, depending on the specific application. It should be noted that method 1100 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after method 1100, and only some of these other processes may be briefly described herein.

[0288] It is understood that parts of a semiconductor device can be manufactured using typical semiconductor technology processes; therefore, only some processes are briefly described herein. Furthermore, exemplary semiconductor devices may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, and / or other logic devices, but these have been simplified for a better understanding of the concepts disclosed herein. In some embodiments, exemplary devices include multiple semiconductor devices (e.g., transistors), including interconnectable PFETs, NFETs, etc. Additionally, it should be noted that the operation of method 1100, including any descriptions given with reference to the figures, is illustrative only and is not intended to limit the scope beyond that specifically referenced in the following claims.

[0289] At block 1110, example method 1100 includes forming a plurality of photosensitive pixels in a substrate. Each photosensitive pixel may include a photosensitive detection area and a plurality of pixel transistors.

[0290] At block 1120, example method 1100 includes forming a memory cell transistor on a substrate. The memory cell transistor is used to transfer content from a photosensitive pixel to an associated memory cell.

[0291] At block 1130, example method 1100 includes forming an image signal processor (ISP) on a substrate. The ISP is used to process content from photosensitive pixels and content stored in associated memory units, and provides neuromorphic computing capabilities.

[0292] At block 1140, example method 1100 includes forming an interconnect structure having conductive lines and conductive VIAs on a substrate. The interconnect structure includes blocks 1142, 1144, and 1146.

[0293] At block 1142, example method 1100 includes forming a plurality of serial memory cells in an interconnect structure. The memory cells may include MRAM memory cells, RRAM memory cells, or other suitable memory cells. The memory cells may include vertical serial memory cells, horizontal serial memory cells, vertical and horizontal serial memory cells, and / or various combinations thereof.

[0294] At block 1144, instance method 1100 includes coupling a plurality of memory cells to memory cell transistors; at block 1146, instance method 1100 includes coupling an ISP to a plurality of memory cells, wherein the ISP is used to provide neuromorphic computing capabilities.

[0295] Figure 12A substrate 1202 having memory cell transistors 1204 on a substrate, a first interconnect structure 1206 on the substrate, and a second interconnect structure 1208 below the substrate are depicted. The first interconnect structure 1206 includes a first memory array 1210, and the second interconnect structure 1208 includes a second memory array 1212. The memory cell transistors 1204 are used to provide data to the first memory array 1210 and the second memory array 1212. In this example, the first memory array 1210 includes a vertically serial memory array, and the second memory array 1212 includes a horizontally serial memory array.

[0296] Figure 13 A substrate 1302 having memory cell transistors 1304 on a substrate, a first interconnect structure 1306 on the substrate, and a second interconnect structure 1308 below the substrate are depicted. The first interconnect structure 1306 includes a first memory array 1310, and the second interconnect structure 1308 includes a second memory array 1312. The memory cell transistors 1304 are used to provide data to the first memory array 1310 and the second memory array 1312. In this example, the first memory array 1310 includes a horizontal serial memory array, and the second memory array 1312 includes a vertical serial memory array.

[0297] Figure 14 The diagram depicts a substrate 1402 having memory cell transistors 1404 on a substrate, a first interconnect structure 1406 on the substrate, and a second interconnect structure 1408 below the substrate. The first interconnect structure 1406 includes a first memory array 1410, and the second interconnect structure 1408 includes a second memory array 1412. The memory cell transistors 1404 are used to provide data to the first memory array 1410 and the second memory array 1412. In this example, the first memory array 1410 includes a vertically serial memory array, and the second memory array 1412 includes both vertically and horizontally serial memory arrays.

[0298] Figure 15 The diagram depicts a substrate 1502 having memory cell transistors 1504 on a substrate, a first interconnect structure 1506 on the substrate, and a second interconnect structure 1508 below the substrate. The first interconnect structure 1506 includes a first memory array 1510, and the second interconnect structure 1508 includes a second memory array 1512. The memory cell transistors 1504 are used to provide data to the first memory array 1510 and the second memory array 1512. In this example, the first memory array 1510 includes vertically and horizontally serial memory arrays, and the second memory array 1512 includes a vertically serial memory array.

[0299] Figure 16The diagram depicts a substrate 1602 having memory cell transistors 1604 on a substrate, a first interconnect structure 1606 on the substrate, and a second interconnect structure 1608 below the substrate. The first interconnect structure 1606 includes a first memory array 1610, and the second interconnect structure 1608 includes a second memory array 1612. The memory cell transistors 1604 are used to provide data to the first memory array 1610 and the second memory array 1612. In this example, the first memory array 1610 includes a horizontal serial memory array, and the second memory array 1612 includes both vertical and horizontal serial memory arrays.

[0300] Figure 17 The diagram depicts a substrate 1702 having memory cell transistors 1704 on a substrate, a first interconnect structure 1706 on the substrate, and a second interconnect structure 1708 below the substrate. The first interconnect structure 1706 includes a first memory array 1710, and the second interconnect structure 1708 includes a second memory array 1712. The memory cell transistors 1704 are used to provide data to the first memory array 1710 and the second memory array 1712. In this example, the first memory array 1710 includes vertical and horizontal serial memory arrays, and the second memory array 1712 includes a horizontal serial memory array.

[0301] Figure 18 A substrate 1802 having memory cell transistors 1804 on a substrate, a first interconnect structure 1806 on the substrate, and a second interconnect structure 1808 below the substrate are depicted. The first interconnect structure 1806 includes a first memory array 1810, and the second interconnect structure 1808 includes a second memory array 1812. The memory cell transistors 1804 are used to provide data to the first memory array 1810 and the second memory array 1812. In this example, the first memory array 1810 includes vertical and horizontal serial memory arrays, and the second memory array 1812 includes both vertical and horizontal serial memory arrays.

[0302] Figure 19 A substrate 1902 having memory cell transistors 1904 on a substrate, a first interconnect structure 1906 on the substrate, and a second interconnect structure 1908 below the substrate are depicted. The first interconnect structure 1906 includes a first memory array 1910, and the second interconnect structure 1908 includes a second memory array 1912. The memory cell transistors 1904 are used to provide data to the first memory array 1910 and the second memory array 1912. In this example, the first memory array 1910 includes a vertically serial memory array and a horizontally serial memory array, and the second memory array 1912 includes both vertically and horizontally serial memory arrays.

[0303] In various embodiments, various types of semiconductor structures can be formed for CIS devices with neuromorphic capabilities. In various embodiments, CIS devices with neuromorphic capabilities may include 3DIC (three-dimensional integrated circuit) bonding, SoIC (small outline integrated circuit) bonding, InFO (integrated fan-out), CoWoS (wafer on substrate), die on die, large die on small die, and other configurations.

[0304] In the foregoing examples, the transistors shown are planar transistors, such as FETs or MOSFETs. In other examples, non-planar transistors, such as FinFET devices, GAA (gate all around) devices, 2D material devices, vertical devices, or BEOL devices, may be used.

[0305] In some embodiments, the technology described herein relates to a semiconductor structure including: a plurality of photosensitive pixels in a substrate; an interconnect structure above a first side of the substrate; a memory region including a plurality of memory cells formed in the interconnect structure, wherein the interconnect structure is used to couple the photosensitive pixels to the plurality of memory cells; and an image signal processor (ISP) coupled to the plurality of memory cells via the interconnect structure, wherein the ISP is used to provide neuromorphic computing capabilities.

[0306] In some cases, the techniques described herein relate to semiconductor structures in which multiple memory cells include magnetoresistive random access memory (MRAM) devices.

[0307] In some cases, the techniques described herein relate to semiconductor structures in which multiple memory cells include resistive random access memory (RRAM) devices.

[0308] In some cases, the techniques described herein relate to semiconductor structures in which multiple memory cells include multiple serial memory cells for serially transferring content from one memory cell to another.

[0309] In some embodiments, the technology described herein relates to a semiconductor structure in which an interconnect structure includes multiple interconnect layers and multiple memory cells include multiple vertically serial memory cells for serially transferring content from a first memory cell in a first interconnect layer of the interconnect structure to a second memory cell in a second interconnect layer of the interconnect structure above or below the first interconnect layer.

[0310] In some embodiments, the technology described herein relates to a semiconductor structure in which an interconnect structure includes multiple interconnect layers and multiple memory cells include multiple horizontally serial memory cells for serially transferring content from a first memory cell at a first level in the interconnect structure to a second memory cell at a first level in the interconnect structure.

[0311] In some embodiments, the technology described herein relates to semiconductor structures in which interconnect structures include multiple interconnect layers, and multiple memory cells include multiple horizontally serial memory cells and multiple vertically serial memory cells. The horizontally serial memory cells are used to serially transfer content from a first memory cell at a first level in the interconnect structure to a second memory cell at a first level in the interconnect structure, and the vertically serial memory cells are used to serially transfer content from a third memory cell at a second level in the interconnect structure to a fourth memory cell at a third level above or below the second level in the interconnect structure.

[0312] In some embodiments, the technology described herein relates to a semiconductor structure that further includes: a second interconnect structure located below a second side of a substrate; a second plurality of memory cells formed in the second interconnect structure, wherein the second interconnect structure is used to couple photosensitive pixels to the second plurality of memory cells; and an image signal processor (ISP) coupled to the second plurality of memory cells via the second interconnect structure to provide neuromorphic computing capabilities.

[0313] In some embodiments, the technology described herein relates to a method comprising: forming a plurality of photosensitive pixels in a substrate; forming memory cell transistors on the substrate; forming an image signal processor (ISP) on the substrate; and forming an interconnect structure having conductive lines and conductive VIAs on the substrate, wherein forming the interconnect structure comprises: forming a plurality of memory cells in the interconnect structure; coupling the plurality of memory cells to the memory cell transistors; and coupling the ISP to the plurality of memory cells, wherein the ISP is used to provide neuromorphic computing capabilities.

[0314] In some cases, the techniques described herein relate to a method in which forming a plurality of memory cells includes forming a magnetoresistive random access memory (MRAM) device.

[0315] In some cases, the techniques described herein relate to a method in which forming a plurality of memory cells includes forming a resistive random access memory (RRAM) device.

[0316] In some forms, the technique described herein relates to a method in which forming a plurality of memory cells includes forming a plurality of serial memory cells for serially transferring content from one memory cell to another.

[0317] In some forms, the technology described herein relates to a method in which forming a plurality of memory cells includes forming a plurality of vertically serialized memory cells for serially transferring content from a first memory cell in a first level of an interconnect structure to a second memory cell in a second level of the interconnect structure above or below the first level.

[0318] In some forms, the technology described herein relates to a method in which forming a plurality of memory cells includes forming a plurality of horizontally serialized memory cells for transferring content from a first memory cell in a first level of an interconnect structure to a second memory cell in a first level of the interconnect structure.

[0319] In some embodiments, the technology described herein relates to a semiconductor structure including: a plurality of photosensitive pixels, each including a plurality of pixel transistors and a photosensitive detection region; an interconnect structure above the photosensitive detection region; a memory region including memory transistors disposed on a substrate and a plurality of memory cells formed in the interconnect structure, wherein the interconnect structure is used to couple the photosensitive pixels to the plurality of memory cells via the memory transistors; and an image signal processor (ISP) coupled to the plurality of memory cells, wherein the ISP is used to provide neuromorphic computing capabilities.

[0320] In some cases, the technology described herein relates to a semiconductor structure in which: the memory region is on a first wafer; and the ISP is on a second wafer bonded to the first wafer.

[0321] In some embodiments, the technology described herein relates to a semiconductor structure in which: a second wafer includes a second interconnect structure; and the second interconnect structure is bonded to the interconnect structure.

[0322] In some embodiments, the technology described herein relates to a semiconductor structure in which: a second wafer includes a second interconnect structure; and the second interconnect structure is bonded to a side of a substrate opposite to a second side of the substrate, the interconnect structure being disposed on the second side.

[0323] In some embodiments, the technology described herein relates to a semiconductor structure that further includes: a first wafer and a second wafer; wherein a plurality of pixel transistors, photosensitive detection regions, memory transistors, and interconnect structures are disposed on the first wafer; wherein the ISP is disposed on the second wafer.

[0324] In some embodiments, the technology described herein relates to a semiconductor structure, which further includes: a first wafer, a second wafer, and a third wafer; wherein a photosensitive detection region is disposed on the first wafer; and wherein a plurality of pixel transistors, memory transistors, and interconnect structures are disposed on the second wafer; wherein the ISP is disposed on the third wafer.

[0325] In some embodiments, the technology described herein relates to a semiconductor structure in which: a plurality of photosensitive pixels are disposed on a first semiconductor wafer, a memory region includes memory transistors disposed on the first semiconductor wafer, and an ISP is disposed on a second semiconductor wafer.

[0326] In some embodiments, the technology described herein relates to a semiconductor structure in which: a photosensitive pixel includes a plurality of pixel transistors and a photosensitive detection region, the photosensitive detection region is disposed on a first semiconductor wafer, the plurality of pixel transistors are disposed on a second semiconductor wafer, a memory region includes memory transistors disposed on the second semiconductor wafer, and an ISP is disposed on a third semiconductor wafer.

[0327] In some embodiments, the technology described herein relates to a semiconductor structure including a substrate, a plurality of photosensitive pixels, an interconnect structure, a memory region, and an image signal processor. The plurality of photosensitive pixels are located in the substrate. The interconnect structure is located on a first side of the substrate. The memory region includes a plurality of memory cells disposed in the interconnect structure, wherein the plurality of photosensitive pixels are coupled to the plurality of memory cells via the interconnect structure. The image signal processor is coupled to the plurality of memory cells via the interconnect structure.

[0328] In some embodiments, the technology described herein relates to a semiconductor structure including a substrate, a plurality of photosensitive pixels, memory cell transistors, an image signal processor, and an interconnect structure having a plurality of conductive lines and a plurality of conductive vias. The plurality of photosensitive pixels are disposed in the substrate. The memory cell transistors are disposed on the substrate. The image signal processor is disposed on the substrate. The interconnect structure is disposed on the substrate. The interconnect structure includes a plurality of memory cells, wherein the interconnect structure couples the plurality of photosensitive pixels to the plurality of memory cells via the memory cell transistors. The image signal processor is coupled to the plurality of memory cells.

[0329] In some embodiments, the technology described herein relates to a semiconductor structure comprising a plurality of photosensitive pixels, an interconnect structure, a memory region, and an image signal processor. The plurality of photosensitive pixels include a plurality of pixel transistors and a photosensitive detection region. The interconnect structure is located above the photosensitive detection region. The memory region includes memory transistors disposed on a substrate and a plurality of memory cells disposed in the interconnect structure, wherein the interconnect structure couples the plurality of photosensitive pixels to the plurality of memory cells via the memory transistors. The image signal processor is coupled to the plurality of memory cells.

[0330] While at least one exemplary embodiment has been given in the foregoing detailed description of this disclosure, it should be understood that numerous variations exist. It should also be understood that one or more exemplary embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of this disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient roadmap for implementing exemplary embodiments of this disclosure. It should be understood that various changes can be made to the function and configuration of the elements described in the exemplary embodiments without departing from the scope of this disclosure as set forth in the appended claims.

Claims

1. A semiconductor structure, characterized in that, Include: Multiple photosensitive pixels are located in a substrate; An interconnect structure is located on a first side of the substrate; A memory region comprising a plurality of memory cells disposed in the interconnect structure, wherein a plurality of photosensitive pixels are coupled to the plurality of memory cells via the interconnect structure; and An image signal processor is coupled to the plurality of memory cells via the interconnect structure.

2. The semiconductor structure as described in claim 1, characterized in that, The plurality of memory units include a magnetoresistive random access memory device.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, The plurality of memory units include a resistive random access memory device.

4. A semiconductor structure, characterized in that, Include: One substrate; Multiple photosensitive pixels are disposed in this substrate; A memory cell transistor is disposed on the substrate; An image signal processor is disposed on the substrate; and An interconnect structure having multiple conductive lines and multiple conductive vias is disposed on the substrate, wherein the interconnect structure includes multiple memory cells, wherein the interconnect structure couples multiple photosensitive pixels to the multiple memory cells via the memory cell transistors, and wherein the image signal processor is coupled to the multiple memory cells.

5. A semiconductor structure, characterized in that, Include: Multiple photosensitive pixels, including multiple pixel transistors and a photosensitive detection area; An interconnect structure is located above the photosensitive detection area; A memory region includes a memory transistor disposed on a substrate and a plurality of memory cells disposed in the interconnect structure, wherein the interconnect structure couples the plurality of photosensitive pixels to the plurality of memory cells via the memory transistor; and An image signal processor is coupled to the plurality of memory units.

6. The semiconductor structure as described in claim 5, characterized in that, in: The memory region is located on a first wafer; and The image signal processor is located on a second wafer bonded to the first wafer.

7. The semiconductor structure as described in claim 6, characterized in that, in: The second wafer includes a second interconnect structure; and The second interconnect structure is joined to the interconnect structure.

8. The semiconductor structure as described in claim 6, characterized in that, in: The second wafer includes a second interconnect structure; and The second interconnect structure is joined to a side of the substrate opposite to a second side of the substrate, and the interconnect structure is disposed on the second side.

9. The semiconductor structure as described in claim 5, characterized in that, Further includes: A first wafer and a second wafer; and The plurality of pixel transistors, the photosensitive detection area, the memory transistor, and the interconnect structure are disposed on the first wafer; The image signal processor is located on the second wafer.

10. The semiconductor structure as described in claim 5, characterized in that, Further includes: A first wafer, a second wafer, and a third wafer; The photosensitive detection area is located on the first wafer; and The plurality of pixel transistors, the memory transistors, and the interconnect structure are disposed on the second wafer; The image signal processor is located on the third wafer.

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