Display device

Abstract

A display device is provided, the display device comprising: a substrate comprising a display area and a non-display area; a plurality of anode electrodes on the substrate; a pixel defining film on the plurality of anode electrodes and defining a plurality of emission areas; a light emitting stack on the pixel defining film and the plurality of anode electrodes; a cathode electrode on the light emitting stack; a plurality of sub-optical layers on the cathode electrode; and a lens on the plurality of sub-optical layers, wherein a plurality of sub-pixels comprises the plurality of anode electrodes, the plurality of emission areas, the light emitting stack, the cathode electrode, and the plurality of sub-optical layers, the plurality of sub-optical layers are offset by a greater magnitude as their distance from a center of the display area increases, and wherein a deviation in an offset distance between adjacent sub-pixels is about 0.001 µm to about 0.009 µm. The display device can improve image quality.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0123357, filed on September 10, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure relate to display devices, electronic devices, and optical devices. Background Technology

[0003] A head-mounted display (HMD) is an image display device worn on a user's head in the form of glasses or a helmet to focus an image at close range in front of the user's eyes. Head-mounted displays can enable virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays magnify and display magnified images on small display devices using multiple lenses. Therefore, display devices used in head-mounted displays need to provide high-resolution images, for example, images with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, organic light-emitting diodes on silicon (OLEDoS), as high-resolution small organic light-emitting display devices, are used in head-mounted displays. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are disposed on a semiconductor silicon wafer substrate, and complementary metal-oxide-semiconductor (CMOS) is disposed on the semiconductor silicon wafer substrate.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background of the utility model, and therefore may contain information that does not form prior art. Utility Model Content

[0006] The purpose of this invention is to provide a display device and electronic device that can improve image quality by minimizing or significantly reducing the number of stain defects.

[0007] According to some disclosed embodiments, a display device is provided, comprising: a substrate including a display area and a non-display area; a plurality of anode electrodes on the substrate; a pixel defining film on the plurality of anode electrodes and defining a plurality of emitting areas; a light-emitting stack on the pixel defining film and the plurality of anode electrodes; a cathode electrode on the light-emitting stack; a plurality of sub-optical layers on the cathode electrode; and a lens on the plurality of sub-optical layers, wherein the plurality of sub-pixels include the plurality of anode electrodes, the plurality of emitting areas, the light-emitting stack, the cathode electrode, and the plurality of sub-optical layers, the plurality of sub-optical layers being offset by a larger magnitude as their distance from the center of the display area increases, and wherein the offset distance deviation between adjacent sub-pixels is from about 0.001 μm to about 0.009 μm.

[0008] In some embodiments, the offset distance deviation between adjacent sub-pixels can be approximately 0.001 μm.

[0009] In some embodiments, the sub-optical layer may include: a color filter; and a sub-lens, on the color filter and superimposed on the color filter.

[0010] In some embodiments, the lens may be stacked with multiple sub-lenses of multiple sub-pixels.

[0011] In some embodiments, the sublens may include a microlens.

[0012] In some embodiments, the offset distance can be the distance between the center of the emission region of the sub-pixel and the center of the sub-optical layer of the sub-pixel.

[0013] In some embodiments, adjacent subpixels may be adjacent subpixels along a virtual line connecting the center of the display area to the edge of the display area.

[0014] In some embodiments, the rate of change of the main ray angle can be gradually varied based on the distance from the center of the display area to the sub-pixel.

[0015] In some embodiments, the rate of change of the main ray angle may gradually increase in proportion to the distance from the center of the display area to the sub-pixel.

[0016] In some embodiments, the lens may include a pancake lens.

[0017] According to some disclosed embodiments, an electronic device including a display device is provided. The display device includes: a substrate including a display area and a non-display area; a plurality of anode electrodes on the substrate; a pixel defining film on the plurality of anode electrodes and defining a plurality of emitting areas; a light-emitting stack on the pixel defining film and the plurality of anode electrodes; a cathode electrode on the light-emitting stack; a plurality of sub-optical layers on the cathode electrode; and a lens on the plurality of sub-optical layers. The plurality of sub-pixels include the plurality of anode electrodes, the plurality of emitting areas, the light-emitting stack, the cathode electrode, and the plurality of sub-optical layers. The plurality of sub-optical layers are offset by a larger magnitude as their distance from the center of the display area increases, and the offset distance deviation between adjacent sub-pixels is from about 0.001 μm to about 0.009 μm.

[0018] In some embodiments, the offset distance deviation between adjacent sub-pixels can be approximately 0.001 μm.

[0019] In some embodiments, the sub-optical layer may include: a color filter; and a sub-lens, on the color filter and superimposed on the color filter.

[0020] In some embodiments, the lens may be stacked with multiple sub-lenses of multiple sub-pixels.

[0021] In some embodiments, the sublens may include a microlens.

[0022] In some embodiments, the offset distance can be the distance between the center of the emission region of the sub-pixel and the center of the sub-optical layer of the sub-pixel.

[0023] In some embodiments, adjacent subpixels may be adjacent subpixels along a virtual line connecting the center of the display area to the edge of the display area.

[0024] In some embodiments, the rate of change of the main ray angle can be gradually varied based on the distance from the center of the display area to the sub-pixel.

[0025] In some embodiments, the rate of change of the main ray angle may gradually increase in proportion to the distance from the center of the display area to the sub-pixel.

[0026] In some embodiments, the lens may include a pancake lens.

[0027] According to this invention, the display device includes a sub-optical layer that shifts more significantly with increasing distance from the center of the display area, such that the rate of change of the main ray angle can gradually increase proportionally to the distance from the center of the display area to the sub-pixel. Therefore, the occurrence of stains (e.g., barcode stains) at the edges of the display panel can be further minimized or significantly reduced, thereby improving the image quality of the display device. Attached Figure Description

[0028] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an exploded perspective view illustrating a display device according to some embodiments of the present disclosure; Figure 2 This is a block diagram illustrating a display device according to some embodiments of the present disclosure; Figure 3 This is an equivalent circuit diagram of the first sub-pixel according to some embodiments of the present disclosure; Figure 4 This is a layout diagram illustrating a display panel according to some embodiments of the present disclosure; Figure 5 This illustrates some embodiments according to the present disclosure. Figure 4 Layout diagram of the display area; Figure 6 This illustrates some other embodiments according to the present disclosure. Figure 4 Layout diagram of the display area; Figure 7 This illustrates some embodiments according to this disclosure. Figure 5 A cross-sectional view of the display panel taken by line I1-I1'; Figure 8 This is a cross-sectional view of a display device according to some embodiments of the present disclosure; Figure 9 This is a diagram illustrating the effect of a display device according to some embodiments of the present disclosure; Figure 10 This is a perspective view illustrating a head-mounted display according to some embodiments of the present disclosure; Figure 11 This illustrates some embodiments according to the present disclosure. Figure 10 Exploded perspective view of a head-mounted display; Figure 12 This is a perspective view illustrating a head-mounted display according to some embodiments of the present disclosure; Figure 13 This is a block diagram of an electronic device according to some embodiments of the present disclosure; and Figure 14 , Figure 15 and Figure 16 This is a schematic diagram of an electronic device according to some embodiments of the present disclosure. Detailed Implementation

[0029] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, wherein the same reference numerals throughout refer to the same elements. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques that are not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure are not described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore redundant descriptions are not repeated.

[0030] When specific embodiments can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0031] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and “above” may be used herein to describe the relationship of one element or feature as shown in the drawings to another element or feature. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “below” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0032] In the accompanying drawings, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system, but can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0033] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first region, first layer, or first part discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0034] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be one or more intermediary elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, the layer, region, or element may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to the other layer, region, or element, with one or more intermediary layers, regions, or elements between them. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intermediary elements or layers.

[0035] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When a statement such as “at least one of…” follows a list of elements, it modifies the entire list of elements without modifying any individual elements within the list. For example, the expressions “at least one of a, b and c” and “at least one of the group consisting of a, b and c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0036] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to account for inherent biases in measurements or calculations that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the term “use,” and variations thereof, may be considered synonymous with the term “utilize,” and variations thereof, respectively.

[0037] The electronic devices or electronic components and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, a tape-on-a-carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory that can be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that, without departing from the spirit and scope of the exemplary embodiments of the present disclosure, the functionality of various computing devices can be combined or integrated into a single computing device, or the functionality of a particular computing device can be distributed across one or more other computing devices.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense, unless so expressly defined herein.

[0039] Figure 1 This is an exploded perspective view illustrating a display device according to some embodiments of the present disclosure. Figure 2 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0040] Reference Figure 1 and Figure 2According to some embodiments, the display device 10 is a device for displaying moving or still images. According to some embodiments, the display device 10 can be applied to portable electronic devices, such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, according to some embodiments, the display device 10 can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. For example, according to some embodiments, the display device 10 can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for implementing virtual and augmented reality.

[0041] The display device 10 according to some embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, a power supply circuit 500, and a first lens 777.

[0042] The display panel 100 may have a planar shape (e.g., a quadrilateral shape or a similar shape). For example, the display panel 100 may have a planar shape similar to a quadrilateral shape, which has a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or a rounded corner with curvature (e.g., a preset or predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape other than a quadrilateral shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0043] Display panel 100 includes multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. Display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images. For example, the substrate of display panel 100 (e.g., Figure 7 The semiconductor substrate (SSUB) may include the display area DAA and the non-display area NDA.

[0044] Multiple pixels (PX) can be set in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix (e.g., a grid) along the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1) and can be arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and can be arranged along the first direction (DR1).

[0045] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL can include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0046] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 can include, for example... Figure 3 The multiple pixel transistors shown can be formed and disposed on a semiconductor substrate SSUB using semiconductor processes (see example). Figure 7 For example, multiple pixel transistors can be formed of complementary metal-oxide-semiconductor (CMOS), but this disclosure is not limited thereto.

[0047] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and a data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0048] The scan driver 610, transmit driver 620, and data driver 700 can be located in the non-display area NDA.

[0049] The scan driver 610 may include multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB (see example) using semiconductor processes. Figure 7 For example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS, but this disclosure is not limited thereto.

[0050] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0051] The transmit driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 may generate a first transmit control signal based on the transmit timing control signal ECS and output them sequentially to a first transmit control line ECL1. The second transmit control driver 622 may generate a second transmit control signal based on the transmit timing control signal ECS and output them sequentially to a second transmit control line ECL2.

[0052] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (see example) using semiconductor processes. Figure 7 For example, multiple data transistors can be formed using CMOS, but this disclosure is not limited thereto.

[0053] Data driver 700 can receive digital video data DATA and data timing control signal DCS from timing control circuit 400. Data driver 700 can convert digital video data DATA into analog data voltage according to (e.g., based on) data timing control signal DCS, and can output analog data voltage to data line DL. For example, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of scan driver 610, and data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0054] The heat dissipation layer 200 may be stacked on the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on its rear surface. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite or a metal layer with high thermal conductivity (such as silver (Ag), copper (Cu), or aluminum (Al)).

[0055] Circuit board 300 can be electrically connected to the first pad (or "soldering pad") portion of display panel 100 PDA1 (see example) using conductive adhesive components (such as anisotropic conductive film). Figure 4 Multiple first pads PD1 (see example) Figure 4 Circuit board 300 can be a flexible printed circuit board or a flexible film made of flexible material. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. For example, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be attached to the first pad portion PDA1 of the display panel 100 (see example) using conductive adhesive members. Figure 4 Multiple first pads PD1 (see example) Figure 4 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0056] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0057] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0058] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. For example, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0059] For example, similar to scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 can be disposed in the non-display area NDA of display panel 100. For example, timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors can be formed on a semiconductor substrate SSUB (see example) using semiconductor processes. Figure 7 On the data driver 700. For example, multiple sequential transistors and multiple power transistors can be formed by CMOS, but this disclosure is not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be arranged in the data driver 700 and the first pad portion PDA1 (see example). Figure 4 )between.

[0060] The first lens 777 may be disposed on the display panel 100. For example, the first lens 777 may be disposed on the display panel 100 to be superimposed on the display area DAA of the display panel 100. The first lens 777 may be superimposed on the entire display area DAA. For example, in a plan view, the first lens 777 may surround the edge of the display area DAA. The first lens 777 may have a hemispherical shape. The first lens 777 may include, for example, a pancake lens.

[0061] Figure 3 This is an equivalent circuit diagram of the first sub-pixel according to some embodiments of the present disclosure.

[0062] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first drive voltage line VSL, to which the first drive voltage VSS corresponding to a low potential voltage is applied; the second drive voltage VDL, to which the second drive voltage VDD corresponding to a high potential voltage is applied; and the third drive voltage VIL, to which the third drive voltage VINT corresponding to the initialization voltage is applied.

[0063] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0064] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0065] The first transistor T1 can be a driving transistor that controls the source-drain current (e.g., driving current) flowing between its source and drain electrodes according to the voltage applied to its gate electrode.

[0066] The second transistor T2 can be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by the write scan signal of the write scan line GWL, thereby connecting one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0067] The third transistor T3 can be positioned between the first node N1 and the second node N2. The third transistor T3 can be turned on by a control scan signal controlling the scan line GCL, thereby connecting the first node N1 to the second node N2. Therefore, when the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode.

[0068] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by the first emitter control signal on the first emitter control line ECL1, so that the second node N2 is connected to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE.

[0069] The fifth transistor T5 can be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 can be turned on by the bias scan signal of the bias scan line GBL, thereby connecting the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0070] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 can be turned on by the second emitter control signal of the second emitter control line ECL2, so that the source electrode of the first transistor T1 is connected to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0071] The first capacitor CP1 can be disposed between the first node N1 and the drain electrode of the second transistor T2. The second capacitor CP2 can be disposed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0072] Each of the first transistors T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 can be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 can be an N-type MOSFET. For example, some of the first transistors T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0073] Despite Figure 3 The diagram shows the first sub-pixel SP1 comprising six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0074] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are not repeated in this disclosure.

[0075] Figure 4 This is a layout diagram illustrating a display panel according to some embodiments of the present disclosure.

[0076] Reference Figure 4According to some embodiments, the display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix. According to some embodiments, the non-display area NDA of the display panel 100 includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0077] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. However, this disclosure is not limited thereto, and the scan driver 610 and the transmit driver 620 can be disposed on both the first and second sides of the display area DAA.

[0078] The first pad portion PDA1 may include a plurality of first pads PD1 connected to the circuit board 300 by conductive adhesive members. The first pad portion PDA1 may be disposed on the third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be disposed on the outside of the data driver 700 in the second direction DR2.

[0079] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to fixtures or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0080] The second pad portion PDA2 can be disposed on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be disposed on the side of the display area DAA opposite to the side having the first pad portion PDA1 in the second direction DR2. The second pad portion PDA2 can be disposed outside the second distribution circuit 720 in the second direction DR2. In other words, the second pad portion PDA2 can be disposed further away from the display area DAA in the second direction than the second distribution circuit 720.

[0081] The first distribution circuit 710 can distribute the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one of the first pads PD1 in the first pad portion PDA1 to multiple data lines DL (see example). Figure 2As a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2.

[0082] The second distribution circuit 720 can distribute the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the side of the display area DAA opposite to the side having the first distribution circuit 710 in the second direction DR2.

[0083] The cathode connection portion CCA can be the display element layer EML (see example). Figure 7 The second electrode CAT (see example) Figure 7 The region connected to the first drive voltage line VSL of the non-display area NDA. The cathode connection portion CCA may be disposed on the outer side of at least one side of the display area DAA. For example, the cathode connection portion CCA may be disposed on the outer side of at least one of the left, right, upper, and lower sides of the display area DAA. For example, the cathode connection portion CCA may be as follows: Figure 4 The setup shown is configured around the display area DAA to significantly reduce or minimize deviations in the first drive voltage VSS caused by voltage drops (e.g., IR drops) or voltage rises (e.g., IR rises) of the second electrode CAT in the display area DAA.

[0084] Figure 5 This illustrates some embodiments according to the present disclosure. Figure 4 The layout diagram of the display area. Figure 6 This illustrates some other embodiments according to the present disclosure. Figure 4 The layout diagram of the display area.

[0085] Reference Figure 5 Each pixel PX includes a first emission region EA1 as the emission region of the first sub-pixel SP1, a second emission region EA2 as the emission region of the second sub-pixel SP2, and a third emission region EA3 as the emission region of the third sub-pixel SP3. (Refer to...) Figure 6 Each of the pixels PX also includes a fourth emission region EA4, which serves as the emission region of the fourth sub-pixel SP4.

[0086] The first launch area EA1, the second launch area EA2, and the third launch area EA3 can be arranged as follows in the plan view: Figure 5 and Figure 6 The quadrilateral or hexagonal shape shown is not the only one described herein. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal, circular, elliptical, or atypical shapes other than quadrilaterals or hexagons in the plan view.

[0087] like Figure 5 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other.

[0088] For example, such as Figure 6 As shown, the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape in the plan view. For example, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent in the second direction DR2. Additionally, the first emission region EA1 and the second emission region EA2 can be adjacent in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second diagonal direction DD2. Furthermore, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first diagonal direction DD1. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0089] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. Here, the first light can be light in the blue band, the second light can be light in the green band, and the third light can be light in the red band. For example, the blue band can be a band of light whose main peak wavelength is in the range of approximately 370 nm to approximately 460 nm, the green band can be a band of light whose main peak wavelength is in the range of approximately 480 nm to approximately 560 nm, and the red band can be a band of light whose main peak wavelength is in the range of approximately 600 nm to approximately 750 nm.

[0090] Each of the multiple pixels PX can include, for example Figure 5 The three launch regions EA1, EA2, and EA3 shown may include, for example, Figure 6 The four emission regions EA1, EA2, EA3, and EA4 are shown. For example, the fourth emission region EA4 can emit the same second light as the second emission region EA2, but this disclosure is not limited thereto.

[0091] The emission regions of multiple pixels PX can be arranged as a strip structure in which the emission regions are arranged in the first direction DR1, and a PenTile in which the emission regions are arranged in a diamond shape. ® The structure or the emission regions EA1, EA2, EA3 and EA4 that are all hexagonal in shape, such as Figure 6 The hexagonal structure arranged as shown in the figure.

[0092] Figure 7 This illustrates some embodiments according to this disclosure. Figure 5 The cross-sectional view of the display panel is taken by line I1-I1'.

[0093] Reference Figure 7 The display panel 100 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0094] The semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films (SINS1, SINS2, and SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) may be referenced... Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0095] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. For example, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0096] Each of the multiple well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to its drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0097] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can be disposed on the lower insulating film (BINS).

[0098] Each of the source region SA and the drain region DA can be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR can be stacked with the well region WA on the third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can be stacked with the gate electrode GE on the third direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0099] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, which may cause an increase in the length of the channel region CH in each of the pixel transistors PTR.

[0100] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0101] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through holes penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (INS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them.

[0102] The third semiconductor insulating film (SINS3) can be disposed on the side surface of each of the plurality of contact terminals (CTEs). The top surface of each of the plurality of contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3).

[0103] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0104] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate (such as polyimide). For example, thin-film transistors can be disposed on a glass substrate or a polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0105] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. Specifically, the backplane (EBP) of the light-emitting element includes a first conductive layer ML1 to an eighth conductive layer ML8 disposed between the multiple insulating films INS1 to INS9.

[0106] The first insulating films INS1 to the eighth insulating films INS8 are used to insulate the first conductive layers ML1 to the eighth conductive layers ML8. The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuit of the first sub-pixel SP1 shown.

[0107] For example, transistors T1 to T6 are formed only in the semiconductor backplane SBP, and the connection between transistors T1 to T6, the first capacitor CP1, and the second capacitor CP2 is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0108] The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first vias VA1 to VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first vias VA1 to VA8 can be made of substantially the same material. The first insulating film INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0109] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0110] Each of the plurality of ninth vias VA9 can penetrate the ninth insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0111] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth insulating film (INS10) and an eleventh insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0112] The reflective electrode RL can be disposed on the ninth insulating film INS9. The reflective electrode RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode RL may include... Figure 7 The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 are shown in the figure.

[0113] The first reflective electrode RL1 can be disposed on the ninth insulating film INS9 and can be connected to the ninth via VA9. Each of the second reflective electrodes RL2 can be disposed on its corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be disposed on its corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be disposed on its corresponding third reflective electrode RL3.

[0114] Because the fourth reflective electrode RL4 is the electrode that essentially reflects light from the light-emitting element LE, the thickness of the fourth reflective electrode RL4 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the second reflective electrode RL2.

[0115] The first reflective electrode RL1 may be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflective electrode RL1 may include titanium nitride (TiN), the second reflective electrode RL2 may include aluminum (Al), the third reflective electrode RL3 may include titanium nitride (TiN), and the fourth reflective electrode RL4 may include titanium (Ti).

[0116] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth insulating film INS10 can be a film used to flatten the stepped portion caused by the reflective electrode RL. The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode RL.

[0117] The tenth insulating film INS10 and the eleventh insulating film INS11 can be made of silicon dioxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0118] The eleventh insulating film INS11 can be an optical auxiliary layer used to adjust the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh insulating film INS11 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0119] For example, such as Figure 7 As shown, the thickness of the eleventh insulating film INS11 in the first sub-pixel SP1 can be less than the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh insulating film INS11 in the second sub-pixel SP2 can be less than the thickness of the eleventh insulating film INS11 in the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 can be less than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 can be less than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0120] Each of the tenth vias VA10 can penetrate the eleventh insulating film INS11 and connect to the exposed reflective electrode RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any of them. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be less than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0121] The first electrode AND of each of the light-emitting elements LE can be disposed on the eleventh insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth vias VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0122] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each of the light-emitting elements (LEs). The PDL can cover the edge (e.g., side surface) of the first electrode AND of each of the light-emitting elements (LEs). The PDL can separate a first emission region EA1, a second emission region EA2, and a third emission region EA3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a region of a light-emitting element (LE) comprising the first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0123] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0124] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x Inorganic films of the form of silicon nitride (SiN) can be formed. For example, the first pixel defining film PDL1 and the third pixel defining film PDL3 can be formed of silicon nitride (SiN). x Inorganic films of this type are formed, while the second pixel defining film PDL2 can be made of silicon oxide (SiO2). x ( ) Formation of inorganic films. The first pixel-defined film PDL1, the second pixel-defined film PDL2, and the third pixel-defined film PDL3 can all have a thickness of approximately 500 Å.

[0125] To prevent or reduce the likelihood of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio (e.g., amount) of the film being coated on inclined portions (e.g., vertical portions) to the degree (e.g., amount) of the film being coated on flat portions (e.g., horizontal portions). The lower the step coverage, the more likely the film will be cut at the inclined portions.

[0126] Each of the multiple trench TRCs can penetrate the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. The eleventh insulating film INS11 can be partially recessed at each of the multiple trench TRCs.

[0127] At least one trench TRC can be set between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 7 Two trench TRCs are shown positioned between adjacent sub-pixels SP1, SP2, and SP3, but this disclosure is not limited thereto.

[0128] The light-emitting stack IL can include multiple stacked layers IL1, IL2 and IL3. Figure 7 The illustration shows a light-emitting stack IL having a triple-tandem structure comprising a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, the light-emitting stack IL may have a double-tandem structure comprising two stacked layers.

[0129] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits a first light, a second stacked layer IL2 that emits a second light, and a third stacked layer IL3 that emits a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0130] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer are stacked sequentially. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer are stacked sequentially. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting third light, and a third electron transport layer are stacked sequentially.

[0131] A first charge generation layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first stacked layer IL1 and a P-type charge generation layer that supplies holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0132] A second charge generation layer for supplying charge to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0133] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and the residual film RIL disposed on the bottom surface of each trench TRC can include the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space can be disposed in the trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can be configured to cover the second stacked layer IL2 in each trench of the trench TRC.

[0134] In a three-series structure, each of the multiple trench TRCs can be a structure for cutting off the first hole transport layer to the third hole transport layer, the first charge generation layer, and the second charge generation layer of the display element layers EML between adjacent sub-pixels SP1, SP2, and SP3. Additionally, in a two-series structure, each of the multiple trench TRCs can be a structure for cutting off the charge generation layer and the lower stacked layer disposed between the lower and upper stacked layers.

[0135] To stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. To cut off the charge generation layer and hole transport layer of the light-emitting stack IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, another structure can exist to replace the trench TRCs. For example, instead of trench TRCs, inverted conical partition walls can be provided on the pixel defining film PDL.

[0136] in addition, Figure 7 The diagram shows a light-emitting stack IL disposed in a first emission region EA1, a second emission region EA2, and a third emission region EA3, but this disclosure is not limited thereto. For example, instead of the light-emitting stack IL, a first light-emitting layer may be disposed in the first emission region EA1, and the first light-emitting layer may be omitted from the second emission region EA2 and the third emission region EA3. Furthermore, a second light-emitting layer may be disposed in the second emission region EA2, and the second light-emitting layer may be omitted from the first emission region EA1 and the third emission region EA3. Furthermore, a third light-emitting layer may be disposed in the third emission region EA3, and the third light-emitting layer may be omitted from the first emission region EA1 and the second emission region EA2. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0137] The second electrode CAT can be disposed on the light-emitting stack IL. The second electrode CAT can be disposed on the third stacked layer IL3 in each trench of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material that can transmit light (e.g., transparent conductive oxide (TCO)) (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to the microcavity effect.

[0138] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one encapsulation inorganic film TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the display element layer EML or substantially reduce the possibility of oxygen or moisture penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be disposed on the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can be formed by multiple layers, in which silicon nitride (SiN) is used. x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO) layer x ) layer, titanium dioxide (TiO) x ) layer and alumina (AlO) x Two or more inorganic layers are stacked alternately in the layer.

[0139] Additionally, the encapsulation layer TFE may include at least one encapsulation organic film TFE2 to protect the display element layer EML from foreign matter such as dust. The at least one encapsulation organic film TFE2 of the encapsulation layer TFE may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The at least one encapsulation organic film TFE2 of the encapsulation layer TFE may be a monomer. For example, the at least one encapsulation organic film TFE2 of the encapsulation layer TFE may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0140] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Alternatively, the adhesive layer ADL can be a transparent adhesive component such as a transparent adhesive or a transparent adhesive resin.

[0141] The optical layer OPL may include multiple color filters CF1, CF2, and CF3, multiple second lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0142] A first color filter CF1 may be superimposed on a first emission region EA1 of a first sub-pixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light in the blue band). The blue band may be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color emitted from the first emission region EA1.

[0143] The second color filter CF2 can be superimposed on the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (e.g., light in the green band). The green band can be from about 480 nm to about 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0144] The third color filter CF3 can be superimposed on the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color (e.g., light in the red band). The red band can be from about 600 nm to about 750 nm. Therefore, the third color filter CF3 can transmit light of a third color emitted from the third emission region EA3.

[0145] Multiple second lenses (LNS) can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple second lenses (LNS) can be a structure for increasing the proportion of light directed toward the front of the display device 10. Each of the multiple second lenses (LNS) can have a cross-sectional shape that convexes in the upward direction. Each of the multiple second lenses (LNS) can include a microlens.

[0146] A filler layer (FIL) can be disposed on multiple second lenses (LNS). The filler layer (FIL) can have a refractive index (e.g., a preset or predetermined refractive index) such that light travels in the third-direction DR3 at the interface between the filler layer (FIL) and the multiple second lenses (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0147] A cover layer CVL can be disposed on a filler layer FLIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FLIL. For example, the filler layer FLIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be applied directly to the filler layer FLIL.

[0148] The polarizing plate (POL) can be disposed on one surface of the CVL (container layer). The polarizing plate (POL) can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, the polarizing plate (POL) can be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0149] Figure 8 This is a cross-sectional view of a display device according to some embodiments of the present disclosure.

[0150] Figure 8 The display device and the above Figure 7 The difference in the display device lies at least in the arrangement of the color filter and the second lens in the sub-pixel relative to the emission area, which will be described below.

[0151] like Figure 8 As shown, the first lens 777 can be disposed on the polarizing plate POL so as to be stacked with a plurality of second lenses SLS11, SLS22, SLS33, SLS44 and SLS55.

[0152] exist Figure 8 The image shows five sub-pixels: SP11, SP22, SP33, SP44, and SP55. For example, in... Figure 8 The diagram shows a first sub-pixel SP11, a second sub-pixel SP22, a third sub-pixel SP33, a fourth sub-pixel SP44, and a fifth sub-pixel SP55. Each of sub-pixels SP11, SP22, SP33, SP44, and SP55 may include a first electrode (hereinafter referred to as the anode electrode), a light-emitting stack IL, a second electrode CAT (hereinafter referred to as the cathode electrode CAT), a color filter, and a second lens (hereinafter referred to as the sub-lens).

[0153] The first sub-pixel SP11 may include a first emitting region EA11, a first anode electrode AND11, a light-emitting stack IL, a cathode electrode CAT, a first color filter CF11, and a first sub-lens SLS11. Here, the light-emitting stack IL of the first sub-pixel SP11 may mean (for example, refers to) the light-emitting stack IL between the first anode electrode AND11 and the cathode electrode CAT. The first color filter CF11 and the first sub-lens SLS11 may be stacked on top of each other.

[0154] The second sub-pixel SP22 may include a second emitting region EA22, a second anode electrode AND22, a light-emitting stack IL, a cathode electrode CAT, a second color filter CF22, and a second sub-lens SLS22. Here, the light-emitting stack IL of the second sub-pixel SP22 may mean the light-emitting stack IL between the second anode electrode AND22 and the cathode electrode CAT. The second color filter CF22 and the second sub-lens SLS22 may be stacked on top of each other.

[0155] The third sub-pixel SP33 may include a third emitting region EA33, a third anode electrode AND33, a light-emitting stack IL, a cathode electrode CAT, a third color filter CF33, and a third sub-lens SLS33. Here, the light-emitting stack IL of the third sub-pixel SP33 may mean the light-emitting stack IL between the third anode electrode AND33 and the cathode electrode CAT. The third color filter CF33 and the third sub-lens SLS33 may be stacked on top of each other.

[0156] The fourth sub-pixel SP44 may include a fourth emission region EA44, a fourth anode electrode AND44, a light-emitting stack IL, a cathode electrode CAT, a fourth color filter CF44, and a fourth sub-lens SLS44. Here, the light-emitting stack IL of the fourth sub-pixel SP44 can mean the light-emitting stack IL between the fourth anode electrode AND44 and the cathode electrode CAT. The fourth color filter CF44 and the fourth sub-lens SLS44 may be stacked on top of each other.

[0157] The fifth sub-pixel SP55 may include a fifth emitting region EA55, a fifth anode electrode AND55, a light-emitting stack IL, a cathode electrode CAT, a fifth color filter CF55, and a fifth sub-lens SLS55. Here, the light-emitting stack IL of the fifth sub-pixel SP55 may refer to the light-emitting stack IL between the fifth anode electrode AND55 and the cathode electrode CAT. The fifth color filter CF55 and the fifth sub-lens SLS55 may be stacked on top of each other.

[0158] The first sub-pixel SP11 can be disposed at the center of the display panel 100 (or the display area DAA of the display panel 100 or the first lens 777). For example, the first sub-pixel SP11 can be superimposed on the center of the first lens 777. For example, the center of the first anode electrode AND11, the center of the first emission area EA11, the center of the first color filter CF11, and the center of the first lens 777 can be superimposed on each other. Here, the first sub-pixel SP11 can be defined as the center sub-pixel.

[0159] The second sub-pixels SP22 to SP55 can be sequentially arranged on one side or the other side of the first sub-pixel SP11 relative to the first sub-pixel SP11. For example, the second sub-pixel SP22 and the third sub-pixel SP33 can be sequentially arranged on one side of the first sub-pixel SP11, and the fourth sub-pixel SP44 and the fifth sub-pixel SP55 can be sequentially arranged on the other side of the first sub-pixel SP11. Here, the second sub-pixels SP22 to SP55 can be defined as peripheral sub-pixels.

[0160] When a color filter and a sub-lens included in a sub-pixel are defined as a sub-optical layer of a sub-pixel, the center SC1 of the sub-optical layer of the center sub-pixel (e.g., the first sub-pixel SP11) located at the center of the display panel 100 (or at the center of the display area DAA, or at the center of the first lens 777) can be superimposed with the center EC1 of the first emission area EA11 of the center sub-pixel (e.g., the first sub-pixel SP11).

[0161] For example, the center of the sub-optical layer of the peripheral sub-pixel may not overlap with the center of the emission region of the peripheral sub-pixel. Therefore, the sub-optical layer of the peripheral sub-pixel may face the display panel 100 (or...) relative to the center of the emission region of the peripheral sub-pixel. Figure 1The display area DAA or the first lens 777 of the display panel 100 is offset by a certain distance (e.g., a preset or predetermined distance). For example, the sub-optical layer (or the center SC2 of the sub-optical layer) of the second sub-pixel SP22 may be offset by a certain distance (e.g., a preset or predetermined distance) relative to the center EC2 of the second emission area EA22 toward the edge of the display panel 100 (or the display area DAA or the first lens 777 of the display panel 100); the sub-optical layer (or the center SC3 of the sub-optical layer) of the third sub-pixel SP33 may be offset by a certain distance (e.g., a preset or predetermined distance) relative to the center EC3 of the third emission area EA33 toward the edge of the display panel 100 (or the display area DAA or the first lens 777 of the display panel 100). The sub-optical layer of the fourth sub-pixel SP44 (or the center SC4 of the sub-optical layer) may be offset by a certain distance (e.g., a preset or predetermined distance) relative to the center EC4 of the fourth emission region EA44 toward the edge of the display panel 100 (or the display area DAA of the display panel 100 or the first lens 777); and the sub-optical layer of the fifth sub-pixel SP55 (or the center SC5 of the sub-optical layer) may be offset by a certain distance (e.g., a preset or predetermined distance) relative to the center EC5 of the fifth emission region EA55 toward the edge of the display panel 100 (or the display area DAA of the display panel 100 or the first lens 777).

[0162] The sub-optical layer of an outer sub-pixel can be offset by a larger amount as its distance from the central sub-pixel increases. For example, in the second sub-pixel SP22 and the third sub-pixel SP33, which are sequentially located on one side of the first sub-pixel SP11, the third sub-pixel SP33, which is relatively farther away from the first sub-pixel SP11, can include a sub-optical layer that is offset by a larger amount than the sub-optical layer of the second sub-pixel SP22. As another example, in the fourth sub-pixel SP44 and the fifth sub-pixel SP55, which are sequentially located on the other side of the first sub-pixel SP11, the fifth sub-pixel SP55, which is relatively farther away from the first sub-pixel SP11, can include a sub-optical layer that is offset by a larger amount than the sub-optical layer of the fourth sub-pixel SP44.

[0163] In other words, sub-pixels SP11 to SP55 may include sub-optical layers that are offset by a greater extent as the sub-pixels SP11 to SP55 are positioned away from the center of the display panel 100 (or the display area DAA of the display panel 100 or the first lens 777). For example, when the distance between the center of the emission area of ​​a sub-pixel and the center of the sub-optical layer of the sub-pixel is defined as the offset distance of the sub-pixel (or the offset distance of the sub-optical layer of the sub-pixel), the offset distance d1 of the first sub-pixel SP11 can be substantially zero; the offset distance d3 of the third sub-pixel SP33 can be greater than the offset distance d2 of the second sub-pixel SP22; and the offset distance d5 of the fifth sub-pixel SP55 can be greater than the offset distance d4 of the fourth sub-pixel SP44.

[0164] As described above, since sub-pixels SP11 to SP55 include a sub-optical layer that is offset by a greater extent as the sub-pixels SP11 to SP55 are positioned away from the center of the display panel 100 (or the display area DAA of the display panel 100 or the first lens 777), light at the edge of the first lens 777 can be emitted to the outside while satisfying the principal ray angle (CRA).

[0165] According to some embodiments, the deviation of the offset distance between adjacent sub-pixels along the virtual line connecting the center of the display panel 100 (or the display area DAA or the first lens 777 of the display panel 100) and the edge of the display panel 100 (or the display area DAA or the first lens 777 of the display panel 100) can be in the range of about 0.001 μm to about 0.009 μm. For example, the aforementioned offset distance deviation can be about 0.001 μm. For example, the difference between the offset distance d2 of the second sub-pixel SP22 and the offset distance d3 of the third sub-pixel SP33 can be about 0.001 μm. As described above, because the offset deviation between adjacent sub-pixels is relatively small, the rate of change of the principal ray angle can be gradually achieved based on the distance from the center of the display panel 100 (or the display area DAA or the first lens 777 of the display panel 100) to the sub-pixel. For example, the rate of change of the principal ray angle can gradually increase proportionally to the distance from the center of the display panel 100 (or the display area DAA or the first lens 777 of the display panel 100) to the sub-pixel. Therefore, the occurrence of stains (e.g., barcode stains) at the edges of the display panel 100 can be further minimized or significantly reduced, thereby improving the image quality of the display device 10.

[0166] For example, Figure 7 The components between the semiconductor substrate SSUB and the eleventh insulating film INS11 can also be arranged in Figure 8 Between the substrate SSUB (e.g., semiconductor substrate SSUB) and the eleventh insulating film INS11.

[0167] also, Figure 8 The pixel-limited film PDL can include Figure 7 The first pixel limiting film PDL1, the second pixel limiting film PDL2, and the third pixel limiting film PDL3.

[0168] in addition, Figure 8 The light-emitting stack IL can include Figure 7 The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3.

[0169] also, Figure 8 The encapsulation layer TFE may include Figure 7 The first encapsulation inorganic film TFE1, the encapsulation organic film TFE2, and the second encapsulation inorganic film TFE3.

[0170] Figure 9 This is a diagram illustrating the effect of a display device according to some embodiments of the present disclosure.

[0171] exist Figure 9 In this diagram, the X-axis represents distance, and the Y-axis represents the angle of the main ray. Here, the X-axis can mean the distance from the center of the display panel to the sub-pixel. For example... Figure 9 As shown, the principal ray angle can vary exponentially as the distance from the center of the display panel to the sub-pixel increases. For example, the rate of change of the principal ray angle can be gradually adjusted based on the distance from the center of the display panel. Therefore, the image quality of the display device can be improved.

[0172] Figure 10 This is a perspective view illustrating a head-mounted display according to some embodiments of the present disclosure. Figure 11 This illustrates some embodiments according to the present disclosure. Figure 10 An exploded perspective view of the head-mounted display.

[0173] Reference Figure 10 and Figure 11 According to some embodiments, a head-mounted display 1000 may include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0174] The first display device 10_1 can provide an image to the user's left eye, and the second display device 10_2 can provide an image to the user's right eye. This is because each of the first display device 10_1 and the second display device 10_2 is combined with... Figures 1 to 8The display devices 10 described are essentially the same, so the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0175] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0176] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0177] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data (see example...). Figure 2 And through the connector, digital video data DATA is sent to the first display device 10_1 and the second display device 10_2.

[0178] The control circuit board 1600 can send digital video data DATA corresponding to a left-eye image suitable for the user's left eye (e.g., adjusted for the user's left eye) to the first display device 10_1, and can send digital video data DATA corresponding to a right-eye image suitable for the user's right eye (e.g., adjusted for the user's right eye) to the second display device 10_2. For example, the control circuit board 1600 can send the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0179] The display device housing 1100 can be used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 positioned thereon for the user's left eye and a second eyepiece 1220 positioned thereon for the user's right eye. Figure 10 and Figure 11 The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately configured, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0180] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0181] The headband 1300 can be used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display 1000 can be configured as follows: Figure 12 The eyeglasses frame shown is not the headband 1300.

[0182] Figure 12 This is a perspective view illustrating a head-mounted display according to some embodiments of the present disclosure.

[0183] Reference Figure 12 According to some embodiments, the head-mounted display 1000_1 may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. According to some embodiments, the head-mounted display 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path alteration component 1070, and a display device housing 1200_1.

[0184] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the light path changing component 1070. An image displayed on (e.g., displayed by) the display device 10_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye via the right eye lens 1020. As a result, the user can view an augmented reality image through their right eye, which combines a virtual image displayed on the display device 10_3 with a real image seen through the right eye lens 1020.

[0185] Figure 12The display device housing 1200_1 is shown positioned at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and, for example, the image displayed on the display device 10_3 may be provided to the user's left eye. For example, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 10_3 through both the left and right eyes.

[0186] The display device according to some embodiments can be applied to a variety of suitable electronic devices. The electronic device according to some embodiments includes the above-described display device, and may also include modules or devices with additional functions in addition to the display device.

[0187] Figure 13 This is a block diagram of an electronic device according to some embodiments of the present disclosure. (See also...) Figure 13 According to some embodiments, the electronic device 50 may include a display module 11 (e.g., a display device), a processor 12, a memory 13, and a power module 14. The electronic device 50 may also include an input module 15, a non-image output module 16 (e.g., an output module), and a communication module 17.

[0188] Electronic device 50 can output various information in the form of images through display module 11. When processor 12 executes an application stored in memory 13, the image information provided by the application can be provided to the user through display module 11. Power module 14 may include a power module (such as a power adapter or battery device) and a power conversion module, which converts the power supplied by the power module to generate power for the operation of electronic device 50. Input module 15 can provide input information to processor 12 and / or display module 11. Non-image output module 16 can receive information other than images (such as sound, touch, and light) sent from processor 12 and provide the information to the user. Communication module 17 is responsible for sending and receiving information between electronic device 50 and external devices, and may include receiving unit and sending unit.

[0189] At least one of the components of the electronic device 50 described above may be included in the display device according to the above embodiment. Additionally, some of the modules functionally included in a single module may be included in the display device, while other modules may be disposed separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed as other devices within the electronic device 50 besides the display device.

[0190] Figure 14 , Figure 15 and Figure 16 This is a schematic diagram of an electronic device according to some embodiments of the present disclosure. Figures 14 to 16 Examples of various electronic devices to which the display device according to the embodiments can be applied are shown.

[0191] Figure 14 Examples of electronic devices are shown, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0192] In addition to the display module 11, the smartphone 10_1a may include an input module (such as a touch sensor) and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules and display the information through the display module of the display device.

[0193] In the cases of tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e, similar to smartphone 10_1a, they may include a display module and an input module, and in some cases may additionally include a communication module.

[0194] Figure 15 An example of an electronic device is shown, including a display module for use in wearable electronic devices. Wearable electronic devices may include smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.

[0195] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits light to display images and a reflector that reflects the light emitted from the display screen and provides it to the user's eyes, thereby providing the user with virtual reality or augmented reality images.

[0196] The smartwatch 10_2c may include a biometric sensor as an input device and may provide the user with biometric information identified by the biometric sensor through a display module.

[0197] Figure 16 The illustration shows an application of an electronic device, including a display module, in a vehicle (e.g., a motor vehicle). For example, the electronic device 10_4 can be applied to the vehicle's dashboard, central instrument panel, etc., or it can be applied to a CID (Central Information Display) placed on the vehicle's dashboard or an interior mirror display that replaces the side mirrors.

[0198] It should be understood that the embodiments described herein are to be considered descriptive and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display device, characterized in that, The display device includes: The substrate includes both the display area and the non-display area; Multiple anode electrodes are disposed on the substrate; A pixel-defining film is provided on the plurality of anode electrodes and defines a plurality of emission regions; Light-emitting stacked components are present on the pixel defining film and the plurality of anode electrodes; Cathode electrode, on the light-emitting stack; Multiple sub-optical layers on the cathode electrode; and Lenses, on the plurality of sub-optical layers, The plurality of sub-pixels includes the plurality of anode electrodes, the plurality of emitting regions, the light-emitting stack, the cathode electrode, and the plurality of sub-optical layers. The plurality of sub-optical layers are offset by a greater magnitude as their distance from the center of the display area increases. The offset distance between adjacent sub-pixels varies from 0.001μm to 0.009μm.

2. The display device according to claim 1, characterized in that, The deviation of the offset distance between adjacent sub-pixels is 0.001 μm.

3. The display device according to claim 1, characterized in that, Each of the plurality of sub-optical layers includes: Color filters; and A sub-lens is placed on the color filter and superimposed on the color filter.

4. The display device according to claim 3, characterized in that, The lens is stacked with multiple sub-lenses of the multiple sub-pixels.

5. The display device according to claim 3, characterized in that, The sub-lens includes microlenses.

6. The display device according to claim 1, characterized in that, The offset distance is the distance between the center of the emission region of one of the plurality of sub-pixels and the center of the sub-optical layer of that one of the plurality of sub-pixels.

7. The display device according to claim 1, characterized in that, The adjacent sub-pixels are those adjacent along a virtual line that connects the center of the display area to the edge of the display area.

8. The display device according to claim 1, characterized in that, The rate of change of the main ray angle varies gradually based on the distance from the center of the display area to one of the plurality of sub-pixels.

9. The display device according to claim 8, characterized in that, The rate of change of the main ray angle gradually increases proportionally to the distance from the center of the display area to one of the plurality of sub-pixels.

10. The display device according to claim 1, characterized in that, The lens includes a pancake lens.

Images