Wafer state detection device

Abstract

The application provides a wafer state detection device, comprising: a light source for irradiating a wafer to be detected; a light path folding device for guiding reflected light of a left side area, a central area and a right side area of the wafer to be detected to an imaging module; and a processing module for determining the number of heavy pieces according to the upper and lower edge pixel distances of the wafer to be detected and the upper and lower edge pixel distances of a standard wafer obtained by the imaging module. The processing module is used for determining the angle of a bevel piece according to the first linear slope, the second linear slope and the third linear slope of the wafer upper edge or the wafer lower edge obtained by fitting the left side area image, the central area image and the right side area image obtained by the imaging module respectively. The processing module is used for determining the warping amount according to the corresponding size of the object side pixel and the maximum longitudinal pixel interval of the wafer upper edge or the wafer lower edge obtained by the imaging module, so as to realize quantitative detection of the wafer state.

Description

Technical Field

[0001] This application relates to the field of wafer condition detection, specifically to a wafer condition detection device. Background Technology

[0002] In the semiconductor manufacturing industry, traditional wafer scanning operations typically rely on range sensors to scan the wafer cassette point by point to determine the state of each wafer within the cassette. However, this method is inefficient and has limited ability to identify abnormal states such as overlapping or tilted wafers.

[0003] Furthermore, existing technologies cannot achieve rapid, high-precision quantitative detection of the state of the wafer under test. Specifically, they cannot accurately determine the number of overlapping wafers, cannot accurately calculate the angle of the skewed wafers, and are even less able to quantify the amount of wafer warpage. This lack of quantitative detection capability makes it difficult for existing technologies to support the higher requirements of process control and yield analysis in highly automated semiconductor production lines. Utility Model Content

[0004] In view of the above problems, this application provides a wafer condition detection device, which overcomes or at least partially solves the problem that the prior art cannot achieve rapid and high-precision quantitative detection of wafer condition.

[0005] A first aspect of this application provides a wafer state detection device, including: a wafer cell, a light source, a refracting optical path, an imaging module, a scanning control module, and a processing module.

[0006] The wafer cassette stores the wafer under test (DUT), the light source illuminates the DUT, and the deflection optical path guides the reflected light from the left, central, and right sides of the DUT to the imaging module. The scanning control module fixes the light source, deflection optical path, and imaging module. The scanning control module also scans the wafer cassette to ensure the light source illuminates the next DUT in the next slot within the cassette. The processing module determines the number of duplicate wafers based on the pixel distances between the top and bottom edges of the DUT and the standard wafer, obtained by the imaging module.

[0007] The processing module is used to determine the slant angle based on the first, second, and third straight line slopes of the upper or lower edge of the wafer obtained by fitting the left, central, and right region images acquired by the imaging module.

[0008] The processing module is used to determine the warpage amount based on the size of the object pixels and the maximum vertical pixel spacing of the upper or lower edge of the wafer obtained from the left, central, and right region images acquired by the imaging module.

[0009] In this embodiment, the scanning control module enables rapid scanning of all wafers to be tested within the wafer cassette, and the processing module performs quantitative calculations on the imaging images. This fundamentally overcomes the shortcomings of existing technologies, such as low detection efficiency and inability to perform quantitative measurements. It can simultaneously and accurately output three key physical parameters: the number of wafers overlapped, the wafer angle, and the warpage, providing precise data support for automated production lines.

[0010] By setting up a folding optical path, image information of the left, central, and right regions of the wafer under test can be acquired simultaneously in a single imaging operation. This not only solves the problem that single-point scanning or single-view imaging is difficult to identify skewed wafers and warping, but also greatly improves the ability to identify complex abnormal states (such as slight warping and asymmetric tilt) and the reliability of detection results through cross-validation and fusion calculation of multi-view information.

[0011] Moreover, by guiding the three reflected lights to the same imaging module through a folding optical path, multi-view synchronous imaging is achieved using only one set of light source and imaging module, avoiding the high cost, large size, and synchronization problems associated with using multiple imaging systems. At the same time, the folding optical path effectively reduces the stringent requirements of the detection device on the depth of field of the imaging module, simplifies the mechanical structure, and achieves miniaturization and low cost of the detection device while ensuring high precision.

[0012] Furthermore, this application performs edge localization and line fitting based on clear two-dimensional images, which has lower algorithm complexity and faster calculation speed, thus effectively solving the contradiction between detection efficiency and accuracy and meeting the high real-time requirements of industrial sites.

[0013] In one alternative approach, the reflected light from the refracted optical path and the illumination light from the light source form a light plane, which is parallel to the plane of the standard wafer under test. It is understood that the plane of the standard wafer under test refers to the plane of the wafer under test placed in the wafer cassette without overlap, tilting, or warping.

[0014] This establishes a stable and consistent detection reference plane, eliminating imaging distortion and measurement errors, and facilitating the formation of highly contrasting images with extremely clear boundaries on the imaging module. This provides better raw data for sub-pixel-level edge localization and line fitting, and improves the measurement accuracy of the number of overlapping slices, the angle of the slice, and the amount of warpage.

[0015] In one alternative approach, the light source is either a line light source or a strip light source.

[0016] In this embodiment, by setting the light source as a line light source or a narrow strip light source, it can be ensured that the optical signal received by the imaging module uniquely corresponds to the edge of the single wafer under test.

[0017] In one alternative embodiment, the optical path includes six right-angle prism reflectors, of which four right-angle prism reflectors are right-angle prisms with beveled edge reflections used to guide the reflected light from the left and right regions of the wafer under test, and two right-angle prisms are right-angle prisms with right-angled edge reflections used to guide the reflected light from the central region of the wafer under test.

[0018] In one alternative approach, the imaging module includes a lens and a detector, the lens being used to focus reflected light passing through a refracted optical path, and the detector being used to convert the reflected light into an image.

[0019] In one alternative approach, the optical path is configured such that the left imaging channel for guiding the reflected light to the left side of the wafer under test and the right imaging channel for guiding the reflected light to the right side of the wafer under test are arranged in a symmetrical optical path layout, and the central imaging channel for guiding the reflected light to the central side of the wafer under test compensates for the optical path difference between the central imaging channel and the left and right imaging channels through optical path folding.

[0020] In this embodiment, by configuring the left and right imaging channels with a symmetrical optical path layout, the consistency of the optical path length within the left and right imaging channels can be ensured. The central imaging channel compensates for the optical path difference between the left and right imaging channels through optical path folding, so that the object distance of the left, right, and central imaging channels remains consistent, ensuring that the imaging images of the left, right, and central imaging channels can be clearly imaged simultaneously on the imaging module.

[0021] In one alternative configuration, the number of reflections in the left imaging channel, right imaging channel, and central imaging channel are all configured to be an even number.

[0022] In this way, it can be ensured that the imaging images corresponding to the left, central and right regions of the wafer under test are consistent in direction and are all "positive images", thus ensuring the consistency and accuracy of the detection.

[0023] A second aspect of this application provides a wafer state detection method, comprising: storing a wafer to be tested in a wafer cassette; illuminating the wafer to be tested with a light source; guiding reflected light from the left, central, and right regions of the wafer to be tested to an imaging module via a deflected optical path; determining the number of wafers to be re-machined based on the pixel distances between the upper and lower edges of the wafer to be tested and the pixel distances between the upper and lower edges of a standard wafer obtained by the imaging module; determining the slant angle based on the slopes of a first straight line, a second straight line, and a third straight line obtained by fitting images of the left, central, and right regions of the wafer to the image obtained by the imaging module; determining the warpage amount based on the object-side pixel corresponding size and the maximum longitudinal pixel interval of the upper or lower edge of the wafer obtained by the imaging module from the images of the left, central, and right regions; and scanning a control module scanning the wafer cassette to illuminate the next wafer to be tested in the next slot within the wafer cassette.

[0024] The wafer condition detection method provided in this embodiment can simultaneously and accurately output three key physical parameters: the number of wafer overlaps, the wafer tilt angle, and the warpage amount, providing precise data support for automated production lines. It solves the problem of single-point scanning or single-view imaging's difficulty in identifying wafer tilt and warpage. Furthermore, through cross-validation and fusion calculation of multi-view information, it greatly improves the ability to identify complex abnormal states (such as slight warpage and asymmetric tilt) and the reliability of detection results. In addition, this application uses clear two-dimensional images for edge localization and line fitting, resulting in lower algorithm complexity and faster calculation speed. This effectively resolves the contradiction between detection efficiency and accuracy, meeting the high real-time requirements of industrial environments.

[0025] In one alternative approach, after the scanning control module scans the wafer cassette to illuminate the next wafer under test in the next slot within the wafer cassette, the method further includes: after determining the number of wafers stacked, the tilt angle, and the warpage of each wafer under test in any slot within the wafer cassette, outputting an overall status file or image file of each wafer under test within the wafer cassette for manual or robotic adjustment of the wafer status and subsequent wafer handling operations.

[0026] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a wafer condition detection device provided in some embodiments of this application.

[0029] Figure 2 The schematic diagrams are provided for some embodiments of the present application to illustrate the principle of wafer state detection.

[0030] Figure 3 This is a schematic diagram of the imaging area and detector imaging of a possible wafer under test within a wafer cassette, provided for some embodiments of this application.

[0031] Figure 4 This is a schematic flowchart of a wafer state detection method provided in some embodiments of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0034] The terms "comprising" and "having," and any variations thereof, used in the specification, claims, and drawings of this application are intended to cover without excluding other meanings. The words "a" or "an" do not exclude the existence of multiple entities.

[0035] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0037] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0038] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, "connection" or "linkage" in mechanical structures can refer to a physical connection, such as a fixed connection, for example, a connection fixed by fasteners, such as a connection fixed by screws, bolts, or other fasteners; a physical connection can also be a detachable connection, such as a snap-fit ​​or interlocking connection; a physical connection can also be an integral connection, such as a connection formed by welding, bonding, or integral molding. In circuit structures, "connection" or "linkage" can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is connected; it can also refer to the internal connection of two components. Signal connection can refer not only to signal connection through a circuit but also to signal connection through a media, such as radio waves. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0039] Figure 1 This is a schematic diagram of the structure of a wafer condition detection device provided in some embodiments of this application. Figure 2 This is a schematic diagram illustrating the wafer state detection principle provided for some embodiments of this application. (Reference) Figure 1 and Figure 2 A wafer condition detection device includes: a wafer cassette 01, a light source 02, a refractive optical path 03, an imaging module 04, a scanning control module, and a processing module. The light source 02 can be positioned in front of the refractive optical path 03, and the processing module can be connected to the imaging module 04.

[0040] The wafer cassette 01 stores the wafer under test 05. The size and specifications of the wafer cassette and the wafer under test 05 inside are not limited, such as 6 inches, 8 inches, 12 inches, etc. The light source 02 illuminates the wafer under test 05. The deflecting optical path 03 guides the reflected light from the left, central, and right sides of the wafer under test 05 to the imaging module 04. The scanning control module fixes the light source 02, the deflecting optical path 03, and the imaging module 04. The scanning control module also vertically scans the wafer cassette 01 so that the light source 02 illuminates the next wafer under test 05 in the next slot within the wafer cassette 01. For example, the scanning control module can sequentially scan the slots within the wafer cassette 01 along the direction of gravity. The scanning control module can be communicatively coupled to the imaging module 04. Specifically, the scanning control module can send a trigger signal to the imaging module 04 when it determines that the imaging module 04 has reached the scanning position of the target slot, based on real-time position information fed back by its built-in encoder. Imaging module 04 acquires an imaging image in response to a trigger signal and binds the imaging image to a slot number determined by real-time location information.

[0041] The processing module is used to determine the number of duplicate wafers m based on the pixel distance N between the top and bottom edges of the wafer under test and the pixel distance n between the top and bottom edges of the standard wafer obtained by the imaging module 04.

[0042] The number of duplicate pieces m is .

[0043] The pixel distance between the top and bottom edges of a standard wafer refers to the number of pixels occupied by the top and bottom edges of a normal, flat single wafer in the imaging image, as determined during the calibration phase of the inspection device. The value of the pixel distance between the top and bottom edges of a standard wafer is a constant fixed through the calibration process.

[0044] The processing module is used to determine the slant angle d based on the first straight line slope a, the second straight line slope b, and the third straight line slope c obtained by fitting the left region image, the central region image, and the right region image acquired by the imaging module 04 to the wafer upper edge or wafer lower edge.

[0045] Slant angle d: .

[0046] Understandably, in a two-dimensional imaging image, the slope of the fitted straight line along the top and bottom edges of a flat, untilted wafer is the same. If it is tilted, the slopes of the top and bottom edges will change simultaneously and in the same direction. Therefore, in principle, measuring the slope of either the top or bottom edge of the wafer is sufficient to reflect the degree of tilt of the entire wafer.

[0047] It is worth noting that when overlapping occurs, the lower edges of the two wafers are tightly fitted together, which may not be distinguishable in the imaging image. However, the upper edges of the wafers are usually easier to distinguish and fit because of the gap.

[0048] If the wafer 05 to be tested is completely flat and placed upright, then its edges should be horizontal when viewed from three angles, i.e., a ≈ b ≈ c ≈ 0.

[0049] Thus, through image processing algorithms, the optical bright lines representing the wafer edge seen from three different perspectives are abstracted into three calculable mathematical slope values. These three slope values ​​and their differences are the direct basis for accurately determining the wafer tilt state and performing quantitative calculations.

[0050] The processing module is used to determine the warpage amount WARP based on the object pixel corresponding size k and the maximum vertical pixel interval n of the upper or lower edge of the wafer obtained from the left region image, central region image and right region image acquired by the imaging module 04.

[0051] For example, the vertical pixels of the upper edge of the wafer obtained by the imaging module 04 from the left region image, the central region image and the right region image are 300 pixels, 250 pixels and 255 pixels respectively. Then the maximum vertical pixel interval n is 300 minus 250, which is 50 pixels.

[0052] Determine the warpage amount WARP: WARP = k*n, where the unit of the object-side pixel size k is micrometers per pixel (μm / pixel). The object-side pixel size k is determined by the detection device and can be determined through calibration. Its value is the ratio of the known feature size D of a standard reference object to the number of pixels Q occupied by that feature in the imaging image, i.e., k = D / Q.

[0053] In this embodiment, the scanning control module enables rapid scanning of all wafers 05 to be tested within the wafer cassette 01, and the processing module performs quantitative calculations on the imaging images. This fundamentally overcomes the shortcomings of existing technologies, such as low detection efficiency and inability to perform quantitative measurements. It can simultaneously and accurately output three key physical parameters: the number of wafers overlapped, the wafer angle, and the warpage, providing precise data support for automated production lines.

[0054] By setting up the folding optical path 03, image information of the left, central and right regions of the wafer under test 05 can be acquired simultaneously in a single imaging. This not only solves the problem that single-point scanning or single-view imaging is difficult to identify slant and warping, but also greatly improves the ability to identify complex abnormal states (such as slight warping and asymmetric tilt) and the reliability of detection results through cross-validation and fusion calculation of multi-view information.

[0055] Furthermore, by guiding the three reflected lights to the same imaging module 04 through the folding optical path 03, multi-view synchronous imaging is achieved using only one set of light source and imaging module 04, avoiding the high cost, large size, and synchronization problems associated with using multiple imaging systems. At the same time, the folding optical path 03 effectively reduces the stringent requirements of the detection device on the depth of field of the imaging module 04, simplifies the mechanical structure, and achieves miniaturization and low cost of the detection device while ensuring high precision.

[0056] Furthermore, this embodiment performs edge localization and line fitting based on clear two-dimensional images, which has low algorithm complexity and faster calculation speed, thus effectively solving the contradiction between detection efficiency and accuracy, and meeting the high real-time requirements of industrial sites.

[0057] In some embodiments, the reflected light from the deflected optical path 03 and the illumination light from the light source 02 form a light plane, which is parallel to the plane of the standard wafer under test. Furthermore, the light plane is perpendicular to the imaging plane. It is understood that the plane of the standard wafer under test refers to the plane of the wafer 05 placed in the wafer cassette 01 when it is not overlapped, tilted, or warped.

[0058] In this way, a stable and consistent detection reference plane is established, eliminating imaging distortion and measurement errors, and facilitating the formation of highly contrasting and sharply defined images on imaging module 04. This provides better raw data for sub-pixel level edge localization and line fitting, and improves the measurement accuracy of the number of overlapping slices, the angle of the slice, and the amount of warpage.

[0059] In some embodiments, the light source 02 is a line light source or a strip light source.

[0060] In this embodiment, by setting the light source 02 as a line light source or a narrow strip light source, it can be ensured that the optical signal received by the imaging module 04 uniquely corresponds to the edge of the single wafer 05 under test.

[0061] In some embodiments, reference Figure 1 and Figure 2 The optical path 03 includes 6 right-angle prism reflectors. Among them, 4 right-angle prism reflectors are right-angle prisms with beveled edge reflection used to guide the reflected light from the left and right regions of the wafer 05 under test, and 2 right-angle prisms are right-angle prisms with right-angle edge reflection used to guide the reflected light from the central region of the wafer 05 under test.

[0062] In practical applications, the folding optical path 03 can also be a plane mirror.

[0063] In some embodiments, the imaging module 04 includes a lens 041 and a detector 042. The lens 041 is used to focus reflected light passing through the refracting optical path 03, and the detector 042 is used to convert the reflected light into an image. The detector 042 may be a CCD camera.

[0064] In some embodiments, reference Figure 1 and Figure 2 The optical path 03 is configured such that the left imaging channel 031, which guides the reflected light from the left side of the wafer 05 under test, and the right imaging channel 032, which guides the reflected light from the right side of the wafer 05 under test, are arranged in a symmetrical optical path layout. The central imaging channel 033, which guides the reflected light from the central area of ​​the wafer 05 under test, compensates for the optical path difference between the central imaging channel 033 and the left imaging channel 031 and the right imaging channel 032 through optical path folding.

[0065] In this embodiment, by configuring the left imaging channel 031 and the right imaging channel 032 with a symmetrical optical path layout, the consistency of the optical path length within the left imaging channel 031 and the right imaging channel 032 can be ensured. The central imaging channel 033 compensates for the optical path difference between the left imaging channel 031 and the right imaging channel 032 through optical path folding, so that the object distance of the left imaging channel 031, the right imaging channel 032 and the central imaging channel 033 can be kept consistent, ensuring that the imaging images of the left imaging channel 031, the right imaging channel 032 and the central imaging channel 033 can be clearly imaged simultaneously on the imaging module 04. Figure 3 This is a schematic diagram illustrating the imaging region and detector imaging of a possible wafer under test within a wafer cassette, provided for some embodiments of this application. (Reference) Figure 3 , Figure 3 The imaging images of the left side region 1, the right side region 3, and the central region 2 of three wafers under test on detector 042 are shown in the first imaging image 11, the second imaging image 13, and the third imaging image 12. It can be seen that... Figure 3 All three wafers under test were in normal condition.

[0066] In some embodiments, the number of reflections of the left imaging channel 031, the right imaging channel 032, and the central imaging channel 033 are all configured to be an even number.

[0067] In this way, it can be ensured that the imaging images corresponding to the left, central and right regions of the wafer under test 05 are consistent in direction and are all "positive images", thus ensuring the consistency and accuracy of the detection.

[0068] It should be noted that the optical path lengths of the left imaging channel 031 and the right imaging channel 032, as well as the optical path folding position, direction, and distance of the central imaging channel 033, can be flexibly adjusted according to different application scenarios to meet the inspection requirements of wafer cassettes and wafers of different sizes.

[0069] It is worth noting that if only basic qualitative identification of the state of the wafer 05 to be tested in wafer box 01 is required, such as overlapping, tilting, missing wafers, etc., a database can be built by learning from a large number of imaging image samples in the early stage. During actual testing, the imaging images are compared with the built database to achieve rapid identification and judgment of abnormal states.

[0070] In practical applications, the detection device can be calibrated before use to ensure that the optical plane is parallel to the plane of the standard wafer under test, perpendicular to the imaging plane, and that the scanning control module has been reset and initialized.

[0071] Another embodiment of this application provides a wafer condition detection method. Figure 4 This is a flowchart illustrating a wafer state detection method provided in some embodiments of this application, such as... Figure 4 As shown, the wafer state detection method provided in this application embodiment includes the following steps 401 to 407: Step 401: The wafer box stores the wafer to be tested.

[0072] Step 402: Illuminate the wafer to be tested with a light source.

[0073] Step 403: Fold the optical path to guide the reflected light from the left, central and right regions of the wafer under test to the imaging module.

[0074] Step 404: The processing module determines the number of duplicate wafers based on the pixel distance between the top and bottom edges of the wafer under test and the pixel distance between the top and bottom edges of the standard wafer obtained by the imaging module.

[0075] Step 405: The processing module determines the slant angle based on the first, second, and third straight line slopes of the upper or lower edge of the wafer obtained by fitting the left, central, and right region images acquired by the imaging module.

[0076] Step 406: The processing module determines the warpage amount based on the size of the object pixels and the maximum vertical pixel spacing of the upper or lower edge of the wafer obtained from the left, central, and right region images acquired by the imaging module.

[0077] Step 407: The scanning control module scans the wafer cassette so that the light source illuminates the next wafer to be tested in the next slot within the wafer cassette.

[0078] Continue repeating steps 403-407 to determine the number of wafers to be re-tested, the skew angle, and the warpage of the next wafer to be tested.

[0079] In some embodiments, after the scanning control module scans the wafer cassette to illuminate the next wafer to be tested in the next slot within the wafer cassette, the method further includes: after determining the number of wafers to be tested, the tilt angle, and the warpage of each wafer to be tested in any slot within the wafer cassette, outputting an overall status file or image file of each wafer to be tested within the wafer cassette for manual or robotic adjustment of the wafer status and subsequent wafer handling operations.

[0080] For example, the overall status file for each wafer under test could be: Slot 1: wafer present, normal status; Slot 2: empty; Slot 3: wafer present, abnormal status - overlap; Slot 4: wafer present, abnormal status - tilted, angle 1.5 degrees; Slot 5: wafer present, abnormal status - warped, warping amount 200 micrometers. The image file could be a composite image that displays all the scanned wafer edge images in slot order, highlighting the number of overlaps, tilt angle, and warping amount at abnormal locations with prominent markers such as red boxes, arrows, and text annotations.

[0081] If the status indicator shows "normal," the robotic arm will proceed to the slot to retrieve the wafer. If the status indicator shows "empty," the robotic arm will skip the slot to avoid performing an invalid "grab" action, saving production time. If the status indicator shows "abnormal," the robotic arm can stop immediately or skip the abnormal slot to prevent forcibly grabbing overlapping or tilted wafers, which could lead to catastrophic wafer collisions, damaging expensive wafers and the precision robotic arm.

[0082] When an abnormal condition occurs, the operator can manually and safely open the wafer cassette to adjust the situation. For example, this includes carefully separating overlapping wafers using specialized tools, straightening tilted wafers, and removing wafer fragments. After manual adjustment, the aforementioned wafer condition detection steps can be repeated to confirm whether the wafer condition issue has been resolved, thus ensuring the production line can continue to operate automatically.

[0083] The wafer condition detection method provided in this embodiment can simultaneously and accurately output three key physical parameters: the number of wafer overlaps, the wafer tilt angle, and the warpage amount, providing precise data support for automated production lines. It solves the problem of single-point scanning or single-view imaging's difficulty in identifying wafer tilt and warpage. Furthermore, through cross-validation and fusion calculation of multi-view information, it greatly improves the ability to identify complex abnormal states (such as slight warpage and asymmetric tilt) and the reliability of detection results. In addition, this application uses clear two-dimensional images for edge localization and line fitting, resulting in lower algorithm complexity and faster calculation speed. This effectively resolves the contradiction between detection efficiency and accuracy, meeting the high real-time requirements of industrial environments.

[0084] The embodiments related to this wafer state detection method are embodiments corresponding to the wafer state detection device in any of the above embodiments. The details described in the wafer state detection device in any of the above embodiments are still applicable to this embodiment and will not be repeated here.

[0085] Those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0086] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A wafer condition detection device, characterized in that, The device includes: Wafer box, light source, optical path for folding, imaging module, scanning control module, and processing module; The wafer cassette is used to store the wafer under test, the light source is used to illuminate the wafer under test, the deflection optical path is used to guide the reflected light from the left, central and right regions of the wafer under test to the imaging module, the scanning control module is used to fix the light source, the deflection optical path and the imaging module, and the scanning control module is also used to scan the wafer cassette so that the light source illuminates the next wafer under test in the next slot in the wafer cassette; The processing module is used to determine the number of duplicate wafers based on the pixel distance between the top and bottom edges of the wafer under test and the pixel distance between the top and bottom edges of the standard wafer obtained by the imaging module. The processing module is used to determine the slant angle based on the first, second, and third straight line slopes of the upper or lower edge of the wafer obtained by fitting the left, central, and right region images acquired by the imaging module, respectively. The processing module is used to determine the warpage amount based on the size of the object pixels and the maximum vertical pixel spacing of the upper or lower edge of the wafer obtained from the left, central, and right region images acquired by the imaging module.

2. The detection device according to claim 1, characterized in that, The reflected light from the refracted optical path and the illumination light from the light source form a light plane, which is parallel to the plane of the standard wafer under test.

3. The detection device according to claim 1, characterized in that, The light source is a line light source or a strip light source.

4. The detection device according to claim 1, characterized in that, The optical path includes six right-angle prism reflectors, of which four right-angle prism reflectors are used to guide the reflected light from the left and right regions of the wafer under test and are right-angle prisms with beveled edge reflection, and two right-angle prisms are used to guide the reflected light from the central region of the wafer under test and are right-angle prisms with right-angle edge reflection.

5. The detection device according to claim 2, characterized in that, The imaging module includes a lens and a detector. The lens is used to focus reflected light passing through the deflected optical path, and the detector is used to convert the reflected light into an imaging image.

6. The detection device according to claim 4, characterized in that, The folding optical path is configured such that the left imaging channel for guiding the reflected light from the left side of the wafer under test and the right imaging channel for guiding the reflected light from the right side of the wafer under test are arranged in a symmetrical optical path layout, and the central imaging channel for guiding the reflected light from the central area of ​​the wafer under test is compensated for the optical path difference between the central imaging channel and the left and right imaging channels by optical path folding.

7. The detection device according to claim 6, characterized in that, The number of reflections in the left imaging channel, the right imaging channel, and the central imaging channel are all configured to be an even number.

Images