Chip heat dissipation cover with preattached interface material and package thereof

Abstract

The utility model relates to chip heat dissipation technical field discloses a kind of chip heat dissipation cover of pre-pasted interface material and its package body.The chip heat dissipation cover of pre-pasted interface material includes cover plate, for being set in the top of chip, the end surface of cover plate close to chip is equipped with first cavity and second cavity, first cavity surrounds second cavity, the top surface of second cavity is heat dissipation end surface;Thermal conductive interface layer, be in second cavity, the top end surface of thermal conductive interface layer is closely connected to heat dissipation end surface, its bottom end surface is flush with the top surface of first cavity.The chip heat dissipation cover of pre-pasted interface material effectively solves the problem that the thermal conductive interface layer occurs deviation and causes the " hollow " phenomenon between cover plate and chip in the process of encapsulation of cover plate and chip, to cause the problem of heat resistance increase, heat transfer efficiency reduces.

Description

Technical Field

[0001] This utility model relates to the field of chip heat dissipation technology, specifically to a chip heat dissipation cover with pre-applied interface material and its encapsulation. Background Technology

[0002] With the rapid development of semiconductor technology, the integration level of integrated circuits is constantly increasing. In chip packaging structures, chips are gradually shifting from single chips to multi-chip integration or large-scale monolithic integration. This shift brings higher performance and functional density, but it also poses a more severe challenge to the heat dissipation performance of chips.

[0003] Existing chip heat dissipation structures typically involve encapsulating a heatsink on the chip for heat dissipation. The bottom of the heatsink has a recessed cavity to provide space for the chip during encapsulation, allowing it to be fully contained within the cavity. The bottom perimeter of the heatsink (the edge of the cavity) also allows for a tight seal against the substrate. A thermally conductive interface material is placed between the heatsink and the chip to facilitate rapid heat transfer, reducing thermal resistance and improving heat dissipation efficiency. However, in this existing structure, the thermally conductive interface layer is first placed on the chip, and then the heatsink is placed over it. During the placement and sealing processes, the thermally conductive interface layer is prone to shifting, creating gaps between the chip and the heatsink. This increases thermal resistance and reduces heat transfer efficiency. Furthermore, if the shifted thermally conductive interface material detaches from the circuit board during encapsulation, it can cause a short circuit.

[0004] Therefore, there is an urgent need for a chip heat sink with pre-applied interface material and its package to solve the above problems. Utility Model Content

[0005] Based on the above, the purpose of this utility model is to provide a chip heat dissipation cover with pre-attached interface material and its package, so as to solve the problem in the background art where the thermal interface material of the chip heat dissipation structure shifts during the packaging process, resulting in a large thermal resistance between the chip and the heat dissipation cover.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] This utility model provides a chip heat dissipation cover with pre-applied interface material, comprising:

[0008] A cover plate is used to be placed above the chip. The cover plate has a first cavity and a second cavity on one end face near the chip. The first cavity surrounds the second cavity, and the top surface of the second cavity is a heat dissipation end face.

[0009] A thermally conductive interface layer is disposed in the second cavity, the top surface of the thermally conductive interface layer is tightly connected to the heat dissipation end surface, and its bottom surface is flush with the top surface of the first cavity.

[0010] As an optional technical solution for a chip heat sink with pre-applied interface material, the heat dissipation end face is coated with an adhesive layer, and the thermally conductive interface layer is tightly bonded to the heat dissipation end face through the adhesive layer.

[0011] As an optional technical solution for a chip heat dissipation cover with a pre-attached interface material, the adhesive layer is a nano-silver sintered adhesive, a phase change adhesive, or a superconducting silicone grease.

[0012] As an optional technical solution for a chip heat dissipation cover with pre-attached interface material, the thermally conductive interface layer is indium, and the thickness of the indium is the same as the depth of the second cavity, with a parameter range of 1mm to 3mm.

[0013] As an optional technical solution for a chip heat dissipation cover with pre-attached interface material, the thermally conductive interface layer is graphene, and the thickness of the graphene is the same as the depth of the second cavity, with a parameter range of 0.1mm~0.3mm.

[0014] As an optional technical solution for a chip heat dissipation cover with pre-applied interface material, the cover plate is a copper heat dissipation cover plate.

[0015] As an optional technical solution for a chip heat dissipation cover with pre-applied interface material, the cover plate is a vacuum chamber heat dissipation plate.

[0016] As an optional technical solution for a chip heat dissipation cover with pre-applied interface material, the cover plate is a liquid-cooled heat dissipation cover plate.

[0017] On the other hand, a chip package is provided, including a chip, a substrate, and a chip heat sink with pre-attached interface material as described above. The chip is electrically fixedly connected to the substrate, and the chip heat sink with pre-attached interface material is packaged on the substrate and located above the chip. The side of the thermally conductive interface layer facing away from the heat dissipation end face is tightly attached to the surface of the chip.

[0018] The beneficial effects of this utility model are as follows:

[0019] This utility model provides a chip heat dissipation cover with pre-attached interface material. The chip heat dissipation cover with pre-attached interface material includes: a cover plate for being disposed above the chip, a first cavity and a second cavity being provided on one end face of the cover plate near the chip, the first cavity surrounding the second cavity, and the top surface of the second cavity being a heat dissipation end face; and a thermally conductive interface layer disposed in the second cavity, the top surface of the thermally conductive interface layer being tightly connected to the heat dissipation end face, and its bottom surface being flush with the top surface of the first cavity.

[0020] In the above structure, by setting a first cavity and a second cavity at the bottom of the cover plate, the first cavity provides clearance space during chip packaging, allowing the cover plate to be fully sealed and mounted on the substrate, providing dust protection and protection for the chip. The thermal interface layer is placed in the second cavity, with its bottom surface flush with the top surface of the first cavity. This allows the second cavity to restrict the position of the thermal interface layer, preventing it from shifting during packaging and creating a "void" between the cover plate and the chip, which would increase thermal resistance and reduce heat transfer efficiency. Simultaneously, it also avoids the problem of the thermal interface layer shifting and detaching onto the circuit board, causing a short circuit.

[0021] On the other hand, the chip package provided by this utility model eliminates the need for the installation or placement of a thermally conductive interface layer on the chip during the packaging process of the chip heat sink with pre-attached interface material and the chip and substrate, thereby improving the chip packaging efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the overall structure of the cover plate in Embodiment 1 of this utility model;

[0023] Figure 2 This is a cross-sectional schematic diagram of the cover plate in Embodiment 1 of this utility model;

[0024] Figure 3 This is a cross-sectional schematic diagram of the vacuum cavity heat spreader in Embodiment 1 of this utility model;

[0025] Figure 4 This is a schematic diagram of the overall structure of the liquid cooling heat dissipation cover plate in Embodiment 1 of this utility model;

[0026] Figure 5 This is a schematic diagram of the overall structure of the chip package in Embodiment 2 of this utility model;

[0027] Figure 6 This is an exploded view of the chip package in Embodiment 2 of this utility model;

[0028] Figure 7 This is a cross-sectional schematic diagram of the chip package in Embodiment 2 of this utility model.

[0029] In the picture:

[0030] 1. Cover plate; 10. First cavity; 11. Second cavity;

[0031] 2. Thermally conductive interface layer;

[0032] 3. Vacuum chamber heat spreader; 30. Evaporation end; 31. Condensation end; 32. Evaporation chamber;

[0033] 4. Liquid cooling heat dissipation cover; 40. Top cover; 401. Water inlet; 402. Water outlet; 41. Bottom cover;

[0034] 5. Substrate; 50. Chip; 51. Solder ball. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, not the entire structure.

[0036] In the description of this utility model, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0037] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0038] In the description of this embodiment, terms such as "upper," "lower," "left," and "right" are based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of description and simplification of operation, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0039] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Furthermore, the terms "first" and "second" are used merely for descriptive distinction and have no specific meaning.

[0040] Example 1

[0041] like Figure 1-4As shown, this utility model provides a chip heat dissipation cover with pre-attached interface material. The chip heat dissipation cover with pre-attached interface material includes: a cover plate 1, which is used to be disposed above the chip 50. The cover plate 1 has a first cavity 10 and a second cavity 11 on one end face near the chip 50. The first cavity 10 surrounds the second cavity 11. The top surface of the second cavity 11 is a heat dissipation end face; a thermally conductive interface layer 2 is disposed in the second cavity 11. The top surface of the thermally conductive interface layer 2 is tightly connected to the heat dissipation end face, and its bottom surface is flush with the top surface of the first cavity 10.

[0042] This invention provides a pre-applied interface material chip heat sink cover. A first cavity 10 and a second cavity 11 are provided at the bottom of a cover plate 1. The first cavity 10 provides clearance space for packaging the chip 50, allowing the cover plate 1 to be fully sealed and mounted on the substrate 5, providing dust protection and shielding for the chip 50. A thermally conductive interface layer 2 is disposed within the second cavity 11, with its bottom surface flush with the top surface of the first cavity 10. This allows the second cavity 11 to restrict the position of the thermally conductive interface layer 2, preventing the thermally conductive interface layer 2 from shifting during packaging and creating a "void" between the cover plate 1 and the chip 50, which would increase thermal resistance and reduce heat transfer efficiency. It also prevents the thermally conductive interface layer 2 from shifting and falling onto the circuit board, causing a short circuit. Furthermore, the pre-applied interface material chip heat sink cover eliminates the need for installation or placement of the thermally conductive interface layer 2 during packaging, improving the packaging efficiency of the chip 50.

[0043] In this embodiment, it should be noted that an adhesive layer is applied to the heat dissipation end face to ensure that the thermal interface layer 2 can be tightly attached to the heat dissipation end face, and the enclosure of the second cavity 11 can surround the thermal interface layer 2, so that the cover plate 1 with the thermal interface layer 2 attached will not shift or fall off during transportation and during the packaging process with the chip 50. This avoids the offset part of the thermal interface layer 2 being squeezed around the periphery during the packaging process and falling off onto the circuit board, causing a short circuit. This structure improves the packaging efficiency of the cover plate 1 and the chip 50, and also improves the packaging qualification rate, ensuring that the heat dissipation efficiency and usage stability of the chip 50 are guaranteed.

[0044] Furthermore, since the thermal interface layer 2 and the heat dissipation end face need to have relatively strong adhesion and thermal conductivity, the material of the adhesive layer can be selected as nano-silver sintered adhesive, phase change adhesive, or superconducting silicone grease with high thermal conductivity. In this embodiment, nano-silver sintered adhesive is preferred.

[0045] Specifically, the thermal interface layer 2 is indium, and the thickness of indium is the same as the depth of the second cavity 11. Its parameter range is 1mm to 3mm, preferably 1mm. When the chip 50 inputs 1000W, the actual experimental test shows that when the indium thickness is 1mm, its thermal resistance is 0.05℃ / W and its thermal conductivity is 1000W / MK; when the indium thickness is 2mm, its thermal resistance is 0.08℃ / W and its thermal conductivity is 800W / MK; when the indium thickness is 3mm, its thermal resistance is 0.1℃ / W and its thermal conductivity is 600W / MK. That is to say, the greater the thickness of indium, the higher its thermal resistance, and conversely, the lower the thermal conductivity. When the thickness of indium is less than 1mm, on the one hand, it is not convenient for bonding operations, and on the other hand, if the thickness of indium is too thin, gaps are easily generated between the heat dissipation end face and the chip 50. Therefore, when the thickness of indium is set to 1mm, its thermal resistance and thermal conductivity can achieve the best efficiency, while ensuring a tight fit between the heat dissipation end face, indium and chip 50, thus improving the overall heat dissipation efficiency.

[0046] The depth of the second cavity 11 is the vertical height from the heat dissipation end face to the top face of the first cavity 10.

[0047] In this embodiment, the thermal interface layer 2 can be selected as graphene. The thickness of the graphene is the same as the depth of the second cavity 11, and its parameter range is 0.1mm~0.3mm; preferably 0.1mm. Since the heat transfer efficiency of graphene in the Z direction is lower than that in the X and Y directions, the thickness of graphene should be less than that of indium. When the chip 50 inputs 1000W, the actual experimental test shows that when the graphene thickness is 0.1mm, its thermal resistance is 0.02℃ / W and its thermal conductivity is 5000~10000W / MK; when the graphene thickness is 0.2mm, its thermal resistance is 0.03℃ / W and its thermal conductivity is 2000~5000W. / MK; When the graphene thickness is 0.3mm, its thermal resistance is 0.04℃ / W, and its thermal conductivity is 1000~2000W / MK; that is to say, the greater the thickness of graphene, the higher its thermal resistance, and conversely, the lower the thermal conductivity. When the graphene thickness is less than 0.1mm, on the one hand, it increases the processing difficulty of graphene and is not convenient for bonding operations. On the other hand, if the graphene thickness is too thin, gaps will easily occur between it and the heat dissipation end face and the chip 50. Therefore, when the graphene thickness is set to 0.1mm, its thermal resistance and thermal conductivity can achieve the best efficiency, while ensuring a tight fit between the heat dissipation end face, indium and chip 50, thus improving the overall heat dissipation efficiency.

[0048] In this embodiment, the cover plate 1 can be a traditional copper heat dissipation cover plate. The conventional cover plate 1 should consider both protection and heat conduction efficiency. Therefore, copper can be selected as the heat dissipation cover plate. The first cavity 10 and the second cavity 11 are located at the bottom of the copper heat dissipation cover plate.

[0049] Furthermore, such as Figure 3As shown, in this embodiment, the cover plate 1 can be selected as a vacuum chamber heat exchanger 3 (i.e., a VC heat exchanger). Specifically, the VC heat exchanger has an evaporation end 30, an evaporation chamber 32 (vacuum chamber), and a condensation end 31. The first chamber 10 and the second chamber 11 are located at the bottom of the evaporation end 30. After absorbing heat from the chip 50, the liquid in the evaporation end 30 evaporates and diffuses into the vacuum chamber, conducting the heat to the condensation end 31, which then diffuses to the outside. Subsequently, it condenses back into liquid and returns to the bottom of the evaporation end 30. This evaporation and condensation process, similar to that of a refrigerator or air conditioner, circulates rapidly within the vacuum chamber, significantly improving heat dissipation efficiency.

[0050] Furthermore, such as Figure 4 As shown, in this embodiment, the cover plate 1 can be a liquid cooling heat dissipation cover plate 4. Specifically, the liquid cooling heat dissipation cover plate 4 has a sealed upper cover 40 and a lower cover 41, and a liquid cooling cavity is formed between the upper cover 40 and the lower cover 41. The top of the upper cover 40 is provided with an inlet 401 and an outlet 402. The first cavity 10 and the second cavity 11 are located at the bottom of the lower cover 41. After the lower cover 41 absorbs the heat of the chip 50, it conducts it to the coolant in the liquid cooling cavity. Under the action of an external circulation pump, the coolant forms a fluid cooling circulation system through the inlet 401 and the outlet 402, so that the heat can flow to the outside for diffusion, further improving the heat dissipation efficiency.

[0051] Example 2

[0052] like Figures 5 to 7 As shown, this embodiment provides a chip package, which includes a chip 50, a substrate 5, and a chip heat sink with pre-attached interface material as described in Embodiment 1. The chip 50 is electrically fixed to the substrate 5 by solder balls 51. The chip heat sink with pre-attached interface material is packaged on the substrate 5 and located above the chip 50. The side of the thermally conductive interface layer 2 facing away from the heat dissipation end face is tightly attached to the surface of the chip 50.

[0053] Specifically, the cover plate 1 can be glued together with the substrate 5 by the bottom surface of the first cavity 10 (i.e., the circumferential bottom surface of the cover plate 1), or it can be sealed by screws on the cover plate 1 and threaded onto the substrate 5, or it can be sealed by a snap-fit ​​structure.

[0054] Because the heat sink in the chip package has a thermal interface layer 2 pre-attached inside the second cavity 11 (heat sink end face), the packaging and assembly process of the thermal interface material is eliminated during the packaging of the heat sink and the chip 50, which improves the packaging efficiency. More importantly, the thermal interface layer 2 pre-attached inside the second cavity 11 can be limited by the enclosure of the second cavity 11, so that the thermal interface layer 2 will not shift during the packaging process of the heat sink 1 and the chip 50, ensuring that no "void" phenomenon is formed between the chip 50 and the heat sink, improving the heat dissipation efficiency of the chip 50. At the same time, there is no risk of the thermal interface layer 2 falling off onto the circuit board and causing a short circuit.

[0055] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the present utility model without departing from the scope of the present utility model shall fall within the scope of the present utility model.

Claims

1. A chip heat dissipation cover with pre-applied interface material, characterized in that, include: A cover plate is used to be placed above the chip. The cover plate has a first cavity and a second cavity on one end face near the chip. The first cavity surrounds the second cavity, and the top surface of the second cavity is a heat dissipation end face. A thermally conductive interface layer is disposed in the second cavity, the top surface of the thermally conductive interface layer is tightly connected to the heat dissipation end surface, and its bottom surface is flush with the top surface of the first cavity.

2. The chip heat dissipation cover with pre-applied interface material according to claim 1, characterized in that, The heat dissipation end face is coated with an adhesive layer, and the thermally conductive interface layer is tightly attached to the heat dissipation end face through the adhesive layer.

3. The chip heat dissipation cover with pre-applied interface material according to claim 2, characterized in that, The adhesive layer is a nano-silver sintered adhesive, a phase change adhesive, or a superconducting silicone grease.

4. A chip heat dissipation cover with pre-applied interface material according to claim 3, characterized in that, The thermally conductive interface layer is indium, and the thickness of the indium is the same as the depth of the second cavity, with a parameter range of 1mm to 3mm.

5. A chip heat dissipation cover with pre-applied interface material according to claim 3, characterized in that, The thermally conductive interface layer is graphene, and the thickness of the graphene is the same as the depth of the second cavity, with a parameter range of 0.1mm to 0.3mm.

6. A chip heat dissipation cover with pre-applied interface material according to claim 1, characterized in that, The cover plate is a copper heat dissipation cover plate.

7. A chip heat dissipation cover with pre-applied interface material according to claim 1, characterized in that, The cover plate is a vacuum chamber heat exchange plate.

8. A chip heat dissipation cover with pre-applied interface material according to claim 1, characterized in that, The cover plate is a liquid-cooled heat dissipation cover plate.

9. A chip package comprising a chip, a substrate, and a chip heat sink with pre-attached interface material as described in any one of claims 1-8, characterized in that, The chip is electrically fixedly connected to the substrate, the chip heat sink cover with pre-applied interface material is encapsulated on the substrate and located above the chip, and the side of the thermally conductive interface layer facing away from the heat dissipation end face is tightly attached to the surface of the chip.

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