Power semiconductor package structure

Abstract

The utility model discloses a kind of power semiconductor packaging structures, it is related to power device heat dissipation and electrical interconnection technical field.The packaging structure includes power semiconductor chip, double-sided metallization semi-insulating silicon carbide substrate and radiator.Semi-insulating silicon carbide substrate is composed of upper conductive metal layer, intermediate semi-insulating silicon carbide substrate and lower conductive metal layer;Power semiconductor chip is fixed in upper conductive metal layer by welding layer or sintering layer, and upper and lower metal layer are all composed of sputtering seed layer, electroplated copper layer and barrier / interface layer;Lower conductive metal layer is connected with radiator by welding layer, to form the high-efficiency heat conduction passage from chip to radiator, while maintaining electrical insulation.The packaging structure of the utility model has high insulation, low thermal resistance and good scalability, and is suitable for the packaging and application of high-power density semiconductor devices.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor device technology, and more specifically to a power semiconductor packaging structure. Background Technology

[0002] Power semiconductor packaging is an industrial product that enables power semiconductor chips to be electrically connected to external circuit boards, achieve efficient thermal conductivity with external heat sinks, and provide mechanical and environmental protection for the power semiconductor chips. The main functions of power semiconductor packaging include: establishing stable electrical contact with the chip through solder, sintered silver, or bonding wires, and reliably connecting to the external electrical interface; providing a low thermal resistance connection path to the heat sink or liquid cooling system to effectively conduct the hundreds to thousands of watts of heat generated by the chip during operation; and preventing damage to the chip from environmental factors such as moisture, dust, and corrosive gases, ensuring long-term stable operation.

[0003] Existing power semiconductor packaging structures are diverse, with common types including direct copper-clad (DBC) substrate structures, metal-based insulated metal substrate (IMS) structures, and direct-mount metal-cased structures. For example, some solutions form upper and lower metal layers by plating copper on both sides of a ceramic insulating layer (such as Al2O3 or AlN) to provide electrical connections and heat dissipation pathways; other structures have multiple flexible conductive layers on the substrate surface to reduce thermal cycling stress and improve connection reliability under high-temperature conditions; still other solutions adopt an integrated design of the metal casing and internal heat sink, allowing the heat generated by the device to be conducted to the external cooling system through multiple paths.

[0004] While existing technologies have made some progress in optimizing heat conduction paths, alleviating stress, and improving structural compactness, they still have shortcomings in the following aspects: the limited thermal conductivity of the ceramic substrate leads to higher junction temperatures in high-power-density devices; the mismatch in thermal expansion coefficients between the substrate and the silicon carbide power chip easily causes solder joint fatigue and warping during thermal cycling; insulation performance and high-temperature stability are difficult to optimize simultaneously; and the high thermal resistance of single-sided heat dissipation structures limits further increases in power density. Therefore, it is necessary to propose a double-sided metallized power semiconductor packaging structure based on a semi-insulating silicon carbide substrate to simultaneously achieve high thermal conductivity, high insulation, matching thermal expansion coefficients, and low thermal resistance double-sided heat dissipation, thereby improving the overall performance and reliability of the package. Utility Model Content

[0005] The technical problem to be solved by this utility model is to provide a power semiconductor packaging structure with high thermal conductivity, double-sided heat dissipation and high reliability.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows: A power semiconductor packaging structure, including a power semiconductor chip, a double-sided metallized semi-insulating silicon carbide substrate assembly, and a heat sink; The double-sided metallized semi-insulating silicon carbide substrate assembly includes a middle semi-insulating silicon carbide substrate, with an upper conductive metal layer on the upper surface of the middle semi-insulating silicon carbide substrate and a lower conductive metal layer on the lower surface of the middle semi-insulating silicon carbide substrate; the power semiconductor chip is mounted on the upper conductive metal layer through a solder layer or a sintering layer, and the lower conductive metal layer is fixedly connected to the heat sink through a solder layer or a sintering layer. The semi-insulating silicon carbide substrate serves as an electrical insulating medium and provides a vertical heat conduction path; both the upper and lower conductive metal layers are formed by sputtering seed layers followed by electroplating to form copper layers, and a functional interface layer is formed on the surface.

[0007] As a preferred embodiment, the thickness of the semi-insulating silicon carbide substrate is 0.4 mm to 0.6 mm, and the bulk resistivity of the semi-insulating silicon carbide substrate is greater than or equal to 1 × 10⁻⁶. 8 Ω·cm.

[0008] As a preferred embodiment, the thickness difference between the copper layers of the upper conductive metal layer and the lower conductive metal layer is within ±5% to reduce substrate warping.

[0009] As a preferred embodiment, the semi-insulating silicon carbide substrate assembly is embedded in the interconnect printed circuit board (PCB) and integrally laminated with the PCB dielectric layer and conductive copper layer of the interconnect printed circuit board (PCB). The lower conductive metal layer is directly connected to the heat dissipation copper block or thermal via inside the interconnected printed circuit board (PCB), and the lower conductive metal layer is connected to the heat sink or liquid cooling interface at the edge of the interconnected printed circuit board (PCB) to achieve efficient heat dissipation inside and outside the board.

[0010] As a preferred embodiment, the heat sink is a liquid cooling plate, a copper base plate, or a cooling device with a microchannel structure.

[0011] As a preferred embodiment, the edges of the semi-insulating silicon carbide substrate are provided with a passivation coating or insulating grooves to suppress the risk of surface discharge and breakdown.

[0012] As a preferred embodiment, both the upper and lower conductive metal layers have a first transition metal titanium layer deposited on their surfaces using reactive sputtering; a second copper seed layer is then deposited on the titanium layer; subsequently, a thick copper layer is formed on the copper seed layer through an electroplating process, the thickness of which can be set according to application requirements.

[0013] As a preferred embodiment, the semi-insulating silicon carbide substrate has a thickness of 0.3–1.0 mm, a thermal conductivity greater than or equal to 370 W / m·K, and is subjected to mechanical polishing or chemical mechanical polishing to achieve a surface roughness Ra < 10 nm.

[0014] The beneficial effects of this utility model are: Utilizing a semi-insulating silicon carbide substrate as an integrated insulating and thermally conductive substrate, with a thermal conductivity greater than 370 W / m·K, significantly reduces the device junction temperature. Under the same heat dissipation conditions, using a substrate with a similar area to the device, compared to a substrate with AlN ceramic material, the device junction temperature can be reduced by approximately 7-10 degrees Celsius, and the junction-to-case thermal resistance can be reduced by approximately 55%-65%. The double-sided metallized structure can be directly connected to the chip and heat sink, realizing a double-sided low thermal resistance heat dissipation path, improving power density and current carrying capacity.

[0015] The substrate and silicon carbide chip have matching coefficients of thermal expansion, effectively reducing the impact of thermal expansion on chip connections; the use of a high thermal conductivity isolation substrate effectively reduces the thermal resistance during device operation, thereby optimizing the heat conduction path, reducing solder joint fatigue caused by thermal cycling, and improving long-term reliability; the insulating protection structure reduces the risk of surface breakdown.

[0016] This structure uses semiconductor technology to directly process the substrate, which improves process accuracy and reliability compared to the multi-step processing in traditional packaging. The metallization process and thickness matching design effectively suppress substrate warping, improve packaging flatness and assembly yield.

[0017] It can be used as an embedded substrate for embedded packaging of interconnect printed circuit boards (PCBs), achieving high integration by integral lamination with multilayer interconnect printed circuit boards (PCBs), shortening interconnect paths, reducing parasitic inductance, reducing package height, and optimizing system thermal management; it has a compact structure and light weight, making it suitable for high power density and high frequency operating conditions.

[0018] The SiC metallized copper-clad structure prepared by the above steps exhibits excellent interfacial bonding strength (>20 MPa), low interfacial thermal resistance, and high thermal cycling reliability, making it a viable alternative to traditional DBC substrates in high-power-density SiC modules or thermally conductive insulating substrate packaging. The metallization layers on both the top and bottom sides are prepared using symmetrical deposition and layer-by-layer annealing processes to reduce metallization stress and prevent substrate warping. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a power semiconductor package structure.

[0020] Figure 2 A schematic diagram of the structure of an embedded package for interconnect printed circuit boards (PCBs).

[0021] In the figure: power semiconductor package structure 100, power semiconductor chip 200, double-sided metallized semi-insulating silicon carbide substrate assembly 300, heat sink 400, interconnect printed circuit board 500; Upper conductive metal layer 301, semi-insulating silicon carbide substrate 302, lower conductive metal layer 303; other circuit elements 501, conductive copper layer 502, PCB dielectric layer 503. Detailed Implementation

[0022] The specific implementation scheme of this utility model will now be described in detail with reference to the accompanying drawings.

[0023] like Figure 1-2 As shown, a power semiconductor packaging structure 100 includes a power semiconductor chip 200, a double-sided metallized semi-insulating silicon carbide substrate assembly 300, and a heat sink 400. The double-sided metallized semi-insulating silicon carbide substrate assembly 300 includes a central semi-insulating silicon carbide substrate 302. The edges of the semi-insulating silicon carbide substrate 302 are provided with a passivation coating or insulating grooves to suppress surface discharge and breakdown risks. An upper conductive metal layer 301 is provided on the upper surface of the central semi-insulating silicon carbide substrate 302, and a lower conductive metal layer 303 is provided on the lower surface of the central semi-insulating silicon carbide substrate 302. The power semiconductor chip 200 is mounted on the upper conductive metal layer 301 via a solder layer or a sintering layer, and the lower conductive metal layer 303 is fixedly connected to a heat sink 400 via a solder layer or a sintering layer. The heat sink 400 is a liquid cooling plate, a copper base plate, or a cooling device with a microchannel structure.

[0024] The semi-insulating silicon carbide substrate 302 serves as an electrical insulating medium and provides a vertical heat conduction path; the upper conductive metal layer 301 and the lower conductive metal layer 303 are both formed by sputtering seed layers and then electroplating to form copper layers, and a functional interface layer is formed on the surface.

[0025] The semi-insulating silicon carbide substrate 302 is a semi-insulating 4H-SiC wafer 302, which is selected as a high-purity semi-insulating type or has a high resistivity (≥1×10⁻⁶) obtained through a semi-insulating doping process. 8 Silicon carbide (SiC) substrates with a thickness typically ranging from 0.3 to 1.0 mm and a thermal conductivity greater than or equal to 370 W / m·K are used to simultaneously achieve high-voltage insulation and efficient heat dissipation. The substrates are subjected to mechanical polishing (CMP) or chemical mechanical polishing to achieve a surface roughness Ra < 10 nm.

[0026] Both the upper conductive metal layer 301 and the lower conductive metal layer 303 have a first transition metal titanium layer deposited on their surfaces using reactive sputtering. A second copper seed layer is then deposited on top of the titanium layer. This Ti / Cu bilayer structure simultaneously enhances interface bonding and promotes conductivity expansion, forming a stable metallization seed system. The seed layer is used for nucleation and uniform deposition of the subsequent electroplated copper layer. Subsequently, a thick copper layer is formed on the copper seed layer through electroplating; the thickness of the copper layer can be set according to application requirements.

[0027] The thickness difference of the copper layer between the upper conductive metal layer 301 and the lower conductive metal layer 303 is within ±5% to reduce substrate warping.

[0028] The semi-insulating silicon carbide substrate assembly 300 is embedded in the interconnect printed circuit board PCB 500 and is integrally pressed with the PCB dielectric layer 503 and conductive copper layer 502 of the interconnect printed circuit board PCB 500. The lower conductive metal layer 303 is directly connected to the heat dissipation copper block or thermal via inside the interconnect printed circuit board 500, and the lower conductive metal layer 303 is connected to the heat sink 400 or liquid cooling interface at the edge of the interconnect printed circuit board 500 to achieve efficient heat dissipation inside and outside the board.

[0029] Thus, the heat generated by the power semiconductor chip 200 is conducted to the external cooling system through a continuous thermal path of "power semiconductor chip 200 → chip solder or sintering layer → upper conductive metal layer 301 → semi-insulating silicon carbide substrate 302 → lower conductive metal layer 303 → heat sink 400".

[0030] In terms of electrical performance, the semi-insulating silicon carbide substrate 302 provides insulation between the upper conductive metal layers, with a withstand voltage of up to several kilovolts, ensuring electrical safety between the chip electrodes and the heat sink. Passivation coatings or insulating grooves can be further provided at the substrate edges to suppress the risk of surface discharge and breakdown.

[0031] In terms of reliability, the semi-insulating silicon carbide substrate 302 and the chip 200 have a high degree of matching in terms of thermal expansion coefficients (approximately 4.0 × 10⁻ ... 6 ( / K), which can effectively reduce solder joint stress and substrate warpage during temperature cycling from room temperature to +150°C, and improve long-term working stability.

[0032] Therefore, this embodiment achieves efficient thermal connection between the chip and the heat sink using a high-purity semi-insulating silicon carbide substrate, combining high insulation with low thermal resistance, making it suitable for power modules operating in high power density and high-temperature environments. It is applicable to high-power density converters, automotive OBCs, drive inverters, and other application scenarios. Through the interconnected printed circuit board (PCB) embedded packaging structure, the device package height is reduced by approximately 30%, parasitic inductance is reduced by over 40%, and thermal resistance is reduced by approximately 25% compared to traditional single-sided heat dissipation packaging.

[0033] This structure is applicable to power semiconductors with vertical structures (such as SiC MOSFETs) and can also be extended to other types of power devices, such as devices with lateral structures.

[0034] The above embodiments are merely illustrative of the principles and effects of the present invention, as well as some examples of its application, and are not intended to limit the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements are all within the protection scope of the present invention.

Claims

1. A power semiconductor packaging structure (100), comprising a power semiconductor chip (200), a double-sided metallized semi-insulating silicon carbide substrate assembly (300), and a heat sink (400); characterized in that: The double-sided metallized semi-insulating silicon carbide substrate assembly (300) includes a middle semi-insulating silicon carbide substrate (302), with an upper conductive metal layer (301) on the upper surface of the middle semi-insulating silicon carbide substrate (302) and a lower conductive metal layer (303) on the lower surface of the middle semi-insulating silicon carbide substrate (302); the power semiconductor chip (200) is mounted on the upper conductive metal layer (301) through a solder layer or a sintering layer, and the lower conductive metal layer (303) is fixedly connected to the heat sink (400) through a solder layer or a sintering layer. The semi-insulating silicon carbide substrate (302) serves as an electrical insulating medium and provides a vertical heat conduction path; the upper conductive metal layer (301) and the lower conductive metal layer (303) are both formed by sputtering seed layers and then electroplating to form copper layers, and a functional interface layer is formed on the surface.

2. The power semiconductor packaging structure (100) as described in claim 1, characterized in that: The thickness of the semi-insulating silicon carbide substrate (302) is 0.4 mm to 0.6 mm, and the bulk resistivity of the semi-insulating silicon carbide substrate (302) is greater than or equal to 1 × 10⁻⁶. 8 Ω·cm.

3. The power semiconductor packaging structure as described in claim 1, characterized in that: The difference in copper layer thickness between the upper conductive metal layer (301) and the lower conductive metal layer (303) is within ±5% to reduce substrate warping.

4. The power semiconductor packaging structure as described in claim 1, characterized in that: The semi-insulating silicon carbide substrate assembly (300) is embedded in the interconnect printed circuit board (PCB) (500) and is integrally pressed with the PCB dielectric layer (503) and conductive copper layer (502) of the interconnect printed circuit board (PCB) (500); The lower conductive metal layer (303) is directly connected to the heat dissipation copper block or thermal via inside the interconnect printed circuit board (PCB) (500), and the lower conductive metal layer (303) is connected to the heat sink (400) or liquid cooling interface at the edge of the interconnect printed circuit board (PCB) to achieve efficient heat dissipation inside and outside the board.

5. The power semiconductor packaging structure (100) as described in claim 1, characterized in that: The radiator (400) is a liquid cooling plate, a copper base plate, or a cooling device with a microchannel structure.

6. The power semiconductor packaging structure (100) as described in claim 1, characterized in that: The edges of the semi-insulating silicon carbide substrate (302) are provided with a passivation coating or insulating grooves to suppress the risk of surface discharge and breakdown.

7. The power semiconductor package structure (100) as described in claim 1, characterized in that: Both the upper conductive metal layer (301) and the lower conductive metal layer (303) have a first transition metal titanium layer deposited on their surfaces by reactive sputtering. A second copper seed layer is then deposited on the titanium layer. Subsequently, a thick copper layer is formed on the copper seed layer by electroplating. The thickness of the copper layer can be set according to the application requirements.

8. The power semiconductor package structure (100) as described in claim 1, characterized in that: The semi-insulating silicon carbide substrate (302) has a thickness of 0.3–1.0 mm, a thermal conductivity greater than or equal to 370 W / m·K, and is mechanically polished or chemically mechanically ground to achieve a surface roughness Ra < 10 nm.

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