Power module and device

Abstract

A power module and a device, the power module comprising a plurality of power chips, a conductive block, oppositely arranged upper and lower substrates, the inner surfaces of the upper and lower substrates being provided with conductive areas, the plurality of power chips and the conductive block being arranged between the upper and lower substrates, the lower surface of the power chip being electrically connected with the conductive area of at least one substrate, the conductive block being arranged between the power chip and the other substrate, the lower surface of the conductive block being electrically connected with the upper surface of the plurality of power chips, the upper surface of the conductive block being electrically connected with the conductive area of the other substrate, the cross section of the conductive block being gradually increased along the direction from the lower surface to the upper surface of the conductive block. In the above embodiment, by designing the conductive block to be large in cross section downward and small upward, the heat flow path is gradually widened in the vertical direction, forming a "thermal gradient guide channel", and achieving symmetrical diffusion of heat to the upper and lower substrates.

Description

Technical Field

[0001] This application relates to the field of electronic power technology, and in particular to power modules and devices. Background Technology

[0002] In related technologies, the heat dissipation capacity of existing power modules is insufficient, which has seriously affected the working performance of power modules. Therefore, how to improve the heat dissipation capacity of power modules has become an increasingly urgent technical problem. Summary of the Invention

[0003] The power module and device provided in this application address at least part of the aforementioned problems. A first aspect of this application provides a power module comprising a plurality of power chips, a conductive block, and an upper substrate and a lower substrate disposed opposite to each other. Conductive regions are provided on the inner surfaces of the upper substrate and the lower substrate. The plurality of power chips and the conductive block are disposed between the upper substrate and the lower substrate. The lower surface of each power chip is electrically connected to a conductive region of at least one substrate. The conductive block is disposed between the power chip and another substrate. The lower surface of the conductive block is electrically connected to the upper surfaces of the plurality of power chips. The upper surface of the conductive block is electrically connected to a conductive region of another substrate. Along the direction from the lower surface to the upper surface of the conductive block, the cross-section of the conductive block continuously increases.

[0004] Optionally, the width of the conductive block gradually increases along the direction from the lower surface to the upper surface of the conductive block.

[0005] Optionally, the conductive block is provided with a groove, and the gap between the groove and the power chip is disposed opposite to each other.

[0006] Optionally, the angle between the width edge of the conductive block and the vertical direction of the conductive block is in the range of 20 degrees to 50 degrees.

[0007] Optionally, the angle between the width edge of the conductive block and the vertical direction of the conductive block is determined according to the following formula:

[0008]

[0009] Where α is the angle between the width edge of the conductive block and the vertical direction of the conductive block, Ka is the thermal conductivity of the power chip, and Kb is the thermal conductivity of the conductive block.

[0010] Optionally, power chips are respectively disposed on the conductive areas of the upper substrate and the lower substrate. The conductive block includes a first conductive block and a second conductive block. The first conductive block is disposed between the upper substrate and the power chip disposed on the lower substrate, so that the upper surface of the power chip on the lower substrate is electrically connected to the conductive area of ​​the upper substrate. The second conductive block is disposed between the lower substrate and the power chip disposed on the upper substrate, so that the upper surface of the power chip on the upper substrate is electrically connected to the conductive area of ​​the lower substrate.

[0011] Optionally, the conductive region includes a positive conductive region, an AC conductive region, and a negative conductive region; the plurality of power chips includes an upper bridge power chip and a lower bridge power chip; the upper bridge power chip is disposed in the positive conductive region, and the lower bridge power chip is disposed in the AC conductive region; the AC conductive region and at least a portion of the negative conductive region are disposed on the upper substrate, and the positive conductive region and at least a portion of the negative conductive region are disposed on the lower substrate; or, the AC conductive region and at least a portion of the negative conductive region are disposed on the lower substrate, and the positive conductive region and at least a portion of the negative conductive region are disposed on the upper substrate.

[0012] Optionally, the power module further includes a positive power terminal and a negative power terminal; the positive power terminal is electrically connected to the positive conductive area, the negative power terminal is electrically connected to the negative conductive area, and the positive power terminal and the negative power terminal are stacked.

[0013] Optionally, the power module further includes a third conductive block disposed between the upper substrate and the lower substrate to electrically connect the negative conductive areas disposed on the different substrates.

[0014] Optionally, the power module further includes an AC power terminal, which is electrically connected to the AC conductive area.

[0015] An apparatus comprising a power module as described in any of the preceding claims.

[0016] This application designs the conductive block with a cross-section that is larger at the top and smaller at the bottom, so that the heat flow path gradually widens in the vertical direction, forming a "thermal gradient guiding channel". This effectively avoids the local accumulation of heat directly above the chip and achieves symmetrical diffusion of heat to the upper and lower substrates.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a schematic diagram of the structure of the upper substrate of a power module provided in an exemplary embodiment of this disclosure;

[0021] Figure 2 This is a planar schematic diagram of the upper substrate of a power module provided in an exemplary embodiment of this disclosure;

[0022] Figure 3 This is a schematic diagram of the structure of the lower substrate of a power module provided in an exemplary embodiment of this disclosure;

[0023] Figure 4 This is a planar schematic diagram of the lower substrate of a power module provided in an exemplary embodiment of this disclosure;

[0024] Figure 5 This is a schematic diagram of the structure of a conductive block of a power module provided in an exemplary embodiment of this disclosure;

[0025] Figure 6 This is a schematic diagram of heat dissipation of a conductive block of a power module provided in an exemplary embodiment of this disclosure;

[0026] Figure 7 This is a schematic diagram of the structure of a power module provided in an exemplary embodiment of this disclosure;

[0027] Figure 8 This is a current diagram of a power module provided in an exemplary embodiment of this disclosure;

[0028] Figure 9 This is a cross-sectional schematic diagram of a power module provided in an exemplary embodiment of this disclosure;

[0029] Figure 10 This is a schematic diagram of the structure of a power module provided in an exemplary embodiment of this disclosure.

[0030] Figure label:

[0031] 1. Positive power terminal; 2. Negative power terminal; 3. AC power terminal; 4. Upper bridge gate drive terminal; 5. Upper bridge source drive terminal; 6. Lower bridge gate drive terminal; 7. Lower bridge source drive terminal; 8. First thermistor resistance monitoring terminal; 9. Second thermistor resistance monitoring terminal; 11. Part of the positive conductive region; 12. Third conductive block; 13. Part of the negative conductive region; 14. First conductive block; 15. Another part of the positive conductive region; 16. Upper bridge power chip; 17. First gate conductive region; 18. First source conductive region; 19. Thermistor conductive region; 20. Thermistor; 21. Another part of the negative conductive region; 22. AC conductive region; 23. Second conductive block; 24. Second source conductive region; 25. Second gate conductive region; 26. Lower bridge power chip; 101. Peripheral first metal layer; 201. Peripheral second metal layer; 102. First insulating layer; 202. Second insulating layer. Detailed Implementation

[0032] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0033] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, features defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] This application provides a power module, such as... Figures 1 to 10 As shown, the power module includes multiple power chips 16 (26), conductive blocks 14 (23), an upper substrate 100 and a lower substrate 200 disposed opposite to each other. Conductive areas 11 (or 13, 15, 17, 18, 19, 21, 22, 24, 25) are provided on the inner surfaces of the upper substrate 100 and the lower substrate 200. Multiple power chips 16 (26) and conductive blocks 14 (23) are disposed between the upper substrate 100 and the lower substrate 200. The lower surface of the power chip 16 (26) is connected to at least one conductive block of the substrate. Electrically connected areas, conductive block 14 (23) is disposed between power chip 16 (26) and another substrate, the lower surface of conductive block 14 (23) is electrically connected to the upper surface of multiple power chips 16 (26), and the upper surface of conductive block 14 (23) is electrically connected to the conductive area of ​​another substrate, so that the upper surface of power chip 16 (26) is electrically connected to the conductive area of ​​another substrate, wherein the cross-section of conductive block 14 (23) continuously increases along the direction from the lower surface to the upper surface of the conductive block 14 (23).

[0036] In the above embodiments, by designing the conductive block with a cross-section that is larger at the top and smaller at the bottom, the heat flow path gradually widens vertically as heat is conducted from the high thermal conductivity silicon carbide power chip (Ka=330 W / mK) to the conductive block (Kb=350–393 W / mK), forming a "thermal gradient guiding channel." This effectively avoids localized heat accumulation directly above the chip, achieving symmetrical heat diffusion to the upper and lower substrates. During the bonding process, this structure ensures uniform pressure distribution across the entire chip surface, significantly reducing the risk of chip breakage or sintering layer cracking caused by localized stress concentration. Experimental results show that, compared to traditional uniform cross-section conductive blocks, this structure reduces chip junction temperature by more than 15%, thermal resistance by approximately 22%, and module lifespan by more than 30%.

[0037] In some embodiments, the width of the conductive block 14 (23) gradually increases along the direction from the lower surface to the upper surface. This design ensures a uniform transition of heat flow in the vertical direction by designing the sidewalls of the conductive block 14 (23) as a continuously expanding inclined structure, avoiding interface cracks caused by stress concentration in traditional right-angle structures during thermal cycling. The conductive block is manufactured using a powder metallurgy integral molding process, avoiding interface defects caused by multi-layer stacking, achieving a sintering density of over 99.5%, ensuring structural integrity. During the pressing process, this expanding structure allows pressure to be smoothly transmitted from the chip edge to the center, promoting densification of the nano-silver sintered layer throughout the entire area, with a sintering porosity of less than 1.5%, significantly improving the reliability of the electro-thermal connection.

[0038] In some embodiments, see Figure 1 , Figure 3The conductive block 14 (23) is provided with a groove, and the gap between the groove and the power chip is set opposite to each other. In this scheme, multiple U-shaped grooves are provided on the lower surface of the conductive block. The depth of the groove is 1 / 3 to 2 / 3 of the thickness of the conductive block, and the width is slightly larger than the gap between adjacent chips. The groove forms a local stress relief zone during the pressing process, avoiding excessive stress on the chip edge due to the rigid transmission of the conductive block, which may cause it to break. In addition, the groove can be filled with a low-modulus thermally conductive adhesive with a thermal conductivity ≥5 W / mK to compensate for manufacturing tolerances and enhance thermal coupling. During thermal cycling, this structure allows for a small relative displacement between the conductive block and the chip, absorbing the shear stress caused by the difference in thermal expansion coefficients, reducing the risk of interface fatigue failure by more than 60%, and improving the reliability of the module to more than 100,000 cycles under temperature cycling from -40℃ to 175℃. In some embodiments, the cross-section of the groove increases continuously along the direction from the lower surface to the upper surface of the conductive block, or the width of the groove gradually increases. The specific design depends on the product design and is not limited here.

[0039] In some embodiments, the angle between the width edge of the conductive block and its vertical direction ranges from 20 degrees to 50 degrees. This angle range has been verified as optimal through thermo-mechanical coupled finite element simulation: when the angle α < 20°, the heat diffusion path is too narrow, heat cannot effectively spread laterally, and the chip edge temperature rise remains high; when α > 50°, the structural strength of the conductive block decreases, and plastic deformation or fracture is prone to occur during the pressing process. In a preferred embodiment, α = 42°, which corresponds to a material combination of Ka = 330 W / mK and Kb = 393 W / mK, minimizing thermal resistance. In actual manufacturing, this angle is formed in one step using a precision mold to ensure batch consistency. See also Figure 7 In the double-sided heat dissipation architecture, this angle setting allows heat flow to diffuse symmetrically from the center of the chip on the upper and lower substrates to the two substrates, forming a "dual-path heat conduction channel," and the chip temperature difference is controlled within ±5℃. In some embodiments, when the conductive block 14 (23) is provided with a groove that is positioned opposite to the gap of the power chip, the width edge of the conductive block 14 (23) can also be the edge of the groove. Therefore, the angle between the conductive block and the vertical direction can also be the angle between the edge of the groove and the vertical direction, and the setting range of this angle can also be 20 degrees to 50 degrees.

[0040] In some embodiments, the angle between the width edge of the conductive block 14 (23) and the vertical direction of the conductive block is determined according to the following formula:

[0041]

[0042] Where α is the angle between the width edge of the conductive block and the perpendicular direction of the conductive block, and K a K represents the thermal conductivity of the power chip. bLet α be the thermal conductivity of the conductive block. This formula is derived based on the principle of heat flow continuity and, analogous to Snell's law in optics, when heat flows from a high thermal conductivity material Ka to a low thermal conductivity material Kb, the angle between the heat flow direction and the interface normal should satisfy tanα = Ka / Kb to minimize interfacial thermal resistance. This scheme uses a copper-molybdenum alloy as the conductive block material. Its thermal conductivity Kb can be precisely controlled by adjusting the molybdenum content (5%–20% wt%) within a gradient range of 350–393 W / mK, allowing Kb to precisely match Ka (330 W / mK), thereby stably controlling α at 40°–45°. When replacing with an aluminum nitride ceramic substrate (Ka = 180 W / mK), Kb can be adjusted to 170–200 W / mK, adjusting α to 47°–50°, achieving a universal design across material platforms and ensuring optimal heat diffusion efficiency in different systems. In some embodiments, when the conductive block 14 (23) is provided with a groove that is positioned opposite to the gap of the power chip 16 (26), the width edge of the conductive block 14 (23) can also be the edge of the groove. Therefore, the angle between the conductive block and the vertical direction can also be the angle between the edge of the groove and the vertical direction. The range of this angle can also be determined by the above formula.

[0043] In some embodiments, see Figures 1 to 8 Power chips are respectively disposed on the conductive areas of the upper and lower substrates. The conductive blocks include a first conductive block 14 and a second conductive block 23. The first conductive block 14 is disposed between the upper substrate 100 and the power chip 26 disposed on the lower substrate 200, so that the upper surface of the power chip 26 on the lower substrate is electrically connected to the conductive area of ​​the upper substrate 100. The second conductive block 23 is disposed between the lower substrate 200 and the power chip 16 disposed on the upper substrate, so that the upper surface of the power chip 16 on the upper substrate is electrically connected to the conductive area of ​​the lower substrate 200. This scheme adopts a symmetrical arrangement structure of dual conductive blocks. The first conductive block connects the power chip on the lower substrate to the conductive area of ​​the upper substrate, and the second conductive block connects the power chip on the upper substrate to the conductive area of ​​the lower substrate, forming a true double-sided fully symmetrical heat dissipation and conductive path. Each power chip achieves heat dissipation on both the upper and lower sides, reducing thermal resistance by more than 40%, and the heat flow distribution on the upper and lower substrates is balanced, avoiding heat accumulation on one side. A nano-silver sintered layer (thickness ≤20μm, sintering temperature 250℃) is used between the conductive block and the chip, with a contact resistance <0.5 mΩ·cm², ensuring low thermal resistance and high reliability. This symmetrical structure ensures symmetrical parasitic inductance paths in the upper and lower bridge arms during high-frequency switching, effectively suppressing common-mode noise and improving EMC performance.

[0044] In some embodiments, see Figures 1 to 4The conductive areas include positive conductive areas 15 and 11, an AC conductive area 22, and negative conductive areas 13 and 21. Multiple power chips include an upper-bridge power chip 16 and a lower-bridge power chip 26. The upper-bridge power chip 16 is disposed in the positive conductive area 15, and the lower-bridge power chip 26 is disposed in the AC conductive area 22. The AC conductive area 22 and at least a portion of the negative conductive area 21 are disposed on the lower substrate 200, and the positive conductive area 15 and at least a portion of the negative conductive area 13 are disposed on the upper substrate 100. Alternatively, the AC conductive area 22 and at least a portion of the negative conductive area 21 are disposed on the upper substrate 100, and the positive conductive area 15 and at least a portion of the negative conductive area 13 are disposed on the lower substrate 200. When the power module is operating, the current path can be found in [reference needed]. Figure 8 This design does not impose specific limitations. It achieves a staggered distribution of positive, AC, and negative regions on the upper and lower substrates, forming a "staggered" electrical layout. For example, the upper substrate houses the AC conductive region and part of the negative conductive region, while the lower substrate houses the positive conductive region and the remaining negative conductive region, spatially separating the positive and negative current paths and reducing loop area. This layout, combined with a dual-conductor block structure, allows the current from the upper bridge chip to flow from the positive conductive region of the lower substrate through the first conductive block to the AC conductive region, and the current from the lower bridge chip to flow from the AC conductive region of the upper substrate through the second conductive block to the negative conductive region of the lower substrate, forming a "Z"-shaped current loop and significantly reducing loop inductance. At switching frequencies above 100kHz, voltage overshoot is reduced by more than 30%, and electromagnetic interference is reduced by 40%. The negative conductive region is separated on the upper and lower substrates, shunting the current, reducing single-point current density, and improving the lifetime of the conductive region.

[0045] In some embodiments, see Figures 1 to 10 The power module also includes a positive power terminal 1 and a negative power terminal 2. The positive power terminal 1 is electrically connected to the positive conductive area 15, and the negative power terminal 2 is electrically connected to the negative conductive area 21. The positive power terminal 1 and the negative power terminal 2 are stacked. The stacked arrangement of the positive and negative power terminals, with opposite current flows, utilizes a magnetic field to partially cancel out mutual inductance, effectively reducing parasitic inductance. The positive / negative power terminals are interconnected with the capacitor terminals using laser welding, further reducing parasitic parameters and improving reliability. In this design, the positive and negative power terminals can employ a copper alloy stacked structure, with a 50μm thick polyimide insulating film separating the positive and negative terminals to form a parallel plate capacitor structure for filtering high-frequency noise. The terminals are connected to the conductive areas via laser welding, with a weld width ≥0.8mm, resistance <0.3 mΩ, and high mechanical strength. The stacked design reverses the directions of positive and negative currents. According to Ampere's law, the resulting magnetic field partially cancels out in space, reducing the overall parasitic inductance of the module to below 5nH, far superior to traditional planar terminal structures (>15nH). U-shaped slots are provided at the terminal edges, with a depth of 1 / 4 of the terminal thickness and a width of 1.5mm, to release heat generated during thermal cycling due to the copper terminals (CTE=17×10⁻⁻⁴). 6 / K) and ceramic substrate (CTE=6×10⁻ 6 The shear stress generated by the difference in temperature ( / K) prevents fatigue cracking of the weld joint. After 1000 thermal cycles, no crack propagation occurred in the weld joint, and the weld integrity remained at 100%.

[0046] In some embodiments, see Figures 1 to 4 The power module also includes a third conductive block 12, which is disposed between the upper substrate 100 and the lower substrate 200 to electrically connect the negative electrode conductive areas 13 and 21 disposed on the different substrates. This design can use a rectangular copper-molybdenum alloy block as the third conductive block, with its upper and lower surfaces connected to the negative electrode conductive areas on the upper and lower substrates respectively through a nano-silver sintering layer, forming a low-resistance, high-reliability shared negative electrode path. This structure allows the negative electrode currents of the upper and lower substrates to converge at the center of the module, avoiding current concentration in the edge areas and reducing local temperature rise. The width of the third conductive block matches the spacing between the positive and AC conductive areas, and its sidewalls also adopt a 20°–50° tilt angle design to achieve the same thermal diffusion characteristics as the main conductive block. Under high current conditions (>100A), the negative electrode current distribution is uniform, and the temperature rise difference is less than 3°C, significantly improving the module's power density. Simultaneously, the third conductive block serves as a structural support, enhancing the mechanical rigidity of the upper and lower substrates, suppressing pressure deformation, and improving overall packaging reliability.

[0047] In some embodiments, see Figures 1 to 10 The power module also includes an AC power terminal 3, which is electrically connected to the AC conductive area 22. In this application, the terminal and conductive area can employ a double-sided ultrasonic welding structure. The bottom of the terminal is welded to the AC conductive area of ​​the upper or lower substrate, and the top extends outwards from the module, forming a low-inductance lead-out structure. The terminal body is a thin copper alloy sheet, 0.5 mm thick, with a width matching the AC conductive area, and wavy bends at the edges to absorb thermal expansion stress. The welding of the terminal and conductive area uses ultrasonic welding (frequency 40 kHz, amplitude 30 μm, pressure 0.3 MPa), with a weld layer thickness ≤ 10 μm and resistance ≤ 0.2 mΩ. This structure, combined with a Kelvin connection design, makes the drive signal line independent of the power path, reducing the common source inductance to below 1.2 nH, significantly improving gate drive stability and reducing switching oscillations. Under high-frequency (>50 kHz) operation, the gate drive voltage overshoot is less than 10 V, ensuring safe turn-off of the SiC MOSFET.

[0048] The power module of this application also includes a thermistor 20 and signal terminals 8 (9, 5, 4, 6, 7). The upper-bridge power chip 16 and the lower-bridge power chip 23 are respectively disposed on the upper and lower substrates, effectively solving the problem of uneven thermal resistance on the upper and lower sides of the double-sided heat dissipation power module. The stacked design of the positive and negative power terminals, with the current flowing in opposite directions on the upper and lower layers, utilizes mutual inductance to offset some parasitic inductance, reducing voltage stress on the device in high-frequency scenarios and improving reliability and application voltage. The power chips are electrically connected through an integrated conductive block, which disperses the heat generated by the chips, ensures uniform stress on the chips during interface connection, and improves production efficiency. Furthermore, the tilt angle design of the conductive block facilitates heat diffusion, improving heat dissipation efficiency and overall heat dissipation effect. Compared with existing double-sided heat dissipation structures, the embodiments proposed in this invention can effectively improve the switching performance and heat dissipation effect of the power module.

[0049] In some embodiments, see Figures 1 to 10 The drain region on the lower surface of the lower bridge power chip 16 is connected to the positive conductive region 15 via nano-silver / nano-copper sintering technology. The source region on the upper surface of the upper bridge power chip 16 is connected to the lower surface of the first conductive block 14 via nano-silver / nano-copper sintering technology. The gate sampling region on the upper surface of the upper bridge power chip 16 is connected to the first gate conductive region 17 via wire bonding. The source sampling region on the upper surface of the upper bridge power chip 16 is connected to the first source conductive region 18 via wire bonding. In addition, the upper bridge gate driving terminal 4 is connected to the first gate conductive region 17 via ultrasonic welding, and the upper bridge source driving terminal 5 is connected to the first source conductive region 18 via ultrasonic welding to achieve Kelvin connection, reduce common source inductance, thereby reducing the influence of the power circuit on the driving circuit and improving the stability of the driving signal. In addition, the upper surface of the first conductive block 14 is electrically connected to the AC conductive area 22 through nano-silver / nano-copper sintering technology; the positive power terminal 1 is connected to the positive conductive area 15 through ultrasonic welding; in addition, the thermistor 20 and temperature sampling terminals 8 and 9 are welded to the surface of the thermistor conductive area 19 for monitoring the operating temperature of the power module.

[0050] See Figures 1 to 10The drain region on the lower surface of the lower-bridge power chip 26 is connected to the AC conductive region 22 via nano-silver / nano-copper sintering technology, and the source region on the upper surface of the lower-bridge power chip 26 is connected to the second conductive block 23 via nano-silver / nano-copper sintering technology. The gate sampling region on the upper surface of the lower-bridge power chip 26 is connected to the second gate conductive region 25 via wire bonding, and the source sampling region on the upper surface of the lower-bridge power chip 26 is connected to the second source conductive region 24 via wire bonding. The lower-bridge gate driving terminal 6 is connected to the second gate conductive region 25 via ultrasonic welding, and the lower-bridge source driving terminal 7 is connected to the second source conductive region 24 via ultrasonic welding to achieve Kelvin connection, reduce common source inductance, thereby reducing the influence of the power circuit on the driving circuit and improving the stability of the driving signal. The negative power terminal 2 is connected to a portion of the negative conductive region 21 disposed on the lower substrate via ultrasonic welding.

[0051] After the semi-finished upper / lower substrates are processed, using the lower substrate as a reference, the first conductive block 14 of the lower substrate is connected to the AC conductive area 22 of the upper substrate, the third conductive block 12 of the lower substrate is connected to the negative conductive area 21 of the upper substrate, and the negative conductive area 13 of the lower substrate is connected to the second conductive block 23 of the upper substrate. The interface connection is achieved using nano-silver sintering or nano-copper sintering. After sintering, insulating material can be filled inside the upper and lower substrates through a mold transfer process to achieve electrical insulation. The insulating material can be silicone gel or epoxy resin. (See also...) Figure 9 , Figure 10 The upper and lower substrates may further include a first insulating layer 102 and a second insulating layer 202, which may be made of Si3N4, AlN, ZTA, or Al2O3. The outer surfaces of the upper and lower substrates may also be provided with an external first metal layer 101 and an external second metal layer 201, which are the exposed surfaces of the opposing substrates. Furthermore, the conductive layer material described in this application is pure copper or pure aluminum.

[0052] This application also provides a device comprising a power module as described in any of the foregoing embodiments. In the application of main drive inverters for new energy vehicles, this power module is integrated into the electronic control unit, operates at 1200V / 400A, and, with the help of a liquid cooling system, the module junction temperature is stabilized below 125℃, improving system efficiency by 1.8%. In photovoltaic inverters, the module supports a 1500V DC bus voltage and a switching frequency of up to 30kHz. Due to its low parasitic inductance, no additional buffer circuit is required, reducing the system size by 25%. In industrial drives, the module can operate continuously in a high-temperature environment of 175℃, with an MTBF exceeding 150,000 hours, meeting the IEC 61800-5-1 standard. The module's double-sided heat dissipation, low parasitic inductance, and high-reliability structure make it a core component of high-power-density, high-efficiency, and high-reliability power electronic systems.

[0053] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0054] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A power module, characterized in that, The power module includes multiple power chips, a conductive block, and an upper substrate and a lower substrate disposed opposite to each other. The inner surfaces of the upper substrate and the lower substrate are provided with conductive areas. The multiple power chips and the conductive block are disposed between the upper substrate and the lower substrate. The lower surface of the power chip is electrically connected to the conductive area of ​​at least one substrate. The conductive block is disposed between the power chip and another substrate. The lower surface of the conductive block is electrically connected to the upper surface of the multiple power chips. The upper surface of the conductive block is electrically connected to the conductive area of ​​another substrate. The cross-section of the conductive block continuously increases along the direction from the lower surface to the upper surface.

2. The power module according to claim 1, characterized in that, The width of the conductive block gradually increases along the direction from the lower surface to the upper surface.

3. The power module according to claim 1, characterized in that, The conductive block is provided with a groove, and the gap between the groove and the power chip is arranged opposite to each other.

4. The power module according to any one of claims 1 to 3, characterized in that, The angle between the width edge of the conductive block and the vertical direction of the conductive block is in the range of 20 degrees to 50 degrees.

5. The power module according to any one of claims 1 to 3, characterized in that, The angle between the width edge of the conductive block and the vertical direction of the conductive block is determined according to the following formula: Where α is the angle between the width edge of the conductive block and the perpendicular direction of the conductive block, and K a K represents the thermal conductivity of the power chip. b is the thermal conductivity of the conductive block.

6. The power module according to claim 1, characterized in that, Power chips are respectively disposed on the conductive areas of the upper substrate and the lower substrate. The conductive block includes a first conductive block and a second conductive block. The first conductive block is disposed between the upper substrate and the power chip disposed on the lower substrate, so that the upper surface of the power chip on the lower substrate is electrically connected to the conductive area of ​​the upper substrate. The second conductive block is disposed between the lower substrate and the power chip disposed on the upper substrate, so that the upper surface of the power chip on the upper substrate is electrically connected to the conductive area of ​​the lower substrate.

7. The power module according to claim 6, characterized in that, The conductive region includes a positive conductive region, an AC conductive region, and a negative conductive region. The plurality of power chips include an upper bridge power chip and a lower bridge power chip. The upper bridge power chip is disposed in the positive conductive region, and the lower bridge power chip is disposed in the AC conductive region. The AC conductive region and at least a portion of the negative conductive region are disposed on the upper substrate, and the positive conductive region and at least a portion of the negative conductive region are disposed on the lower substrate. Alternatively, the AC conductive region and at least a portion of the negative conductive region are disposed on the lower substrate, and the positive conductive region and at least a portion of the negative conductive region are disposed on the upper substrate.

8. The power module according to claim 7, characterized in that, The power module further includes a positive power terminal and a negative power terminal; the positive power terminal is electrically connected to the positive conductive area, and the negative power terminal is electrically connected to the negative conductive area, and the positive power terminal and the negative power terminal are stacked.

9. The power module according to claim 7, characterized in that, The power module further includes a third conductive block disposed between the upper substrate and the lower substrate to electrically connect the negative conductive areas disposed on the different substrates.

10. The power module according to claim 7, characterized in that, The power module also includes an AC power terminal, which is electrically connected to the AC conductive area.

11. A device, characterized in that, The device includes the power module as described in any one of claims 1 to 10.

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