System-in-package carrier board

Abstract

The utility model discloses a system level package load board, including load board main part and stop welding layer, load board main part is equipped with outer layer circuit, and the outer layer circuit is divided and has pastes the functional area and big copper surface, and stop welding layer covers and is located on load board main part outer surface, and stop welding layer does not cover pastes the functional area, but covers big copper surface outer periphery, pastes the functional area includes main functional area and secondary functional area, and the main functional area includes a plurality of FC pad bottom copper that array is arranged on big copper surface, and the area on big copper surface and located in every FC pad bottom copper peripheral prearranged range is used as protection area, first surface treatment layer that the outermost side is gold layer is plated and is established on the main functional area respectively, forms first functional film layer on the surface of protection area, forms second functional film layer on the surface of secondary functional area, the different functional surface treatment structure of setting up on the different functional area of this package load board has satisfied FC welding, wire bonding, SMT pastes etc. Heterogeneous package demand, has reduced manufacturing cost.

Description

Technical Field

[0001] This utility model relates to the field of advanced packaging technology, and in particular to a system-level packaging carrier with diversified surface treatment structures. Background Technology

[0002] As semiconductor packaging technology evolves towards higher density, multifunctionality, and miniaturization, system-in-package (SIP) has become a crucial technological approach in the post-Moore's Law era. SIP integrates multiple chips, passive devices, and active devices with different functions into a single package. It enables various packaging processes on a single package substrate, such as flip-chip bonding, wire bonding, and surface mount technology.

[0003] Different packaging and mounting methods impose different requirements on the physical and chemical properties of the substrate pad surface. For example: ① FC flip-chip bonding technology usually requires the pad surface to be gold-plated (such as electroless nickel-gold, electroless nickel-palladium-gold, or electroplated nickel-gold), and to ensure soldering reliability, the large copper surface around the FC pad needs to have solder resisting / rejecting properties; ② The wire bonding area requires a highly reliable gold-plated surface to ensure bonding strength; ③ In SMT surface mount technology, the pads of passive devices (such as resistors and capacitors) can usually be treated with organic solder protectant (OSP) to meet solderability requirements and at a lower cost; while the pads of power devices (such as MOSFETs) often need to be gold-plated due to reliability requirements.

[0004] However, existing packaging substrate structures have the following shortcomings: ① Existing packaging substrates typically only have a maximum of two surface treatment structures, making it difficult to accurately match the diverse packaging requirements mentioned above. ② While a full-board gold plating solution can cover various mounting requirements, it results in a large amount of precious metals and high manufacturing costs; while an OSP surface treatment solution cannot meet the processing requirements of FC soldering and high-reliability bonding.

[0005] In view of the above, this utility model is hereby proposed. Utility Model Content

[0006] To overcome the above-mentioned defects, this utility model provides a system-level packaging carrier board with different surface treatment structures on different functional areas. It not only meets the heterogeneous packaging requirements of FC soldering, wire bonding, passive device SMT soldering, and power device SMT mounting, but also achieves the optimal configuration of costs and significantly reduces manufacturing costs.

[0007] The technical solution adopted by this utility model to solve its technical problem is as follows: a system-in-package carrier board, including a carrier board body and a solder mask layer. The carrier board body is provided with an outer layer circuit, which is divided into a mounting functional area and a large copper surface. The solder mask layer is applied to the outer surface of the carrier board body, and the solder mask layer does not cover the mounting functional area on the outer layer circuit, but covers the outer periphery of the large copper surface. The mounting functional area includes a main functional area and a secondary functional area. The main functional area includes an FC soldering area composed of a plurality of FC solder pad bottom copper arrays arranged on the large copper surface. The area on the large copper surface and located within a predetermined range outside the bottom copper of each FC solder pad is used as a protective area. In addition, a first surface treatment layer is plated on the main functional area. The first surface treatment layer includes a gold layer located on the outermost side. A first functional film layer with solder resisting function is formed on the surface of the protective area, and a second functional film layer with anti-oxidation function is formed on the surface of the secondary functional area.

[0008] As a further improvement of this utility model, the first functional film layer is a browning layer or a blackening layer.

[0009] As a further improvement of this utility model, the remaining area on the large copper surface, excluding the FC welding area and the outer peripheral area covered by the solder resist layer, is used as the protective area.

[0010] As a further improvement of this utility model, the second functional film layer adopts an OSP protective film.

[0011] As a further improvement of this utility model, the first surface treatment layer is composed of a nickel layer, a palladium layer and the gold layer arranged sequentially from the inside to the outside, or it is composed of a nickel layer and the gold layer arranged sequentially from the inside to the outside.

[0012] As a further improvement of this utility model, the main functional area further includes a wire bonding area composed of a plurality of wire bonding finger bottom copper and a first SMT soldering area composed of a plurality of first SMT pad bottom copper; the secondary functional area includes a second SMT soldering area composed of a plurality of second SMT pad bottom copper. Accordingly, the copper base of each FC pad and the first surface treatment layer thereon together form an FC pad; the copper base of each wire bonding finger and the first surface treatment layer thereon together form a wire bonding finger; the copper base of each first SMT pad and the first surface treatment layer thereon together form a first SMT pad for connection to power devices; and the copper base of each second SMT pad and the second functional film layer thereon together form a second SMT pad for connection to passive devices.

[0013] As a further improvement of this utility model, the carrier board body is also provided with an insulating intermediate layer. On the opposite sides of the insulating intermediate layer, an inner layer circuit, an insulating layer and an outer layer circuit are stacked sequentially from the inside to the outside, and the two outer layer circuits are electrically connected to the two inner layer circuits respectively.

[0014] The beneficial effects of this utility model are as follows: Compared with the prior art, the system-level packaging substrate provided by this utility model has the following advantages: ① The packaging substrate is provided with surface treatment structures with different functions in different functional areas (specifically, the first surface treatment layer, the first functional film layer, and the second functional film layer), which well meets the heterogeneous packaging requirements such as FC soldering, wire bonding, passive device SMT soldering, and power device SMT mounting. ② By providing the first functional film layer with solder resist function on the large copper surface and within a preset range around the bottom copper of each FC pad, this utility model significantly improves the accuracy and reliability of subsequent FC soldering, while also improving the high-frequency signal transmission performance and the bonding force between the packaging molding compound and the roughened copper layer interface, effectively reducing the cracking and delamination problems of the packaging substrate under high / low temperature reliability conditions. ③ This utility model only deposits the first surface treatment layer containing a gold layer on the main functional areas (such as the FC soldering area, the wire bonding area, and the first SMT soldering area), while setting the second functional film layer with the lowest cost on the secondary functional areas, and setting the first functional film layer on the protective area. Through the above-mentioned differentiated configuration of the areas, the cost is optimized, and the amount of precious metals used and the manufacturing cost are greatly reduced. ④ The diversified surface treatment structure provided by this utility model (specifically: the first surface treatment layer, the first functional film layer, and the second functional film layer) can not only achieve the coexistence of different areas on the same side of the packaging substrate, but also implement different surface treatment combinations on the front and back sides of the packaging substrate, providing greater wiring and packaging freedom for the three-dimensional stacking and double-sided mounting design in complex system-level packaging. Attached Figure Description

[0015] Figure 1 This is a cross-sectional structural diagram of the carrier plate body described in this utility model; Figure 2 This is a schematic cross-sectional view of the structure after a solder resist layer is applied to the outer surface of the carrier plate body in this utility model. Figure 3 This is a cross-sectional structural diagram of the system-in-package carrier board described in this utility model.

[0016] Referring to the accompanying drawings, the following explanations are provided: 1. Outer layer circuitry; 10. Main functional area; 11. Secondary functional area; 12. Protective area; 13. Other protective areas; 14. Large copper surface; 2. Solder mask layer; 30. First surface treatment layer; 31. First functional film layer; 32. Second functional film layer; 4. Insulating intermediate layer; 5. Inner layer circuitry; 6. Insulating reinforcement layer; 7. Conductive copper layer. Detailed Implementation

[0017] The preferred embodiments of this utility model will be described in detail below with reference to the accompanying drawings.

[0018] Example:

[0019] Please see the appendix Figure 1 To be continued Figure 3 As shown, this embodiment provides a system-in-package (SIPP) carrier board, including a carrier board body and a solder mask layer 2. The carrier board body has an outer layer circuit 1, which is divided into a mounting functional area and a large copper surface 14. The solder mask layer 2 is applied to the outer surface of the carrier board body, and the solder mask layer 2 does not cover the mounting functional area on the outer layer circuit 1, but it does cover the outer periphery of the large copper surface 14. Further, the mounting functional area is divided into a main functional area 10 and a secondary functional area 11. The main functional area 10 includes an FC soldering area composed of a plurality of FC pad bottom copper arrays arranged on the large copper surface 14, and a plurality of wire bonding finger bottom copper. The main functional area 10 has a wire bonding area and a first SMT soldering area composed of a plurality of first SMT pad bottom copper, and the area on the large copper surface 14 and located within a predetermined range around the bottom copper of each FC pad is used as a protective area 12. The secondary functional area 11 includes a second SMT soldering area composed of a plurality of second SMT pad bottom copper. In addition, a first surface treatment layer 30 is plated on the main functional area 10, the first surface treatment layer 30 includes a gold layer located on the outermost side, a first functional film layer 31 with solder resisting function is formed on the surface of the protective area 12, and a second functional film layer 32 with anti-oxidation function is formed on the surface of the secondary functional area 11. Accordingly, the bottom copper of each FC pad together with the first surface treatment layer 30 on its surface forms an FC pad, the bottom copper of each wire bonding finger together with the first surface treatment layer 30 on its surface forms a wire bonding finger, and the bottom copper of each first SMT pad together with the first surface treatment layer 30 on its surface forms a first SMT pad for connection to power devices (including but not limited to metal oxide semiconductor field effect transistors MOSFETs); the bottom copper of each second SMT pad together with the second functional film layer 32 on its surface forms a second SMT pad for connection to passive devices (including but not limited to resistors, capacitors, etc.).

[0020] Understandably, compared to existing technologies, the system-level packaging substrate provided in this embodiment has the following advantages: ① The packaging substrate has surface treatment structures with different functions (specifically, the first surface treatment layer 30, the first functional film layer 31, and the second functional film layer 32) set on different functional areas, which well meets the heterogeneous packaging requirements such as FC soldering, wire bonding, passive device SMT soldering, and power device SMT mounting. ② This embodiment significantly improves the accuracy and reliability of subsequent FC soldering by setting the first functional film layer 31 with solder resist function on the large copper surface 14 and in the area within the preset range of the bottom copper of each FC pad, while also improving the high-frequency signal transmission performance and the bonding force between the packaging molding compound and the roughened copper layer interface, effectively reducing the cracking and delamination problems of the packaging substrate under high / low temperature reliability conditions. ③ In this embodiment, the first surface treatment layer 30 containing a gold layer is plated only on the main functional areas (such as the FC soldering area, the wire bonding area, and the first SMT soldering area), while the second functional film layer 32, which has the lowest cost, is set on the secondary functional areas, and the first functional film layer 31 is set on the protective area. Through the above-mentioned differentiated configuration of the areas, the cost optimization configuration is achieved, which significantly reduces the amount of precious metals used and the manufacturing cost. ④ The diversified surface treatment structure provided by this embodiment (specifically, the first surface treatment layer 30, the first functional film layer 31, and the second functional film layer 32) can not only achieve the coexistence of different areas on the same side of the packaging substrate, but also implement different surface treatment combinations on the front and back sides of the packaging substrate, providing greater wiring and packaging freedom for the three-dimensional stacking and double-sided mounting design in complex system-level packaging.

[0021] The specific structure of the system-in-package carrier board described in this embodiment will be described in detail below.

[0022] Regarding the carrier board body, its specific implementation structure is determined based on the design requirements of the system-in-package carrier board. This application does not impose any limiting requirements. However, in order to provide a clear and detailed description of the specific structure of the system-in-package carrier board provided in this application, this embodiment uses a four-layer board structure as an example for explanation. For details, please refer to the appendix. Figure 1 As shown, the implementation structure of the carrier board body is as follows: it includes an insulating intermediate layer 4, and inner layer circuits 5, insulating reinforcement layer 6 and outer layer circuits 1 are stacked sequentially from the inside to the outside on the opposite sides of the insulating intermediate layer 4, and the two outer layer circuits 1 are electrically connected to the two inner layer circuits 5 respectively through conductive copper layers 7.

[0023] Furthermore, in this embodiment, the carrier board body can be manufactured using the subtractive process or mSAP process commonly used in the circuit board processing field, so it will not be described in detail here.

[0024] Furthermore, both the insulating intermediate layer 4 and the insulating augmentation layer 6 can be, but are not limited to, prepregs, and the thicknesses of the insulating intermediate layer 4, the insulating augmentation layer 6, the inner layer circuit 5, and the outer layer circuit 1 are determined according to the design requirements of the system-in-package carrier board, and this application does not impose any restrictions.

[0025] Furthermore, according to the design requirements of the system-in-package (SIPP) substrate, the structure of the outer layer circuit 1 is designed as follows: it includes a circuit pattern body, a large copper surface 14 (which can be understood as "a copper block with a relatively large outer surface area"), several FC pad base copper arrays arranged on the large copper surface 14, several wire bonding finger base copper arrays, several first SMT pad base copper arrays, and several second SMT pad base copper arrays. Correspondingly, the several FC pad base copper arrays together form the FC soldering area, the several wire bonding finger base copper arrays together form the wire bonding area, the several first SMT pad base copper arrays together form the first SMT soldering area, and the several second SMT pad base copper arrays together form the second SMT soldering area.

[0026] Based on the carrier board body, in this embodiment, the solder resist layer 2 is first formed on the outer surface of the carrier board body using a solder resist process (which can be a liquid photosensitive solder resist process). The solder resist layer 2 does not cover the mounting functional area on the outer layer circuit 1, but it covers the outer periphery of the large copper surface 14. Then, the main functional area 10 is surface treated / gold plated using a selective gold plating process (which can be a selective chemical gold plating process or a selective electroplating gold plating process commonly used in the circuit board processing field) to achieve the deposition of the first surface treatment layer 30 on the main functional area 10. Next, the first functional film layer 31 with solder resisting function is formed on the surface of the protective area 12 and other protective areas 13 that also have solder resisting requirements using a "selective dry coating, surface protection treatment and dry film removal combination process" (understandably, other protective areas 13 also belong to the outer layer circuit 1). Then, the second functional film layer 32 with anti-oxidation function is formed on the surface of the secondary functional area 11 using a "selective dry coating, surface anti-oxidation treatment and dry film removal combination process".

[0027] Furthermore, in this embodiment, the first surface treatment layer 30 may be composed of a nickel layer, a palladium layer, and a gold layer arranged sequentially from the inside out, wherein the thickness of the nickel layer is preferably controlled to be 0.3–15 μm, the thickness of the palladium layer is preferably controlled to be 0.03–0.15 μm, and the thickness of the gold layer is preferably controlled to be 0.03–0.15 μm. Alternatively, the first surface treatment layer 30 may be composed of a nickel layer and a gold layer arranged sequentially from the inside out, wherein the thickness of the nickel layer is preferably controlled to be 3–15 μm, and the thickness of the gold layer is preferably controlled to be 0.05–1 μm.

[0028] Furthermore, in this embodiment, the surface protection treatment is preferably performed using a browning or blackening process, and correspondingly, the first functional film layer 31 is preferably a browning or blackening layer. The reason why the first functional film layer 31 has solder-blocking / solder-rejecting functions is the result of the combined action of multiple physical and chemical mechanisms in the browning / blackening layer, as explained in detail below: In the field of multilayer printed circuit board manufacturing, the typical physicochemical properties of browning and blackening layers are as follows: I) The main component of the browning layer is cuprous oxide, which appears as a fine granular, nodular, or gravelly structure on a microscopic scale; the typical surface roughness Ra of the browning layer is 0.4–0.8 μm, and the solder wetting angle θ is 80°–110°; II) The main component of the blackening layer is copper oxide, which appears as a fine feather-like or cauliflower-like structure on a microscopic scale; the typical surface roughness Ra of the blackening layer is 0.6–1.2 μm, and the solder wetting angle θ is 95°–130°.

[0029] As can be seen from the above, ① compared to a pure copper surface (where the solder wetting angle θ is approximately 25°), the brown and black layers are not only denser in microstructure, but their main components (cuprous oxide or copper oxide) are also chemically extremely stable. This blocks the direct contact between the tin in the solder and the underlying copper, thus forcibly halting the alloying reaction and causing a sharp drop in wettability (i.e., the solder wetting angle of the brown and black layers is significantly increased). ② Liquid solder spreads easily and evenly on a smooth pure copper surface, but on the complex microstructure of the brown or black layers, which have porous structures and high specific surface areas, the surface tension of the liquid solder dominates. This makes it difficult for the solder to penetrate into the tiny pores of the microstructure, and it is also prone to retraction under the action of surface tension, forming an extremely high contact angle, exhibiting a soldering resistance / rejection phenomenon similar to the "lotus effect." ③ Compared to the highly reactive pure copper surface, the surface energy of the brown and black layers is significantly reduced, causing the liquid solder to lose its thermodynamic propulsion for free spreading. In summary, because the browning and blackening processes physically create a rough, porous structure that hinders solder spreading and chemically generate an oxide film that blocks the alloying reaction, the resulting browning and blackening layers exhibit a large wetting angle and excellent solder resisting / rejecting properties.

[0030] Furthermore, due to the significant difference in chemical activity between copper and gold, copper is an active metal while gold is inactive. Therefore, during the processing of the first functional film layer 31, the first functional film layer 31 can only be formed on the copper surface (i.e., formed on the surface of the protective area 12 and other protective areas 13), and will not be formed on the gold surface (i.e., will not be formed on the first surface treatment layer 30).

[0031] In addition, please continue to refer to the appendix. Figure 2As shown, in this embodiment, in order to improve the processing convenience of the first functional film layer 31 and to better improve the accuracy and reliability of subsequent FC soldering, this embodiment preferably uses the remaining area on the large copper surface 14, excluding the FC soldering area (composed of several FC pad bottom copper, belonging to the main functional area 10) and the outer peripheral area covered by the solder resist layer 2, as the protective area 12. It can be understood that the remaining area on the large copper surface 14, excluding the FC soldering area and the outer peripheral area covered by the solder resist layer 2, is covered with the first functional film layer 31 with solder resisting function to significantly improve the FC soldering quality and avoid soldering defects and bridging caused by solder creep.

[0032] Additional notes: ① The area covered by the solder mask layer 2 on the outer periphery of the large copper surface 14 is determined according to the design requirements of the system-in-package carrier board; this embodiment does not impose any restrictions. ② Because the FC soldering area (belonging to the main functional area 10) and the protective area 12 are integrated on the same large copper surface 14, therefore, in the appendix... Figure 2 The FC soldering area (specifically referring to the copper base of the FC solder pad) and the protective area 12 are divided and distinguished by a "red dashed line".

[0033] Furthermore, in this embodiment, the surface anti-oxidation treatment method is preferably the OSP anti-oxidation treatment process, and correspondingly, the second functional film layer 32 adopts the OSP protective film.

[0034] Additional explanation: The OSP anti-oxidation treatment process described above is a commonly used technique in PCB manufacturing. The core material of the generated OSP protective film (i.e., the second functional film layer 32) is a nitrogen-containing organic compound, such as azole compounds. Furthermore, as mentioned above, due to the significant difference in chemical reactivity between copper and gold, after OSP anti-oxidation treatment, only the copper surface (i.e., the sub-functional area 11) will be covered with the OSP protective film (i.e., the second functional film layer 32), while the gold surface remains bright and clean.

[0035] Finally, the prefixes "first," "second," etc. (such as first functional film layer, second functional film layer, etc.) in the component names in this utility model patent specification are only for ease of description and are not intended to limit the scope of implementation of this utility model patent.

[0036] Many specific details have been set forth in the above description to provide a full understanding of this utility model. However, the above description is only a preferred embodiment of this utility model, and this utility model can be implemented in many other ways different from those described herein. Therefore, this utility model is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solution of this utility model using the methods and techniques disclosed above, or modify it into equivalent embodiments with equivalent changes, without departing from the scope of the technical solution of this utility model. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this utility model, without departing from the content of the technical solution of this utility model, shall still fall within the protection scope of the technical solution of this utility model.

Claims

1. A system-in-package carrier board, characterized in that: The substrate includes a carrier board body and a solder mask layer (2). The carrier board body is provided with an outer layer circuit (1). The outer layer circuit (1) is divided into a mounting functional area and a large copper surface (14). The solder mask layer (2) is applied to the outer surface of the carrier board body. The solder mask layer (2) does not cover the mounting functional area on the outer layer circuit (1), but covers the outer periphery of the large copper surface (14). The mounting functional area includes a main functional area (10) and a secondary functional area (11). The main functional area (10) includes an FC soldering area composed of a plurality of FC pad bottom copper arrays arranged on the large copper surface (14). The area on the large copper surface (14) and located within a preset range outside each FC pad bottom copper is used as a protective area (12). In addition, a first surface treatment layer (30) is plated on the main functional area (10). The first surface treatment layer (30) includes a gold layer located on the outermost side. A first functional film layer (31) with solder resisting function is formed on the surface of the protective area (12), and a second functional film layer (32) with anti-oxidation function is formed on the surface of the secondary functional area (11).

2. The system-in-package carrier board according to claim 1, characterized in that: The first functional film layer (31) is a browning layer or a blackening layer.

3. The system-in-package carrier board according to claim 2, characterized in that: The remaining area on the large copper surface (14), except for the FC welding area and the outer peripheral area covered by the solder resist layer (2), is used as the protective area (12).

4. The system-in-package carrier board according to claim 1, characterized in that: The second functional membrane layer (32) adopts an OSP protective membrane.

5. The system-in-package carrier board according to claim 1, characterized in that: The first surface treatment layer (30) is composed of a nickel layer, a palladium layer and a gold layer arranged sequentially from the inside to the outside, or is composed of a nickel layer and a gold layer arranged sequentially from the inside to the outside.

6. The system-in-package carrier board according to claim 1, characterized in that: The main functional area (10) also includes a wire bonding area composed of a plurality of wire bonding finger bottom copper and a first SMT soldering area composed of a plurality of first SMT pad bottom copper; the secondary functional area (11) includes a second SMT soldering area composed of a plurality of second SMT pad bottom copper; Accordingly, the copper base of each FC pad together with the first surface treatment layer (30) thereon forms an FC pad; the copper base of each wire bonding finger together with the first surface treatment layer (30) thereon forms a wire bonding finger; the copper base of each first SMT pad together with the first surface treatment layer (30) thereon forms a first SMT pad for connection to power devices; and the copper base of each second SMT pad together with the second functional film layer (32) thereon forms a second SMT pad for connection to passive devices.

7. The system-in-package carrier board according to claim 1, characterized in that: The carrier board body is also provided with an insulating intermediate layer (4). On the opposite sides of the insulating intermediate layer (4), an inner layer circuit (5), an insulating layer (6) and an outer layer circuit (1) are stacked sequentially from the inside to the outside. The two outer layer circuits (1) are electrically connected to the two inner layer circuits (5) respectively.

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