Semiconductor device

Abstract

A semiconductor device includes a first level structure and a second level structure, the first level structure including a silicon portion and a via formed through the silicon portion after a back end of line, the first level structure attached to a first carrier, the first carrier including an alignment mark to form the via and a corresponding backside bump pad metal, the backside bump pad metal aligning the via based on a position of the alignment mark, the second level structure bonded to the first level structure with the backside bump pad metal between the two levels. In some embodiments, the via is an inverse column with a bottom notch and a specific ratio between a top and the bottom.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices. Background Technology

[0002] The semiconductor industry continues to grow due to the continuous improvement in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.).

[0003] In addition to smaller electronic components, improvements have been developed to enhance component packaging, striving to provide smaller packages that occupy less area than previous packages. Exemplary approaches include quad flat packs (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DICs), wafer-level packages (WLPs), package-on-package (PoP), system-on-chip (SoC), or system-on-integrated-chip (SoIC) devices. Some of these 3D devices are prepared by placing chips on a wafer. These 3D devices offer good integration density and other advantages due to the reduced length of interconnect structures between stacked chips. However, there are many challenges associated with 3D devices, including the alignment of multi-level devices.

[0004] For example, vias (such as through-silicon vias) are patterned and etched based on overlay marks, alignment marks, or backside marks. During subsequent dicing and placement processes, the reference marks (i.e., overlay marks, alignment marks, or backside marks) used to align the via and the first carrier are no longer physically related. Therefore, alignment based on the previous reference marks no longer exists and may not ensure accurate and / or correct alignment in the future. To further complicate matters, alignment marks on a second carrier or substrate (i.e., not used to position the alignment marks on the first carrier) are typically used to form backside bump pad metal (BSBPM) on the via. Therefore, for the reasons described above, the via and the backside bump pad metal are often misaligned.

[0005] Therefore, existing systems on System-on-Chips (SoIC) devices are often affected by overlay (OVL) offsets between layers. Overlay offsets can occur due to misalignment, where the physical center and the identified center of a component may differ due to die displacement. Depending on the degree of misalignment, the device may require additional processing to function effectively, or in some cases, misalignment may lead to severe loss of accuracy and render the device unusable. Utility Model Content

[0006] In some embodiments, a semiconductor device is provided, the semiconductor device including a first layer structure including a plurality of vias through a silicon portion of the first layer structure, wherein the top width of the plurality of vias is greater than the bottom width of the plurality of vias, each of the plurality of vias including a via barrier layer, and a portion of the via barrier layer being located between a conductive metal material of the via and a top metal; and a plurality of back bump pad metals correspondingly coupled to the plurality of vias; and a second layer structure bonded to the first layer structure, wherein the second layer structure includes a plurality of bonding pad metals correspondingly bonded to the plurality of back bump pad metals of the first layer structure.

[0007] In some embodiments, the ratio of the bottom width of the via to the top width of the via is less than 1.

[0008] In some embodiments, the angle between the sidewall of the via and the bottom width of the via is greater than 90°.

[0009] In some embodiments, the central axis of each of the plurality of back-side bump pad metals is substantially aligned with the central axis of each of the plurality of through holes.

[0010] In some embodiments, the central axis of each of the plurality of back-side bump pad metals is within approximately 5 nm of the central axis of each of the plurality of vias.

[0011] In some embodiments, the width of each of the plurality of back-side bump pad metals is greater than the width of the top of each of the plurality of through holes.

[0012] In some embodiments, the width of each of the plurality of back-side bump pad metals is greater than the width of each of the plurality of bonding pad metals.

[0013] In some embodiments, the first hierarchical structure further includes a cover layer in which the plurality of back-side bump pad metals are located.

[0014] In some embodiments, the second-level structure further includes a dielectric layer in which the plurality of bonding pad metals are located.

[0015] In some embodiments, the capping layer is bonded to the dielectric layer. Attached Figure Description

[0016] The embodiments of this utility model can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0017] Figure 1 This is a vertical cross-sectional view of an intermediate semiconductor device having a first-layer structure, according to various embodiments of the present invention.

[0018] Figure 2 This is a vertical cross-sectional view of an intermediate semiconductor device having a first layer structure bonded to a first carrier wafer, according to various embodiments of the present invention. The first carrier wafer includes alignment marks.

[0019] Figure 3 This is a vertical cross-sectional view of an intermediate semiconductor device after gap filling, according to various embodiments of the present invention.

[0020] Figure 4 This is a vertical cross-sectional schematic diagram of an intermediate semiconductor device after chemical mechanical polishing of the first layer structure, according to various embodiments of the present invention.

[0021] Figure 5A This is a vertical cross-sectional view of an intermediate semiconductor device having multiple vias formed in a first layer structure, according to various embodiments of the present invention. This view also includes an enlarged view of the vias.

[0022] Figure 5B According to various embodiments of this utility model, it has Figure 5A A top view of the intermediate semiconductor device with the via shown.

[0023] Figure 6 This is a vertical cross-sectional schematic diagram of an intermediate semiconductor device after an etch-back process having at least two vias, according to various embodiments of the present invention.

[0024] Figure 7A This is a vertical cross-sectional view of an intermediate semiconductor device after the backside bump pad metal (BSBPM) layer has been formed and the vias have been aligned, according to various embodiments of the present invention.

[0025] Figure 7B According to various embodiments of this utility model, it has the following characteristics: Figure 7A A top view of an intermediate semiconductor device with a back-side bump pad metal layer aligned with a via.

[0026] Figure 8 This is a vertical cross-sectional schematic diagram of an intermediate semiconductor device having a first layer structure bonded to a second layer structure, according to various embodiments of the present invention.

[0027] Figure 9 This is a vertical cross-sectional schematic diagram of an intermediate semiconductor device bonded to a second carrier wafer according to various embodiments of the present invention.

[0028] Figure 10 This is a vertical cross-sectional view of the intermediate semiconductor device after the first carrier wafer has been peeled off and the intermediate semiconductor device has been flipped along the horizontal axis, according to various embodiments of the present invention.

[0029] Figure 11 This is a vertical cross-sectional schematic diagram of an intermediate semiconductor device after the formation of a passivation layer and a polyimide layer, according to various embodiments of the present invention.

[0030] Figure 12 This is a vertical cross-sectional view of an intermediate semiconductor device after the bumps have been formed, according to various embodiments of the present invention.

[0031] Figure 13A This is a vertical cross-sectional schematic diagram of a portion of a semiconductor device having improved alignment between a via and a back-side bump pad metal layer, according to various embodiments of the present invention.

[0032] Figure 13B This is a vertical cross-sectional schematic diagram of an alternative embodiment of a semiconductor device having improved alignment between a via and a back-side bump pad metal layer, according to various embodiments of the present invention.

[0033] Figure 14 This is a flowchart illustrating a method for forming a part of a semiconductor device having a via according to an embodiment of the present invention.

[0034] Figure 15 This is a flowchart illustrating a method for aligning a via with a back bump pad metal layer in a semiconductor device, according to an embodiment of the present invention.

[0035] The reference numerals in the attached figures are explained as follows:

[0036] 100: First-level structure

[0037] 102: Rewire Layer

[0038] 103, 230: Dielectric layer

[0039] 104: First carrier wafer

[0040] 106: Aim at the hole

[0041] 107, 207: Gap filling materials

[0042] 108, 308: Through holes

[0043] 110, 214: Silicon portion

[0044] 112: Barrier Layer

[0045] 114: Through-hole barrier layer

[0046] 116: Conductive metallic materials

[0047] 118: Bottom width

[0048] 120: Top width

[0049] 122: Backside bump pad metal

[0050] 124, 204: Top metal

[0051] 126: Alignment Mark

[0052] 127, 227, 229: adhesive

[0053] 130: Cap layer

[0054] 200: Second-level structure

[0055] 202: Grain

[0056] 210: Bump pad metal

[0057] 212: Second carrier wafer

[0058] 300, 400: Semiconductor devices

[0059] 304: Passivation layer

[0060] 306: Polyimide layer

[0061] 310: Microbumps

[0062] 310A: Solder pad

[0063] 310B: Solder ball

[0064] 406: Supporting substrate

[0065] 410, 424: Additional devices

[0066] 412, 426: Additional internal metal

[0067] 427: Joint Pad

[0068] BR: Bottom notch

[0069] 1400, 1500: Method

[0070] 1402, 1404, 1406, 1406a, 1406b, 1406c, 1502, 1504, 1506, 1508, 1510: Steps Detailed Implementation

[0071] It is important to understand that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, the dimensions of the components are not limited to the range or values ​​of one embodiment disclosed, but may depend on the processing conditions and / or required nature of the components. Furthermore, in the following description, embodiments in which the first component is formed above or on the second component include those where the first and second components are formed in direct contact, and embodiments in which additional components may be formed between the first and second components such that the first and second components are not in direct contact. Additionally, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0072] To facilitate the description of the relationship between one element or component and another element(s) in the drawings, spatially related terms such as "below," "under," "lower part," "above," "upper part," and similar terms are used. In addition to the orientation shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be otherwise positioned (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly. Unless otherwise explicitly stated, each element having the same reference numeral is assumed to have the same material composition and thickness within the same thickness range.

[0073] Various embodiments of this invention relate to semiconductor devices, and more particularly to multilevel semiconductor devices. A multilevel semiconductor device may include at least one integrated circuit (IC) bonded to a carrier structure (which may be, for example, a substrate, an interposer, another semiconductor die, or a semiconductor wafer). This at least one semiconductor IC may be configured, for example, as a system-on-integrated chip (SoIC), chip-on-wafer-on-substrate (CoWoS), chip-on-wafer, etc., bonded to the carrier structure. This multilevel semiconductor device can increase the density of devices that can occupy a given planar area or "footprint".

[0074] A semiconductor integrated circuit die comprises a semiconductor material substrate (e.g., a silicon substrate) and has multiple circuit components and elements formed on and / or in the semiconductor material. Typically, an integrated circuit is formed by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer over a semiconductor substrate (e.g., a wafer), patterning the various material layers using photolithography, and separating individual dies from the substrate, for example, by sawing along dicing lines between the integrated circuits.

[0075] The first level of a multi-level semiconductor device can be configured to integrate various component-level interconnect structures onto a silicon substrate with precise positioning accuracy. This process can be achieved by using techniques such as chemical-mechanical planarization (CMP), shallow trench isolation (STI) for forming isolation structures, well formation for forming transistors, source and drain module fabrication, and surface treatment of contacts to prepare for metallization to form individual components such as transistors, capacitors, resistors, or other devices. Subsequently, metal interconnect layers are deposited onto the wafer through pick-and-place (PnP) assembly of the components.

[0076] Silicon dioxide or other dielectric materials are deposited between adjacent conductors as insulating layers to prevent electrical short circuits and ensure reliable connections. These insulating layers can be planarized using a combination of chemical mechanical polishing (CMP) and chemical etching to remove excess material. Silicon nitride or other barrier materials can be deposited as adhesive layers between metal interconnect structures to improve conductivity while minimizing conductive material diffusion. Other processes may involve depositing dielectric layers with precise thickness control to ensure optimized component spacing and alignment.

[0077] The device structure can be formed by placing a first device structure (e.g., an integrated circuit die) on a carrier structure in a "face-down" configuration, such that the integrated circuit assembly formed on a first side (i.e., front side) of the semiconductor substrate of the first device structure faces the surface of the carrier structure (e.g., a carrier wafer). A bonding process can be used to bond bonding components on the first device structure to corresponding bonding components on the carrier structure.

[0078] In some embodiments, the device structure may include multiple tiers. For example, an integrated circuit die may be bonded to the aforementioned carrier structure. Then, a second integrated circuit die may be bonded over a second side (i.e., the back side) of the first integrated circuit die, a third integrated circuit die may be bonded over the second integrated circuit die, and so on, to provide a multi-level bonding device structure.

[0079] A multi-level device structure can be formed by placing a second device structure (e.g., a semiconductor substrate or die, selectively having an integrated circuit formed thereon) onto a first device structure (e.g., a spaced-apart semiconductor substrate or die, selectively having an integrated circuit formed thereon). A bonding process can be used to bond bonding components on the first device structure to corresponding bonding components on the second device structure. In some embodiments, direct bonding techniques (e.g., metal-to-metal (MM) and dielectric-to-dielectric (DD) bonding techniques) can be used to bond the device structures to form a bonded device structure. In these bonding techniques, a bonding layer comprising an array of metal bonding pads surrounded by dielectric material can be formed on the structures to be bonded. The bonding layer on the second device structure can be aligned with a corresponding bonding layer on the first device structure, and the two bonding layers can contact each other. This can result in chemical pre-bonding between the dielectric materials of the corresponding bonding layers. An annealing process can then be performed to promote bonding of the metal bonding pads of the corresponding bonding layers, thereby creating a metallic bond extending between the first and second device structures. Other types of bonding processes can also be used, such as fusion bonding between dielectric bonding material layers.

[0080] A dicing process can be used to separate a portion of the bonding device structure to form individual bonding die structures, each of which may contain a stack of two or more semiconductor integrated circuit dies bonded together. The dicing process typically uses a metal blade (e.g., a cutting saw) to mechanically cut through the layers of the bonding device structure to separate the individual bonding die structures.

[0081] The processing of each layer may involve forming multilayers with precise alignment, using techniques such as photolithography, dry etching, and wet chemical processing to create physical markers, such as overlay alignment marks (OAM), as reference points in subsequent manufacturing steps. These OAMs can be configured to provide precise positioning and registration of components within each layer. Techniques such as chemical mechanical polishing (CMP) or chemical mechanical grinding (CMP) can be used to form multilayers with precise spacing control to achieve planarization while maintaining conductivity through the formation of adhesive layers between metal interconnects. Surface roughness and flatness are useful during this process due to their impact on electrical connectivity.

[0082] Alignment marks are useful components in multilayer semiconductor devices, enabling precise positioning and registration of subsequent components within each layer of the structure. Overlay alignment marks serve as reference points for the precise positioning of subsequent components within each layer. These marks can be formed using photolithography to create physical marks on a surface. Various types of alignment marks for different purposes are feasible, and may include separate layers for forming vias and alignment marks for forming capping layers. For example, vias require specific types of markings that can be detected by a scanner during grinding or drilling processes to ensure accurate positioning within the silicon portion. Alignment marks can be formed using various techniques such as dry etching, wet chemical processing, and plasma cutting processes for forming ends in subsequent layers. These marks serve as reference points for aligning components in each layer, ensuring consistent spacing and positioning between layers.

[0083] During the formation of a bonded semiconductor device, components can become misaligned due to offset. For example, existing system-integrated wafer devices are often affected by overlay (OVL) offset between multiple bonding layers. Overlay offset occurs because of misalignment between the physical center of each layer and an identified center that is different from that physical center. The physical center and the identified center may differ due to die displacement that occurs during the formation of the first layer structure.

[0084] For example, the first-level structure may include vias, which can be formed during fabrication steps (such as manufacturing and patterning individual components, like transistors, capacitors, or resistors). In an example of the fabrication process during via formation, alignment marks manufactured during the initial fabrication step are used to align the via locations. Vias formed during this process are referred to as via-first through-vias. Vias are commonly used in interconnect structures and often affect thermomechanical stresses, leading to design and manufacturing problems.

[0085] Alternatively, when vias are formed after initial fabrication and during additional fabrication processes (such as depositing metal interconnect layers on a substrate or wafer after device patterning), alignment marks created during the additional fabrication process are used to align the vias, such as metal alignment marks in the drawn areas. Vias formed during these processes are also known as via-middle through-vias. These vias are commonly used in advanced 3D integrated circuits and interposer stacks.

[0086] For vias formed during initial and additional machining, once the back side bump pad metal (BSBPM) layer is formed on the first-level structure, the vias and the BSBPM layer are no longer correlated. Therefore, vias and the BSBPM structure are often misaligned. This misalignment may be due to the fact that vias are formed using alignment marks in different machining steps, and these alignment marks no longer exist or are correctly correlated with the remaining structure when the BSBPM layer is formed. Therefore, misalignment exists between the vias and the BSBPM layer because the alignment marks used to create the vias have no physical correlation with the alignment marks used to create the BSBPM layer. Depending on the degree of misalignment, the device may require additional machining to function. In some cases, misalignment can lead to a significant loss of accuracy and negatively impact the device, even causing it to malfunction.

[0087] In various embodiments of this invention, vias are formed in a first hierarchical structure based on alignment marks in a first carrier wafer. In some embodiments, the first hierarchical structure can be prepared by forming individual components, such as transistors, capacitors, and resistors, on a silicon wafer. Furthermore, the first hierarchical structure can undergo a pick-and-place (PnP) process to assemble components on the first hierarchical structure. The first hierarchical structure can be placed on and bonded to the first carrier wafer with alignment marks. After the pick-and-place process, vias can be formed through at least a silicon portion of the first hierarchical structure using alignment marks located on the first carrier wafer via a post-via process. Since the vias are formed based on alignment marks after the pick-and-place process, a back-side bump pad metal layer can align the vias during formation based on the same alignment marks used to form the vias. Furthermore, since the vias are formed through a post-via process, the back-side bump pad metal layer can be formed after or during the formation of the vias, thereby improving the alignment between the vias and the back-side bump pad metal layer. In some embodiments, the second-level structure may be bonded to the first-level structure to form a multi-level bonding structure, the multi-level bonding structure further including aligned back-side bump pad metal layers and aligned bonding pad metal (BPM) layers. Overall, various embodiments of the present invention improve the alignment of structures located in the same and different levels of a semiconductor structure.

[0088] In some embodiments, the first-level structure can be patterned to include individual components on a substrate (e.g., a silicon wafer). This process may include: selecting a wafer, chemically mechanically planarizing or polishing (CMP) the wafer surface, performing a shallow trench isolation (STI) process to form isolation structures, forming well regions for different types of transistors, forming source and drain modules, and surface treatment to prepare contacts for metallization. Once the first-level structure contains the desired structures, these structures can be electrically connected to a circuit.

[0089] Furthermore, a metal interconnect layer can be deposited within the first-level structure, and components can be placed on the first-level structure via a pick-and-place process. For example, this process may include: silicide formation of the source and drain regions, addition of a dielectric layer to isolate the metal and silicon portions, chemical mechanical polishing (CMP) to planarize the dielectric layer, formation of vias in the dielectric layer, and metal deposition. Vias can be formed through a portion of the first-level structure (e.g., a silicon portion) to form vertical electrical connections between components.

[0090] In some embodiments, alignment marks may be formed on a first carrier wafer. Alignment marks serve as reference points for precisely positioning components within the same layer and for aligning components between different layers. Alignment marks also serve as reference points for aligning components within the same layer, ensuring consistent spacing and positioning between layers.

[0091] For example, alignment marks on the first carrier wafer can be used as patterned photolithography masks during via formation and as reference points for forming back-side bump pad metal in the capping layer. This ensures accurate placement of subsequent components on top of the vias while maintaining precise positioning between components and layers. Scanners detect the alignment marks using various techniques, such as optical microscopy (visible light), infrared imaging, X-ray inspection, or electron beam lithography, depending on the mark design and material properties.

[0092] Please refer to Figures 1 to 12 These figures show sequential vertical cross-sectional views illustrating the process of forming vias in the first layer structure, forming corresponding back-side bump pad metal layers (sometimes referred to as BSBPM layers) in the capping layer, and bonding the first layer structure to the second layer structure to form a multilayer bonded semiconductor device structure. As described above, the present invention improves the alignment between the vias and the back-side bump pad metal layers because the vias are formed after the first layer structure undergoes a pick-and-place process, and alignment marks are located on the first carrier wafer.

[0093] Figure 1This diagram shows a vertical cross-sectional view of an example of a first-level structure 100 according to various embodiments of the present invention. In some embodiments, the first-level structure 100 may be diced. As shown, the first-level structure 100 includes a silicon portion 110 and a top metal 124 (sometimes referred to as a top metal interconnect structure) formed in a dielectric layer 103 to form a redistribution layer (RDL) 102. The silicon portion 110 may include devices formed in the silicon portion 110 (not shown). Figure 1 (Middle). The device may include various active transistor devices, passive capacitors, and / or resistors. These devices can be interconnected with each other and / or interconnected to other components formed in other layered structures via top metal 124 (see reference). Figure 13A and Figure 13B Alternatively, the first hierarchy 100 may include alignment cavities 106, which may be formed during the cutting process. The alignment cavities 106 may space a portion of the first hierarchy 100.

[0094] In various embodiments, the dicing process may include system-on-a-chip (SOC) plasma dicing technology. The plasma dicing process may use a dry etching process that uses plasma, such as fluorine plasma. During the plasma dicing process, a portion of the first-level structure 100 may be chemically etched away along the dicing line. In some embodiments, the plasma dicing may use pulsed plasma dicing, time-multiplexed etching, near-isotropic plasma etching, or passivation layer deposition. In some embodiments, the first-level structure 100 undergoes dicing using techniques other than plasma dicing, such as blade dicing or laser dicing. The dicing process may form aligned holes 106.

[0095] Figure 2This is a schematic vertical cross-sectional view of the first hierarchical structure 100 after the bonding process, according to various embodiments of the present invention. After plasma cutting of the first hierarchical structure 100, a first carrier wafer 104 can be bonded to the first hierarchical structure 100. In some embodiments, the first carrier wafer 104 can be bonded to the first hierarchical structure 100 using a fusion bonding process or by an adhesive 127. In some embodiments, the adhesive 127 can be an epoxy resin layer for bonding the first carrier wafer 104 and the first hierarchical structure 100. In other embodiments, the first carrier wafer 104 and the first hierarchical structure 100 are bonded using copper microbumps, copper hybrid bonding, or other suitable bonding techniques.

[0096] Furthermore, the first carrier wafer 104 may include an alignment mark 126. A first hierarchy structure 100 may be located on and bonded to the first carrier wafer 104 such that the alignment mark 126 on the first carrier wafer 104 is located within the lateral edge of the alignment hole 106. In some embodiments, the alignment mark 126 may be an overlay alignment mark or a backside mark on the first carrier wafer 104. In other embodiments, the alignment mark 126 may be an overlay alignment mark, a transistor alignment mark, a metal alignment mark, a die alignment mark, or other suitable mark on the first carrier wafer 104.

[0097] In various embodiments, alignment mark 126 can be used to physically associate the position of the vertical via and the back bump pad metal formed in the cap layer. As described above, alignment mark 126 can be formed after the pick-and-place process and before the via is formed in the first layer structure.

[0098] Figure 3 The image shows alignment holes 106 filled with gap filler material 107, with additional gap filler material 107 placed on top of redistribution layer 102. In some embodiments, gap filler material 107 may comprise a thermal gap filler, a high aspect ratio process material, an organosilane material, other suitable materials, or a combination thereof. A thermal gap filler may comprise a silicone matrix having a filler such as boron nitride, zinc oxide, or aluminum oxide, and the gap filler both generates and dissipates heat. A high aspect ratio process gap filler may comprise a thermal non-plasma-based chemical vapor deposition (CVD) process with a high aspect ratio, which enhances transistor performance and reliability. An organosilane material may comprise crosslinked by oxygen and be radiation-curable. Gap filler material 107 may be transparent or optically activated (e.g., by using photons), making alignment marks 126 visible and / or detectable.

[0099] Figure 4This diagram shows a vertical cross-sectional view of a portion of the first hierarchical structure 100 after partial removal of the gap filler material 107. In some embodiments, the gap filler material 107 is removed using a polishing process, such as chemical mechanical polishing (CMP). In other embodiments, the gap filler material 107 is removed using a dry etching process or a wet etching process, a mechanical removal process, or other suitable removal process. Furthermore, the silicon portion 110 may be thinned during the removal process. The resulting structure includes a top surface of a coplanar silicon portion 110 and a top surface of the gap filler material 107.

[0100] Figure 5A This is a vertical cross-sectional view of a first-level structure 100 having a through-hole 108 according to various embodiments of the present invention. This view also includes an enlarged view of the through-hole 108. Various embodiments of the present invention include forming-last through-holes.

[0101] In some embodiments, the vertical via 108 electrically couples different components in the first layer structure 100 and / or other layers. For example, the via 108 allows wiring across multiple layers and provides efficient signal and power conversion.

[0102] To form via 108, holes are formed in silicon portion 110 through grinding, drilling, and / or patterning processes. Holes may further be formed through a portion of dielectric layer 103. The location of the holes may depend on alignment marks 126. More specifically, a scanner, camera, or other device can identify the location of alignment marks 126 and determine the location of holes formed in silicon portion 110 relative to the location of alignment marks 126. This ensures appropriate and consistent spacing of holes available for subsequent formation of via 108.

[0103] The hole may extend further beyond the silicon portion 110 to connect to the top metal 124 and form a bottom notch BR. In some embodiments, the bottom notch BR is larger than approximately about or about The process for removing silicon portion 110 and dielectric layer 103 can occur at specific times to remove a specific amount of silicon portion 110. In other embodiments, hole formation can continue for a period of time until a barrier layer 112 (sometimes referred to as a dielectric barrier layer) on top metal 124 is encountered.

[0104] Barrier layer 112 can protect top metal 124 during the formation of via 108. For example, a cavity is formed to connect via 108 to top metal 124. Barrier layer 112 can protect top metal during patterning, drilling, or polishing processes used to form recesses reaching top metal 124. Furthermore, barrier layer 112 can further prevent top metal 124 from diffusing into dielectric layer 103. In some embodiments, only top metal connected to via 108 includes barrier layer 112. In other embodiments, each top metal may include barrier layer 112. Barrier layer 112 may be located only on top metal 124, partially surrounding top metal 124, or completely surrounding top metal 124. Furthermore, barrier layer 112 may be formed of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0105] Selectively, after removing a portion of the silicon portion 110 and the dielectric layer 103 through drilling, polishing, and / or patterning processes to form via holes, a chemical mechanical polishing (CMP) process can be used to further remove a portion of the silicon portion 110 and smooth the via holes. CMP combines chemical etching and abrasive polishing to create a smooth surface. The CMP process can use chemical mixtures (e.g., colloids) to remove excess silicon and create a smooth surface. Furthermore, via holes can be further smoothed using epoxy dissolution to create a smooth surface.

[0106] Subsequently, the via barrier layer 114 can be deposited in the via hole using chemical vapor deposition, atomic vapor deposition, physical vapor deposition, or other deposition methods. In some embodiments, the via barrier layer 114 may be formed of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. By providing the via barrier layer 114 in the via hole, the barrier layer 112 above the top metal 124 can contact the via barrier layer 114 in the via hole. The connection between the via barrier layer 114 in the via hole and the barrier layer 112 above the top metal 124 can form a double barrier layer. A chemical mechanical polishing process can provide a smooth surface for the conductive metal material 116 to fill the via hole. Furthermore, the via barrier layer 114 can prevent the conductive metal material 116 from diffusing into the silicon portion 110 and the dielectric layer 103.

[0107] In some embodiments, a conductive metal material 116 may be grown or filled in the via cavity to form a via 108. The conductive metal material 116 may be copper, tungsten, silver, gold, or other suitable conductive materials. The conductive metal material 116 may be grown in the via cavity by chemical vapor deposition, physical vapor deposition, sputtering, electroplating, or other suitable methods. In this manner, the via 108 may include a via barrier layer 114 deposited in the via cavity and the conductive metal material 116 deposited or grown in the via cavity.

[0108] like Figure 5A As shown, a dual barrier layer can be formed, wherein the via barrier layer 114 of the via 108 contacts the barrier layer 112 of the top metal 124. In some embodiments, the barrier layer 112 and the via barrier layer 114 may be formed of the same material, partially the same material, or different materials. The barrier layer 112 and the via barrier layer 114 can be used to minimize the diffusion of conductive metal material 116, such as copper, into the silicon portion 110, the dielectric layer 103, and the top metal 124. By restricting the migration of conductive metal material 116, the dual barrier layer including the barrier layer 112 and the via barrier layer 114 ensures the structural integrity and reliability of the via 108.

[0109] Referring again to via 108, in some embodiments, the conductive metal material 116 allows different components to be vertically stacked in a semiconductor device by providing electrical connections between components and between different layers of the semiconductor structure. Furthermore, the conductive metal material 116 increases bandwidth, reduces signal delay, and improves power management. By filling via 108 with the conductive metal material 116, via 108 provides reliable and functional electrical connections between components across multiple layers and / or levels.

[0110] In some embodiments, via 108 may have an inverted columnar shape, wherein the top width 120 of via 108 (i.e., the width of via 108 adjacent to subsequently formed back bump pad metal 122) is greater than the bottom width 118 of via 108. For example, the ratio of the bottom width 118 of via 108 (i.e., the width of via 108 away from subsequently formed back bump pad metal 122) to the top width 120 of via 108 may be about 0.8, about 0.9, about 0.99, or less than about 1. In some embodiments, via 108 includes a bottom notch BR extending beyond silicon portion 110 into dielectric layer 103. The bottom notch BR may be about 0.5 micrometers, about 1 micrometer, about 5 micrometers, about 8 micrometers, about 10 micrometers, or about 15 micrometers. Via 108 may have a circular, elliptical, square, rectangular, or other polygonal horizontal cross-sectional shape. The width of the via 108 can be optimized to provide an electrical via with appropriate resistance for suitable electrical connections.

[0111] Figure 5B The above references are shown. Figure 5A The diagram shows a top view of the via 108 formed by the described process. As shown, alignment marks 126 are visible through the gap-filling material 107 in the alignment cavities 106 using a scanner, camera, or other suitable method. After identifying the alignment marks 126, the location of the via cavities can be determined, and the via 108 can subsequently be formed and positioned within these cavities. The alignment marks 126 ensure that the via 108 is formed at consistent intervals in the appropriate locations.

[0112] Please refer to Figure 6 An etch-back process is performed to remove a portion of the silicon portion 110 and expose the top of the via 108. In some embodiments, the etch-back process may be a wet etching or a dry etching process. A wet etching process may involve applying a chemical solution to a surface to selectively remove specific materials, such as the silicon portion 110. A dry etching process may involve applying a gas or plasma to a material to selectively remove material, such as the silicon portion 110. The etching process removes the top of the silicon portion 110 and partially exposes the via 108.

[0113] Figure 7A According to various embodiments, a vertical cross-sectional schematic diagram of a first layer structure 100 after the back bump pad metal 122 is formed in the cover layer 130 is shown, wherein the back bump pad metal 122 is aligned with the through hole 108 based on the alignment mark 126.

[0114] Initially, a dielectric layer (also referred to as capping layer 130) may be formed over silicon portion 110. Capping layer 130 may be patterned or drilled to form back-side bump pad metal holes at locations determined based on alignment marks 126 corresponding to the location of via 108. A scanner may be used to identify alignment marks 126 associated with the first carrier wafer 104. In this way, alignment marks 126 can be used to form via 108 and back-side bump pad metal 122. Different identification tools may be used to identify alignment marks 126; however, the same alignment marks 126 can still be used to form both via 108 and back-side bump pad metal 122. In this way, the position of back-side bump pad metal 122 can be determined relative to the same alignment mark 126 used to determine the position of via 108. In doing so, the position of back-side bump pad metal 122 can be correlated with the position of via 108. This process facilitates the alignment of the back-side bump pad metal 122 with the center of the via 108.

[0115] Selectively, the back bump pad metal cavities may further undergo a polishing process (e.g., chemical mechanical polishing) to smooth the cavity surface. In some embodiments, the back bump pad metal 122 may be formed in the back bump pad metal cavities using a coating, exposure, and development process. For example, deposition, electroplating, or sputtering methods may be used to grow or deposit conductive metal in the back bump pad metal cavities to form the back bump pad metal 122. In some embodiments, the conductive metal in the back bump pad metal 122 is formed of copper, tungsten, gold, silver, other conductive metals, or combinations thereof, which provides conductivity while also ensuring reliable connections between layers and preventing oxidation.

[0116] The back-side bump pad metal 122 provides interconnects, improves reliability, and enables a flat surface for connecting components in the final semiconductor package. Furthermore, the back-side bump pad metal 122 can provide improved interconnect density, particularly in complex semiconductor structures. The back-side bump pad metal 122 can be embedded in the exposed portion of the via 108, thus forming directly above and contacting the silicon portion 110. In some embodiments, more back-side bump pad metal 122 may be formed than the via 108. In other embodiments, the number of vias 108 and the number of back-side bump pad metal 122 may be the same.

[0117] By forming via 108 as a post-processed via, the alignment mark 126 associated with the first carrier wafer 104 remains available and physically associated with the position of via 108. Therefore, by using the same alignment mark 126, the back-side bump pad metal 122 can be properly aligned with the via 108. For these reasons, this embodiment of the invention improves the alignment between via 108 and back-side bump pad metal 122 by maintaining the physical correlation between components based on the alignment mark 126. For example, the central axis of via 108 and the central axis of back-side bump pad metal 122 can be aligned within approximately 1 nm, approximately 2 nm, approximately 4 nm, approximately 5 nm, or greater than 5 nm. For these reasons, this embodiment of the invention advantageously improves the alignment between via 108 and back-side bump pad metal 122 by using the alignment mark 126 on the first carrier wafer 104 after the pick-and-place process on the first hierarchical structure 100.

[0118] Figure 7BA top view showing the back-side bump pad metal 122 aligned with the via 108 based on alignment marks 126. As shown, the alignment marks 126 on the first carrier wafer 104 are visible through the gap filler material 107 in the alignment cavity 106. Once the alignment marks 126 are identified, the location for forming the back-side bump pad metal 122 is determined. Determining the location results in the back-side bump pad metal 122 completely covering and aligning with the via 108. As shown, the central axis of the back-side bump pad metal 122 is approximately aligned with the central axis of the via 108.

[0119] Figure 8 This illustration shows a vertical cross-sectional view of a first layer 100 bonded to a second layer 200 to form a semiconductor device 300, according to various embodiments of the present invention. The second layer 200 can be disposed above the first layer 100 using a pick-and-place process. The pick-and-place process can use alignment marks 126 located on a first carrier wafer 104 to align the second layer 200 with the first layer 100. In some embodiments, the second layer 200 includes bump pad metal 210 and top metal 204 located in a dielectric layer 230, and a silicon portion 214 located above the dielectric layer 230.

[0120] The second-level structure 200 can be bonded to the first-level structure 100 via a hybrid bonding process. The hybrid bonding process (also referred to as direct bonding) bonds the second-level structure 200 to the first-level structure 100 using a metal-to-metal connection between the back-side bump pad metal 122 and the bump pad metal 210, and a dielectric-to-dielectric connection between the capping layer 130 and the dielectric layer 230. In some embodiments, each back-side bump pad metal 122 on the first-level structure 100 may correspond to a bump pad metal 210 on the second-level structure 200.

[0121] Furthermore, the semiconductor device 300 may include a die 202 (e.g., a dummy die, other active die, or wafer) that may be bonded and / or attached to the first hierarchy 100. A gap-filling material 207 may surround the second hierarchy 200 and the die 202. In some embodiments, the die 202 may be diced by a plasma dicing process prior to bonding to the first hierarchy 100. The plasma dicing process may include a dry etching process using a chemical formulation (e.g., fluorine plasma) to etch cut lines. In other embodiments, the die 202 may be diced using a blade dicing process, a laser dicing process, or other suitable dicing processes. In some embodiments, the die 202 may be formed of silicon monoxide, silicon oxynitride, silicates, silicon dioxide, or other suitable compounds.

[0122] Once the die 202 has been segmented using a plasma cutting process, it can be adhered to the first-level structure 100 via adhesive 229. Alternatively, in some embodiments, the die 202 can be bonded to the first-level structure 100 via a fusion bonding process (also known as direct bonding). The fusion bonding process includes a room-temperature pre-bonding stage, in which hydrogen bonding generates initial interfacial bonds. Furthermore, the fusion bonding process includes a high-temperature annealing stage, in which the annealing process promotes the formation of covalent bonds on the surface. In some embodiments, the die 202 can provide structural and thermal management support during the fabrication of the semiconductor device 300.

[0123] Figure 9 The diagram shows a vertical cross-sectional view of the semiconductor device 300 after the second carrier wafer 212 has been bonded to the second hierarchy 200 and the die 202. The second carrier wafer 212 can be bonded to the second hierarchy 200 using an adhesive 227. In some embodiments, the adhesive 227 may be an epoxy resin layer or other suitable adhesive. In other embodiments, the second carrier wafer 212 and the second hierarchy 200 can be bonded using other suitable bonding techniques.

[0124] Figure 10 This is a cross-sectional view showing the semiconductor device 300 after the first carrier wafer 104 has been removed and the entire device has been flipped. In other words, the first layer structure 100 sits on top of the second layer structure 200, which is adhered to the second carrier wafer 212. In some embodiments, the first carrier wafer 104 can be removed by chemical or mechanical processes to remove the adhesive layer or adhesive 127.

[0125] Figure 11 This diagram shows cross-sectional views of the passivation layer and polyimide layer according to various embodiments of the present invention. In some embodiments, the passivation layer 304 may be formed over the first layer structure 100. The passivation layer 304 may be formed of an oxide layer, a nitride layer, a borosilicate layer, a glass layer, other suitable materials, or a combination thereof. The passivation layer 304 can enhance resistance to environmental factors and prevent the degradation of the semiconductor device 300 to ensure long-term reliability. Furthermore, the passivation layer 304 can provide a barrier to prevent the metal layer from oxidation and corrosion.

[0126] In some embodiments, via 308 may be formed through passivation layer 304, connecting top metal 124 to other components and forming a vertical electrical connection. Holes may be formed in passivation layer 304 using a patterning process. Once the holes are formed, polyimide layer 306 may be deposited along the top surface of passivation layer 304 and into the holes, whereby via 308 is subsequently formed. Polyimide layer 306 may be deposited using chemical vapor deposition, physical vapor deposition, atomic vapor deposition, or other suitable deposition methods.

[0127] The polyimide layer 306 provides thermal stability, electrical insulation, and mechanical strength to the semiconductor device 300. Furthermore, the polyimide layer 306 provides mechanical elasticity, tensile strength, and enhances adhesion between devices to achieve a stable connection. Additionally, the polyimide layer 306 provides stress buffering to reduce thermal stress, provides a protective layer to shield the semiconductor device 300 from environmental influences, and serves as a high-temperature adhesive.

[0128] After the polyimide layer 306 is formed, conductive material is deposited or grown in the holes using a deposition method, electroplating method, sputtering method or other suitable method to form the final via 308.

[0129] Figure 12 An example of forming a microbump 310 over a via 308 is shown, providing electrical connection between a semiconductor device 300 and components in a final semiconductor package. In some embodiments, the microbump 310 may be formed of a soldering material, such as a tin alloy. The microbump 310 may further include a solder pad 310A and solder balls 310B located on the solder pad 310A. The microbump 310 may be connected to other components, devices, dies, or elements in the semiconductor package.

[0130] Please refer to Figure 13A and Figure 13B The semiconductor device 400 is, in an example, coupled to a carrier substrate 406. The semiconductor device 400 can be coupled to the carrier substrate 406 by placing the semiconductor device 400 to align the microbumps 310 with bonding pads 427 formed on the carrier substrate 406. A reflow process can be performed to reflow solder balls 310B to couple the microbumps 310 to the bonding pads 427 of the carrier substrate 406. The semiconductor device 400 can be coupled to the carrier substrate 406 via... Figures 1 to 12 The semiconductor cutting device 300 is described to be formed. Figure 13A This diagram shows a vertical cross-sectional view of a semiconductor device 400 according to various embodiments of the present invention, wherein the first layer structure 100 is generally aligned with the second layer structure 200. Figure 13B This diagram shows a vertical cross-sectional view of a semiconductor device 400 according to various embodiments of the present invention, wherein a first layer structure 100 is offset (i.e. slightly misaligned) from a second layer structure 200.

[0131] In addition, such as Figure 13A and Figure 13BAs shown in the embodiments, the first hierarchical structure 100 may further include additional device 410 and additional internal metal 412, while the second hierarchical structure 200 includes additional device 424 and additional internal metal 426. In some embodiments, the additional devices 410 and 424 may be formed in silicon portions 110 and 214, respectively. The formation of the additional devices 410 and 424 may be prior to the formation of the via 108, the back-side bump pad metal 122, and / or the pick-and-place process of placing the second hierarchical structure 200 above the first hierarchical structure 100. The additional devices 410 and 424 may be capacitors, transistors, or other suitable devices. The additional internal metals 426 and 412 may electrically connect the additional devices 410 and 424 to dielectric layers 230 and 103, respectively.

[0132] As described above, the location of the via 108 can be determined based on alignment marks 126 on the first carrier wafer 104. After the via 108 is formed, the back-side bump pad metal 122 can be formed based on the same alignment marks 126. Since the via 108 and the back-side bump pad metal 122 are formed based on the same alignment marks 126 associated with the first carrier wafer 104, the via 108 and the back-side bump pad metal 122 are substantially aligned. For example, the central axis of the via 108 can be substantially aligned with the central axis of the back-side bump pad metal 122. This improved alignment provides a more reliable electrical connection between the back-side bump pad metal 122 and the via 108.

[0133] More specifically, the via 108 has an inverted columnar shape, wherein the bottom width 118 of the via 108 (i.e., the portion of the via 108 away from the subsequently formed back bump pad metal 122) is smaller than the top width 120 of the via 108 (i.e., the portion of the via 108 adjacent to the subsequently formed back bump pad metal 122). In some embodiments, the ratio of the bottom width 118 to the top width 120 is between about 0.9 and about 0.99, or less than about 1. Furthermore, the back bump pad metal 122 may have a width greater than the top width 120 of the via 108. This further improves the alignment between the via 108 and the back bump pad metal 122. The increased width of the back bump pad metal 122 provides an enhanced landing target for placing the second hierarchy 200 on top of the first hierarchy 100 during the pick-and-place process. This increased width of the back-side bump pad metal 122 can provide a wider margin of error in the event of misalignment or misalignment between the second hierarchical structure 200 and the first hierarchical structure 100.

[0134] Therefore, embodiments of the present invention advantageously improve the alignment of the via 108 and the back-side bump pad metal 122 by forming the via 108 and the back-side bump pad metal 122 based on the same alignment mark 126 associated with the first carrier wafer 104. Furthermore, in some embodiments, this alignment can be further enhanced by placing the second layer structure 200 also based on the same alignment mark 126. This improved alignment also improves the connectivity, stability, and efficiency of the multilayer semiconductor device 400.

[0135] In some embodiments, the bump pad metal 210 included in the second hierarchy 200 can be aligned with the back-side bump pad metal 122 included in the first hierarchy 100 based on alignment marks 126. Similarly, the back-side bump pad metal 122 has a larger width than the bump pad metal 210, further improving alignment. Figure 13A As shown, the first-level structure 100 and the second-level structure 200 are approximately aligned. In contrast, due to the alignment between the via 108, the back-side bump pad metal 122, and the bump pad metal 210, even when the first-level structure 100 is not aligned with the second-level structure 200, such as... Figure 13B As shown, proper electrical connections still exist within the semiconductor device 400. In other words, regardless of whether the first hierarchical structure 100 is substantially aligned with the second hierarchical structure 200, the via 108 maintains proper electrical connections with the back-side bump pad metal 122 and bump pad metal 210, providing complete electrical connections through the first hierarchical structure 100 and the second hierarchical structure 200. Therefore, misalignment caused by pick-and-place errors, bonding errors, or other manufacturing errors can be mitigated.

[0136] The following discussion refers to many manufacturing processes used to form the semiconductor device 300 or 400 with the bonding. Although the various processing steps are discussed in a specific order or shown in the flowchart to occur in a specific order, no particular order is required unless explicitly stated or required, as one action depends on another action that is completed before that action.

[0137] The following combination Figure 14 Describe the embodiments, Figure 14 A flowchart is shown for an exemplary method 1400 for forming a via 108 in semiconductor devices 300 and 400. In some embodiments, step 1402 includes providing a first hierarchy 100, wherein the first hierarchy 100 includes a silicon portion 110 and a top metal 124. In some embodiments, an additional device 410 may be formed in the silicon portion 110 and coupled to the top metal 124. In some embodiments, an alignment hole 106 may also be formed in the first hierarchy 100.

[0138] In some embodiments, step 1404 includes attaching a first carrier wafer 104 to a first hierarchy 100. In some embodiments, the first carrier wafer 104 includes alignment marks 126, which may be overlay alignment marks or back-side marks, and the alignment marks 126 are associated with alignment holes 106. Therefore, the alignment marks 126 can be easily identified by using a scanner, camera, or other suitable identification method through the alignment holes 106.

[0139] In some embodiments, step 1406 includes forming a plurality of vias 108 extending through at least a silicon portion 110 based on alignment marks 126. Optionally, the vias 108 may extend through a portion of the dielectric layer 103. The location of the vias 108 may be based on the alignment marks 126 associated with the first carrier wafer 104. In some embodiments, a scanner is used to identify the alignment marks 126 and determine the location where the vias 108 are formed. The vias 108 may directly contact the top metal 124. More specifically, a via barrier layer 114 associated with the vias 108 may directly contact a barrier layer 112 associated with the top metal 124 to form a dual barrier structure.

[0140] Optionally, intermediate steps 1406a, 1406b, and 1406c include forming a plurality of vias 108. In some embodiments, step 1406a includes forming holes through at least a silicon portion 110. In some embodiments, the holes are formed using patterning, grinding, or drilling processes. In some embodiments, the hole formation process occurs until the contact barrier layer 112 reaches a certain concentration or persists for a predetermined time. Furthermore, holes may be formed through a portion of the dielectric layer 103 to form at least The bottom notch. Furthermore, in some embodiments, after the initial cavity is formed, a chemical mechanical polishing process can be used to polish the cavity.

[0141] Step 1406b includes depositing a via barrier layer 114 in the hole. In some embodiments, the via barrier layer 114 may be deposited using chemical vapor deposition, physical vapor deposition, atomic vapor deposition, or other deposition methods. Furthermore, the via barrier layer 114 may be formed of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0142] Step 1406c includes filling the voids with a conductive metal material 116 to form a via 108. In some embodiments, the conductive metal material 116 may be formed or grown using electroplating, sputtering, or deposition processes. The conductive metal material 116 may be copper, tungsten, silver, gold, or other suitable materials.

[0143] The following combination Figure 15 Describe the embodiments, Figure 15A flowchart showing an exemplary method 1500 for forming a via 108 aligned with a back-side bump pad metal 122 formed in a capping layer 130 is displayed. Referring to Figures 2, 5A, and 7A, in some embodiments, step 1502 includes attaching a first hierarchical structure 100 to a first carrier wafer 104. The first carrier wafer 104 may be attached to the first hierarchical structure 100 by an adhesive 127 or other suitable bonding method.

[0144] Step 1504 includes identifying alignment marks 126 on the first carrier wafer 104. In some embodiments, alignment marks 126 are located on the first carrier wafer 104 and within alignment holes 106 of the first hierarchy 100 to allow for easy identification of alignment marks 126. Alignment marks 126 can be identified using a scanner, camera, or other identification methods.

[0145] In some embodiments, step 1506 includes forming a via 108 in the first layer structure 100, semiconductor device 400, based on alignment marks 126. For example, alignment marks 126 can be used to determine the location where the via 108 is formed in the first layer structure 100. In some embodiments, the via 108 is formed through a silicon portion 110 of the first layer structure 100. Furthermore, the via 108 may extend through a portion of the dielectric layer 103 to form a bottom notch.

[0146] Furthermore, method 1500 may include step 1508, which includes forming a back-side bump pad metal 122 substantially aligned with the via 108 based on alignment marks 126. The same alignment marks 126 on the first carrier wafer 104 are used to form both the via 108 and the back-side bump pad metal 122. Therefore, the central axis of the back-side bump pad metal 122 can be substantially aligned with the central axis of the via 108.

[0147] Furthermore, selective step 1510 includes bonding the second hierarchical structure 200 to the first hierarchical structure 100. The second hierarchical structure 200 can be placed above the first hierarchical structure 100 using the same alignment mark 126. Using the alignment mark 126 enhances the alignment of the second hierarchical structure 200 with the first hierarchical structure 100. The second hierarchical structure 200 and the first hierarchical structure 100 can be bonded using a hybrid bonding method, wherein a back-side bump pad metal 122 formed on the first hierarchical structure 100 is bonded to a bump pad metal 210 formed on the second hierarchical structure 200, and a capping layer 130 is bonded to a dielectric layer 230. The alignment mark 126 can be used to align the bump pad metal 210 with the back-side bump pad metal 122 to improve alignment. Furthermore, the increased width of the back-side bump pad metal 122 can provide a larger margin of error for the placement of the second hierarchical structure 200 on the first hierarchical structure 100. Therefore, even if the first-level structure 100 and the second-level structure 200 are deviated (see reference...) Figure 13B The components of the first-level structure 100 and the second-level structure 200 can still be electrically connected via the bump pad metal 210 and the back bump pad metal 122. Referring to all figures and various embodiments of the present invention, semiconductor devices 300 and 400 are described. Semiconductor device 300 includes a first-level structure 100, wherein the first-level structure 100 includes a plurality of vias 108 through a silicon portion 110 of the first-level structure 100, wherein the top width 120 of the vias 108 is greater than the bottom width 118 of the vias 108, each of the plurality of vias 108 includes a via barrier layer 114, and a portion of the via barrier layer 114 is located between the conductive metal material 116 of the via 108 and the top metal 124. The first-level structure 100 further includes a plurality of back bump pad metals 122 correspondingly coupled to the plurality of vias 108. Semiconductor devices 300 and 400 further include a second layer structure 200 bonded to a first layer structure 100, wherein the second layer structure 200 includes a plurality of bonding pad metals 210, corresponding to a plurality of back-side bump pad metals 122 bonded to the first layer structure 100.

[0148] In some embodiments, the ratio of the bottom width 118 to the top width 120 of the via 108 is less than 1. In some embodiments, the via 108 may have a bottom notch of at least approximately In some embodiments, the angle between the sidewall of the via 108 and the bottom width 118 of the via 108 is greater than 90°. In some embodiments, the central axis of each of the plurality of back-side bump pad metals 122 is substantially aligned with the central axis of each of the plurality of vias 108. In some embodiments, the central axis of each of the plurality of back-side bump pad metals 122 is within approximately 5 nm of the central axis of each of the plurality of vias 108. In some embodiments, the width of each of the plurality of back-side bump pad metals 122 is greater than the width of the top of each of the plurality of vias 108.

[0149] Alternative embodiments describe a method 1400 for forming semiconductor devices 300, 400, the method comprising providing a first layer structure 100, wherein the first layer structure 100 includes a top metal 124; attaching the first layer structure 100 to a first carrier wafer 104; and forming a via 108 through a silicon portion 110 of the first layer structure 100 and contacting the top metal 124.

[0150] In some embodiments, the step of forming the via 108 includes forming a hole in the silicon portion 110 of the first layer structure 100; forming a via barrier layer 114 in the hole; and filling the hole with a conductive metal material 116 to form the via 108. In some embodiments, the step of forming the hole removes at least approximately [missing information] of the dielectric layer beneath the silicon portion 110. To form a bottom notch. In some embodiments, this method includes identifying alignment marks 126 on the first carrier wafer 104. In some embodiments, this method includes determining a location in the first hierarchical structure 100 based on the alignment marks 126 to form a via 108. In some embodiments, the step of forming a via barrier layer 114 in the cavity forms a dual barrier layer having a barrier layer 112 associated with the top metal 124.

[0151] An alternative embodiment describes a method for aligning a back-side bump pad metal 122 with a via 108, the method comprising attaching a first hierarchical structure 100 to a first carrier wafer 104; identifying an alignment mark 126 on the first carrier wafer 104; and forming a via 108 in the first hierarchical structure 100 at a position relative to the alignment mark 126.

[0152] In some embodiments, the method includes etching back a portion of the first hierarchy 100 to expose the top of the via 108. In some embodiments, the method includes forming a dielectric layer (capping layer 130) above the top surface of the first hierarchy 100, wherein back-side bump pad metal is formed in the dielectric layer. In some embodiments, the method includes forming back-side bump pad metal 122 at a position relative to alignment mark 126 such that the central axis of the back-side bump pad metal 122 is substantially aligned with the central axis of the via 108. In some embodiments, the method includes bonding the second hierarchy 200 to the first hierarchy 100 by metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the step of bonding the second hierarchy 200 to the first hierarchy 100 includes bonding bonding pad metal 210 in the second hierarchy 200 to the back-side bump pad metal 122 based on alignment mark 126. In some embodiments, the step of forming the via 108 includes: forming a hole in a silicon portion 110 of the first layer structure 100; forming a via barrier layer 114 in the hole; and filling the hole with a conductive metal material 116 to form the via 108. In some embodiments, this method includes determining the location in the first layer structure 100 based on alignment marks 126 to form the via 108.

[0153] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A first-level structure, including: Multiple vias, passing through a silicon portion of the first-level structure, wherein the top width of the multiple vias is greater than the bottom width of the multiple vias, each of the multiple vias includes a via barrier layer, and a portion of the via barrier layer is located between a conductive metal material and a top metal of the via; and Multiple back-side bump pads are metal, correspondingly coupled to the multiple vias; and A second-level structure, joined to the first-level structure, wherein the second-level structure includes: Multiple bonding pad metals are correspondingly bonded to the multiple back-side bump pad metals of the first-level structure.

2. The semiconductor device as claimed in claim 1, characterized in that, The ratio of the bottom width of the through hole to the top width of the through hole is less than 1.

3. The semiconductor device as claimed in claim 1, characterized in that, The angle between the sidewall of the through hole and the bottom width of the through hole is greater than 90°.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The central axis of each of the plurality of back-side bump pad metals is approximately aligned with the central axis of each of the plurality of through holes.

5. The semiconductor device as claimed in claim 4, characterized in that, The central axis of each of the plurality of back-side bump pad metals is within approximately 5 nm of the central axis of each of the plurality of vias.

6. The semiconductor device as claimed in claim 4, characterized in that, The width of each of the plurality of back-side bump pad metals is greater than the width of the top of each of the plurality of through holes.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The width of each of the plurality of back-side bump pad metals is greater than the width of each of the plurality of joint pad metals.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first-level structure further includes a cover layer in which the plurality of back-side bump pad metals are located.

9. The semiconductor device as claimed in claim 8, characterized in that, The second-level structure further includes a dielectric layer in which the plurality of bonding pad metals are located.

10. The semiconductor device as claimed in claim 9, characterized in that, The capping layer is bonded to the dielectric layer.

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