A multi-channel pulse signal detection circuit

Abstract

The utility model discloses a kind of multi-channel pulse signal detection circuit, it is related to the technical field of characteristic parameter test equipment of power device, including multi-channel detection channel, power module and reset module, multi-channel detection channel and multiple drivers one-to-one correspondence, any detection channel includes signal acquisition circuit, comparison judging circuit and fault self-locking circuit;Signal acquisition circuit is connected with comparison judging circuit, comparison judging circuit is connected with fault self-locking circuit, fault self-locking circuit is connected with corresponding driver, reset module is connected with power module, in any detection channel, signal acquisition circuit is used to generate logic signal according to the pulse signal received by corresponding driver, the comparison judging circuit is used to generate fault signal according to logic signal and calibration signal, when the fault signal is effective level, it is used to stop output by fault self-locking circuit control corresponding driver.This circuit can feedback in time and close driver when any pulse signal fault, and reliability is high.

Description

Technical Field

[0001] This utility model relates to the technical field of power device characteristic parameter testing equipment, and in particular to a multi-channel pulse signal detection circuit. Background Technology

[0002] The current testing equipment generally uses a single signal split into multiple parallel signals based on the "Darlington transistor array" device design. Each output signal reaches the front-end isolation driver chip to control the driver chip to work. The detection method is generally placed at the output end of the isolation driver chip, by detecting whether the secondary side of the driver chip is working and whether the pulse signal is output normally.

[0003] The current detection method has drawbacks: the secondary side of the isolation driver chip is under high voltage, which poses a danger during high-voltage detection. Furthermore, the high-voltage detection circuit and the half-bridge power circuit are subject to electromagnetic and thermal coupling effects. The switching characteristics and circuit efficiency of the power devices can also cause interference, leading to complex detection circuit design. Additionally, the current detection method suffers from abnormal signal lag, which could cause a complete failure of a particular isolation driver circuit, failing to prevent timely intervention within the effective timeframe. Utility Model Content

[0004] In response to the aforementioned problems and technical requirements, the applicant has proposed a multi-channel pulse signal detection circuit.

[0005] The technical solution of this utility model is as follows: A multi-channel pulse signal detection circuit includes multiple detection channels, a power supply module, and a reset module. The multiple detection channels correspond one-to-one with multiple drivers. Each detection channel includes a signal acquisition circuit, a comparison and judgment circuit, and a fault self-locking circuit. The signal acquisition circuit is connected to the comparison and judgment circuit, the comparison and judgment circuit is connected to the fault self-locking circuit, the fault self-locking circuit is connected to the corresponding driver, the power supply module is connected to the signal acquisition circuit, the comparison and judgment circuit and the fault self-locking circuit, and the reset module is connected to the power supply module. Each of the plurality of drivers receives a pulse signal. In any detection channel, the signal acquisition circuit is used to generate a logic signal based on the pulse signal received by the corresponding driver. The comparison and judgment circuit is used to generate a fault signal based on the logic signal and the calibration signal. When the fault signal is at an active level, it is used to control the corresponding driver to stop output through a fault self-locking circuit.

[0006] A further technical solution is that the signal acquisition circuit includes an interface U3, capacitors C1, C2, C3, C4, C5, C6, and C7, resistors R2, R3, R4, R5, R6, and R7, resistor RF1, operational amplifier U4, and comparator U2, wherein... The interface U3 is connected to one end of the capacitor C6, the other end of the capacitor C6 is connected to one end of the resistor R7 and one end of the resistor R6, the other end of the resistor R6 is connected to one end of the capacitor C7 and the non-inverting input terminal of the operational amplifier U4, and the other end of the resistor R7 and the other end of the capacitor C7 are grounded. One end of resistor R5 is connected to one end of resistor RF1, one end of capacitor C1, and the inverting input terminal of operational amplifier U4. The other end of resistor R5 is grounded. The other ends of resistor RF1 and capacitor C1 are connected to one end of resistor R2. The other end of resistor R2 is connected to the output terminal of operational amplifier U4. A further technical solution is that the output terminal of the operational amplifier U4 is connected to the non-inverting input terminal of the comparator U2, the inverting input terminal of the comparator U2 is connected to one end of resistor R3 and one end of resistor R4, the other end of resistor R4 is connected to the power supply module, the other end of resistor R3 is grounded, the other end of resistor R4 is also grounded through capacitor C2, the output terminal of the comparator U2 serves as the output terminal of the signal acquisition circuit, and capacitors C3, C4, and C5 are connected in parallel with capacitor C2.

[0007] A further technical solution is that the comparison and judgment circuit includes an XNOR gate U15, a comparator U18, resistors R28, R29, R30, and R33, and capacitors C28, C29, C30, C31, and C32, wherein... The first input terminal of the XNOR gate U15 is connected to the output terminal of the signal acquisition circuit. The second input terminal of the XNOR gate U15 is connected to the calibration signal. The output terminal of the XNOR gate U15 is connected to the non-inverting input terminal of the comparator U18 through resistor R33. The non-inverting input terminal of the comparator U18 is grounded through capacitor C28. The inverting input terminal of the comparator U18 is connected to one end of resistor R30 and one end of resistor R29.

[0008] A further technical solution is that the other end of the resistor R29 is grounded, the other end of the resistor R30 is connected to the power module, the other end of the resistor R30 is also grounded through the capacitor C29, the capacitors C30, C31, and C32 are connected in parallel with the capacitor C29, the output terminal of the comparator U18 is connected to one end of the resistor R28, and the other end of the resistor R28 serves as the output terminal of the comparison judgment circuit.

[0009] A further technical solution is that the power module includes an interface CN1, a fuse F1, a Schottky diode D1, a capacitor C25, a voltage regulator U16, and a voltage regulator U17, wherein... The second pin of the interface CN1 is connected to one end of the fuse F1. The other end of the fuse F1 is connected to the negative terminal of the Schottky diode D1, one end of the capacitor C25, and the input terminal of the voltage regulator U16. The other end of the capacitor C25 and the positive terminal of the Schottky diode are grounded. The input terminal of the voltage regulator U16 is grounded through the capacitor C23. The output terminal of the voltage regulator U16 is grounded through the capacitor C26. The output terminal of the voltage regulator U16 is connected to the signal acquisition module and the comparison and judgment module. The input terminal of voltage regulator U17 is connected to the reset module. The input terminal of voltage regulator U17 is grounded through capacitor C24, and the output terminal of voltage regulator U17 is grounded through capacitor C27.

[0010] A further technical solution is that the fault self-locking circuit includes resistors R26, R31, R34, and R35, switching transistor Q1, and switching transistor Q3, wherein... One end of resistor R26 is connected to the output terminal of voltage regulator U17 in the power module. The other end of resistor R26 is connected to the first electrode of switching transistor Q1. The second electrode of switching transistor Q1 is connected to the third electrode of switching transistor Q3, one end of resistor R31, and one end of resistor R34. The other end of resistor R31 is connected to the output terminal of the comparison and judgment circuit. The other end of resistor R34 and the first electrode of switching transistor Q3 are grounded. The second electrode of switching transistor Q3, the third electrode of switching transistor Q1, and one end of resistor R35 are connected and serve as the output terminal of the fault self-locking circuit. The other end of resistor R35 is grounded.

[0011] A further technical solution is that the reset module is used to reset the fault self-locking circuit. The reset module includes resistor R44, resistor R45, switching transistor Q6, and interface CN2. One end of resistor R44 is connected to the second pin of interface CN2, the other end of resistor R44 is connected to one end of resistor R45 and the second electrode of switching transistor Q6, the third electrode of switching transistor Q6 is connected to the input terminal of voltage regulator U16, the first electrode of switching transistor Q6 is connected to the input terminal of voltage regulator U17, the other end of resistor R45 is grounded, the first pin of interface CN2 is connected to the output terminal of voltage regulator U16, and the third pin of interface CN2 is grounded.

[0012] A further technical solution is that the switching transistor Q1 is a PMOS transistor, and the switching transistors Q3 and Q6 are NMOS transistors.

[0013] A further technical solution is that the fault self-locking circuit also includes a resistor R1, a light-emitting diode LED1, and an interface CN3, wherein, The output terminal of the fault self-locking circuit is connected to the second pin of interface CN3. Interface CN3 is connected to the corresponding driver. One end of resistor R1 is connected to the output terminal of voltage regulator U16. The other end of resistor R1 is connected to the positive terminal of light-emitting diode LED1. The negative terminal of light-emitting diode LED1 is connected to the output terminal of the fault self-locking circuit.

[0014] The beneficial technical effects of this utility model are: The multi-channel pulse signal detection circuit provided by this invention performs detection from the signal input side of the driver. When any pulse signal fails, it can promptly provide feedback and shut down the isolation driver, keeping the entire isolation drive circuit in a safe off state. It has a fast response speed, high reliability, and the detection circuit is not in the power circuit, resulting in less interference. Furthermore, the overall detection circuit design is simple and low in cost. Attached Figure Description

[0015] Figure 1 This is a structural block diagram of one embodiment of the multi-channel pulse signal detection circuit provided by this utility model.

[0016] Figure 2 This is a circuit diagram of one embodiment of the three-channel signal acquisition circuit provided by this utility model.

[0017] Figure 3 This is a circuit diagram of one embodiment of the three-way comparison and judgment circuit provided by this utility model.

[0018] Figure 4 This is a circuit diagram of one embodiment of the power module provided by this utility model.

[0019] Figure 5 This is a circuit diagram of one embodiment of the three-way fault self-locking circuit provided by this utility model.

[0020] Figure 6 This is a circuit diagram of one embodiment of the reset module provided by this utility model. Detailed Implementation

[0021] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0022] This invention provides a multi-channel pulse signal detection circuit, mainly used in the technical field of power device characteristic parameter testing equipment. Related testing equipment splits a single signal (multi-channel signal source) into multiple parallel synchronous pulse signals and outputs them to each driver. Each output pulse signal reaches the driver and controls its operation. Please refer to [reference needed]. Figure 1 The multi-channel pulse signal detection circuit includes multiple detection channels, a power supply module, and a reset module. Each detection channel corresponds to multiple drivers, and each detection channel includes a signal acquisition circuit, a comparison and judgment circuit, and a fault self-locking circuit. The signal acquisition circuit is connected to the comparison and judgment circuit, the comparison and judgment circuit is connected to the fault self-locking circuit, the fault self-locking circuit is connected to the corresponding driver, the power supply module is connected to the signal acquisition circuit, the comparison and judgment circuit and the fault self-locking circuit, and the reset module is connected to the power supply module. Each of the plurality of drivers receives a pulse signal. In any detection channel, the signal acquisition circuit generates a logic signal based on the pulse signal received by the corresponding driver. The comparison and judgment circuit generates a fault signal based on the logic signal and the calibration signal. When the fault signal is at a valid level, it is used to control the corresponding driver to stop output through a fault self-locking circuit. The power supply module supplies power to the signal acquisition circuit, the comparison and judgment circuit, the fault self-locking circuit, and the reset module. The reset module resets the fault self-locking circuit and releases the self-locking state after a fault occurs and is handled.

[0023] Specifically, this embodiment includes three signal detection channels. The number of signals detected depends on the number of drivers being detected. The following section uses one of these signal detection channels as an example to explain the specific structure and working principle of the signal acquisition circuit, comparison and judgment circuit, and fault self-locking circuit. Please refer to [link / reference]. Figure 2 The signal acquisition circuit includes interface U3, capacitors C1, C2, C3, C4, C5, C6, and C7, resistors R2, R3, R4, R5, R6, and R7, resistor RF1, operational amplifier U4, and comparator U2, wherein the comparator U2 may be an LM393DR. The interface U3 is connected to one end of the capacitor C6, the other end of the capacitor C6 is connected to one end of the resistor R7 and one end of the resistor R6, the other end of the resistor R6 is connected to one end of the capacitor C7 and the non-inverting input terminal of the operational amplifier U4, and the other end of the resistor R7 and the other end of the capacitor C7 are grounded. One end of resistor R5 is connected to one end of resistor RF1, one end of capacitor C1, and the inverting input of operational amplifier U4. The other end of resistor R5 is grounded. The other ends of resistor RF1 and capacitor C1 are connected to one end of resistor R2. The other end of resistor R2 is connected to the output of operational amplifier U4. The output of operational amplifier U4 is connected to the non-inverting input (1IN+) of comparator U2. The inverting input (1IN-) of comparator U2 is connected to one end of resistor R3 and one end of resistor R4. The other end of resistor R4 is connected to the power supply module. The other end of resistor R3 is grounded. The other end of resistor R4 is also grounded through capacitor C2. The output (1OUT) of comparator U2 serves as the output of the signal acquisition circuit. Capacitors C3, C4, and C5 are connected in parallel with capacitor C2. The power supply terminals (VCC) of comparator U2 and operational amplifier U4 are connected to the power supply module. The ground terminals (GND) of comparator U2 and operational amplifier U4 are grounded.

[0024] The operational amplifier circuit, consisting of operational amplifier U4, resistors R2, RF, R5, and R6, amplifies the pulse signal and outputs it to the comparator. The power supply module provides a +5V voltage to the comparator. Resistors R4 and R3 divide the +5V voltage. Comparator U2 uses the voltage divided by resistors R4 and R3 as a reference voltage and compares it with the amplified pulse signal before outputting a logic level (logic signal).

[0025] Further, please refer to Figure 3 The comparison and judgment circuit includes an XNOR gate U15, a comparator U18, resistors R28, R29, R30, and R33, and capacitors C28, C29, C30, C31, and C32. The comparator U18 can also be an LM393DR. The comparison and judgment circuit in the multi-channel detection channel can use a multi-channel XNOR gate. In this embodiment, the three-channel comparison and judgment circuit uses a three-channel XNOR gate U15. The first, second, and output terminals of the XNOR gate U15 mentioned below refer to the first, second, and output terminals of the first XNOR gate in the three-channel XNOR gate U15.

[0026] The first input terminal (1A) of the XNOR gate U15 is connected to the output terminal of the signal acquisition circuit. The second input terminal (1B) of the XNOR gate U15 is connected to the calibration signal. The output terminal (1Y) of the XNOR gate U15 is connected to the non-inverting input terminal (1IN+) of the comparator U18 through resistor R33. The non-inverting input terminal (1IN+) of the comparator U18 is grounded through capacitor C28. The inverting input terminal (1IN-) of the comparator U18 is connected to one end of resistor R30 and one end of resistor R29.

[0027] The other end of resistor R29 is grounded, the other end of resistor R30 is connected to the power module (connected to +5V voltage), the other end of resistor R30 is also grounded through capacitor C29, capacitors C30, C31, and C32 are connected in parallel with capacitor C29, the output terminal (1OUT) of comparator U18 is connected to one end of resistor R28, and the other end of resistor R28 serves as the output terminal of the comparison judgment circuit.

[0028] The calibration signal can be provided by a microcontroller. The calibration signal maintains the same level as the correct pulse signal. The logic signal output from the signal acquisition circuit is output to the first input of the XOR gate U15, and the calibration signal is input to the second input of the XOR gate U15. When the logic signal and the calibration signal are both high / low level, the pulse signal is fault-free, and the XOR gate U15 outputs a high-level signal. The signal output by the XOR gate U15 is output to the comparator U18. The comparator U18 uses the voltage obtained by dividing the voltage of resistor R30 and resistor R29 as the reference voltage. When the XOR gate outputs a high-level signal, the comparator U18 outputs an invalid level (high level) fault signal. Conversely, when the logic signal and the calibration signal are not high / low level, the pulse signal is faulty, and the XOR gate U15 outputs a low-level signal. The signal output by the XOR gate U15 is output to the comparator U18, and the comparator U18 outputs a valid level (low level) fault signal (FAULT).

[0029] Further, please refer to Figure 4 The power module includes an interface CN1, a fuse F1, a Schottky diode D1, a capacitor C25, a voltage regulator U16, and a voltage regulator U17. The second pin of the interface CN1 is connected to one end of the fuse F1. The other end of the fuse F1 is connected to the negative terminal of the Schottky diode D1, one end of the capacitor C25, and the input terminal of the voltage regulator U16. The other end of the capacitor C25 and the positive terminal of the Schottky diode are grounded. The input terminal of the voltage regulator U16 is grounded through a capacitor C23, and the output terminal of the voltage regulator U16 is grounded through a capacitor C26. The output terminal of the voltage regulator U16 is connected to a signal acquisition module and a comparison and judgment module. The input terminal of the voltage regulator U17 is connected to a reset module, and the input terminal of the voltage regulator U17 is grounded through a capacitor C24. The output terminal of the voltage regulator U17 is grounded through a capacitor C27. The +12V external power supply voltage (VCC) is connected to the power module through interface CN1 and converted to +5V by voltage regulator U16 and applied to the power supply terminals of the aforementioned operational amplifier U4, comparator U2, XNOR gate U15, and comparator U18.

[0030] Further, please refer to Figure 5 The fault self-locking circuit includes resistors R26, R31, R34, and R35, switching transistor Q1, and switching transistor Q3, wherein... One end of resistor R26 is connected to the output of voltage regulator U17 in the power module. The other end of resistor R26 is connected to the first electrode of switching transistor Q1. The second electrode of switching transistor Q1 is connected to the third electrode of switching transistor Q3, one end of resistor R31, and one end of resistor R34. The other end of resistor R31 is connected to the output of the comparison and judgment circuit. The other end of resistor R34 and the first electrode of switching transistor Q3 are grounded. The second electrode of switching transistor Q3, the third electrode of switching transistor Q1, and one end of resistor R35 are connected and serve as the output of the fault self-locking circuit. The other end of resistor R35 is grounded. The fault self-locking circuit also includes resistor R1, light-emitting diode LED1, and interface CN3. The output of the fault self-locking circuit is connected to the second pin of interface CN3. Interface CN3 is connected to the corresponding driver, specifically to the enable pin of the driver. One end of resistor R1 is connected to the output of voltage regulator U16. The other end of resistor R1 is connected to the positive terminal of light-emitting diode LED1. The negative terminal of light-emitting diode LED1 is connected to the output of the fault self-locking circuit.

[0031] In this embodiment, switch Q1 is a PMOS transistor and switch Q3 is an NMOS transistor. For both PMOS and NMOS transistors, the first electrode is the source, the second electrode is the gate, and the third electrode is the drain. When there is no fault in the pulse signal, the fault signal (FAULT) is a high-level signal. At this time, the fault self-locking circuit outputs a low-level control signal (DRIVE), the driver outputs normally, and the light-emitting diode LED1 lights up. When there is a fault in the pulse signal, the fault signal (FAULT) is a low-level signal. At this time, the gate-source voltage difference of PMOS transistor Q1 is greater than the threshold voltage, so PMOS transistor Q1 is turned on. After PMOS transistor Q1 is turned on, resistor R35 divides the input 5V voltage, making the gate-source voltage difference of NMOS transistor Q3 greater than the threshold voltage, so NMOS transistor Q3 is turned on. Resistor R34 keeps PMOS transistor in a constantly conducting state, so NMOS transistor Q3 remains in a conducting state, that is, it reaches the self-locking state. At this time, the fault self-locking circuit outputs a high-level control signal (DRIVE), controlling the driver to stop outputting, and the light-emitting diode LED1 is turned off to indicate the fault state.

[0032] Furthermore, the reset module is used to reset the fault self-locking circuit, such as... Figure 6 As shown, the reset module includes resistor R44, resistor R45, switching transistor Q6, and interface CN2, wherein, One end of resistor R44 is connected to the second pin of interface CN2, the other end of resistor R44 is connected to one end of resistor R45 and the second electrode of switching transistor Q6, the third electrode of switching transistor Q6 is connected to the input terminal of voltage regulator U16, the first electrode of switching transistor Q6 is connected to the input terminal of voltage regulator U17, the other end of resistor R45 is grounded, the first pin of interface CN2 is connected to the output terminal of voltage regulator U16, and the third pin of interface CN2 is grounded.

[0033] In this embodiment, the switching transistor Q6 is an NMOS transistor. The definitions of the first to third electrodes of the NMOS transistor are the same as described above and will not be repeated here. The reset module achieves the function of releasing the self-locking circuit, i.e., resetting the self-locking circuit, by controlling the power supply state of the fault self-locking circuit. Specifically, the +12V external power supply voltage is connected to the voltage regulator U17 through the switching transistor Q6. During normal operation, the second pin of interface CN2 is shorted by a jumper cap to the +5V power supply provided by the voltage regulator U16 (connected to the first pin of CN2). At this time, the NMOS transistor Q6 is in the conducting state, and the +12V external power supply voltage can be provided to the voltage regulator U17 through the NMOS transistor. The voltage regulator U17 converts the +12V voltage to +5V voltage and provides it to the fault self-locking circuit. When it is necessary to release the self-locking circuit through the reset circuit, the second pin of interface CN2 is grounded by a jumper cap (connected to the third pin of CN2). At this time, the NMOS transistor Q6 is turned off, the voltage regulator U17 loses its input voltage, stops supplying power to the fault self-locking circuit, and thus releases the self-locking state.

[0034] In summary, the multi-channel pulse signal detection circuit provided by this utility model detects signals from the signal input side of the driver. When any pulse signal fails, it can promptly provide feedback and shut down the isolation driver, keeping the entire isolation drive circuit in a safe off state. It has a fast response speed, high reliability, and the detection circuit is not in the power circuit, resulting in less interference. Furthermore, the overall detection circuit design is simple and low in cost.

[0035] In the description of this specification, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0036] The use of terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example, which is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0037] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A multi-channel pulse signal detection circuit, characterized in that, It includes multiple detection channels, a power module, and a reset module. The multiple detection channels correspond one-to-one with multiple drivers. Each detection channel includes a signal acquisition circuit, a comparison and judgment circuit, and a fault self-locking circuit. The signal acquisition circuit is connected to the comparison and judgment circuit, the comparison and judgment circuit is connected to the fault self-locking circuit, the fault self-locking circuit is connected to the corresponding driver, the power supply module is connected to the signal acquisition circuit, the comparison and judgment circuit and the fault self-locking circuit, and the reset module is connected to the power supply module. Each of the plurality of drivers receives a pulse signal. In any detection channel, the signal acquisition circuit is used to generate a logic signal based on the pulse signal received by the corresponding driver. The comparison and judgment circuit is used to generate a fault signal based on the logic signal and the calibration signal. When the fault signal is at an active level, it is used to control the corresponding driver to stop output through a fault self-locking circuit.

2. The multi-channel pulse signal detection circuit according to claim 1, characterized in that, The signal acquisition circuit includes interface U3, capacitors C1, C2, C3, C4, C5, C6, and C7, resistors R2, R3, R4, R5, R6, and R7, resistor RF1, operational amplifier U4, and comparator U2. The interface U3 is connected to one end of the capacitor C6, the other end of the capacitor C6 is connected to one end of the resistor R7 and one end of the resistor R6, the other end of the resistor R6 is connected to one end of the capacitor C7 and the non-inverting input terminal of the operational amplifier U4, and the other end of the resistor R7 and the other end of the capacitor C7 are grounded. One end of resistor R5 is connected to one end of resistor RF1, one end of capacitor C1, and the inverting input terminal of operational amplifier U4. The other end of resistor R5 is grounded. The other ends of resistor RF1 and capacitor C1 are connected to one end of resistor R2. The other end of resistor R2 is connected to the output terminal of operational amplifier U4.

3. The multi-channel pulse signal detection circuit according to claim 2, characterized in that, The output terminal of the operational amplifier U4 is connected to the non-inverting input terminal of the comparator U2. The inverting input terminal of the comparator U2 is connected to one end of resistor R3 and one end of resistor R4. The other end of resistor R4 is connected to the power supply module. The other end of resistor R3 is grounded. The other end of resistor R4 is also grounded through capacitor C2. The output terminal of the comparator U2 serves as the output terminal of the signal acquisition circuit. Capacitors C3, C4, and C5 are connected in parallel with capacitor C2.

4. The multi-channel pulse signal detection circuit according to claim 3, characterized in that, The comparison and judgment circuit includes an XNOR gate U15, a comparator U18, resistors R28, R29, R30, and R33, and capacitors C28, C29, C30, C31, and C32. The first input terminal of the XNOR gate U15 is connected to the output terminal of the signal acquisition circuit. The second input terminal of the XNOR gate U15 is connected to the calibration signal. The output terminal of the XNOR gate U15 is connected to the non-inverting input terminal of the comparator U18 through resistor R33. The non-inverting input terminal of the comparator U18 is grounded through capacitor C28. The inverting input terminal of the comparator U18 is connected to one end of resistor R30 and one end of resistor R29.

5. The multi-channel pulse signal detection circuit according to claim 4, characterized in that, The other end of resistor R29 is grounded, the other end of resistor R30 is connected to the power module, the other end of resistor R30 is also grounded through capacitor C29, capacitors C30, C31, and C32 are connected in parallel with capacitor C29, the output of comparator U18 is connected to one end of resistor R28, and the other end of resistor R28 serves as the output of the comparison judgment circuit.

6. The multi-channel pulse signal detection circuit according to claim 5, characterized in that, The power module includes an interface CN1, a fuse F1, a Schottky diode D1, a capacitor C25, a voltage regulator U16, and a voltage regulator U17, wherein... The second pin of the interface CN1 is connected to one end of the fuse F1. The other end of the fuse F1 is connected to the negative terminal of the Schottky diode D1, one end of the capacitor C25, and the input terminal of the voltage regulator U16. The other end of the capacitor C25 and the positive terminal of the Schottky diode are grounded. The input terminal of the voltage regulator U16 is grounded through the capacitor C23. The output terminal of the voltage regulator U16 is grounded through the capacitor C26. The output terminal of the voltage regulator U16 is connected to the signal acquisition module and the comparison and judgment module. The input terminal of voltage regulator U17 is connected to the reset module. The input terminal of voltage regulator U17 is grounded through capacitor C24, and the output terminal of voltage regulator U17 is grounded through capacitor C27.

7. The multi-channel pulse signal detection circuit according to claim 6, characterized in that, The fault self-locking circuit includes resistors R26, R31, R34, and R35, switching transistor Q1, and switching transistor Q3, wherein... One end of resistor R26 is connected to the output terminal of voltage regulator U17 in the power module. The other end of resistor R26 is connected to the first electrode of switching transistor Q1. The second electrode of switching transistor Q1 is connected to the third electrode of switching transistor Q3, one end of resistor R31, and one end of resistor R34. The other end of resistor R31 is connected to the output terminal of the comparison and judgment circuit. The other end of resistor R34 and the first electrode of switching transistor Q3 are grounded. The second electrode of switching transistor Q3, the third electrode of switching transistor Q1, and one end of resistor R35 are connected and serve as the output terminal of the fault self-locking circuit. The other end of resistor R35 is grounded.

8. The multi-channel pulse signal detection circuit according to claim 7, characterized in that, The reset module is used to reset the fault-locking circuit. The reset module includes resistor R44, resistor R45, switching transistor Q6, and interface CN2. One end of resistor R44 is connected to the second pin of interface CN2, the other end of resistor R44 is connected to one end of resistor R45 and the second electrode of switching transistor Q6, the third electrode of switching transistor Q6 is connected to the input terminal of voltage regulator U16, the first electrode of switching transistor Q6 is connected to the input terminal of voltage regulator U17, the other end of resistor R45 is grounded, the first pin of interface CN2 is connected to the output terminal of voltage regulator U16, and the third pin of interface CN2 is grounded.

9. The multi-channel pulse signal detection circuit according to claim 8, characterized in that, The switching transistor Q1 is a PMOS transistor, and the switching transistors Q3 and Q6 are NMOS transistors.

10. The multi-channel pulse signal detection circuit according to claim 6, characterized in that, The fault self-locking circuit also includes a resistor R1, a light-emitting diode LED1, and an interface CN3, wherein... The output terminal of the fault self-locking circuit is connected to the second pin of interface CN3. Interface CN3 is connected to the corresponding driver. One end of resistor R1 is connected to the output terminal of voltage regulator U16. The other end of resistor R1 is connected to the positive terminal of light-emitting diode LED1. The negative terminal of light-emitting diode LED1 is connected to the output terminal of the fault self-locking circuit.

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