A new industrial control mainboard
Patent Information
- Application Number
- CN202522537259.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-10-13
- Estimated Expiration
- 2035-11-28
AI Technical Summary
[0005]本申请的目的在于提供一种新型工控主板，其解决了现有技术中存在的自主可控性不足、接口协议兼容性局限、故障诊断效率低等技术问题
[0034]1.本实用新型采用国产飞腾FT-2000/4四核处理器与安路EG4系列FPGA芯片构成的多核协同架构，关键器件包括DDR4 ECC内存、SPI Nor Flash存储器等均选用国产型号，规避了进口x86架构处理器与国外接口芯片的供应链风险及技术壁垒，实现了从处理器到外围电路的自主可控。FT-2000/4四核处理器架构与安路FPGA的硬件可重构逻辑相结合，无需依赖国外EDA工具链即可完成全链路开发与验证，满足能源、轨道交通、智能制造等关键基础设施领域的安全自主要求；
Smart Images
Figure CN224851492U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of industrial control motherboard technology, and more specifically, to a novel industrial control motherboard. Background Technology
[0002] Industrial control boards (ICBs) are the core hardware platform of industrial automation systems. By integrating processors, memory, signal acquisition units, and communication interfaces, ICBs enable parallel data acquisition from field sensors or other devices, real-time control logic operations, multi-protocol data conversion, and high-speed interconnection between devices. In critical infrastructures such as smart manufacturing, rail transportation, and smart grids, ICBs must meet requirements for long-term continuous operation, wide-temperature operation, and high reliability in strong electromagnetic environments. Their performance directly determines the stability and security of the entire industrial control system.
[0003] In existing technologies, industrial control boards generally adopt imported processors and commercial chipsets based on the x86 architecture, along with signal conditioning circuits with fixed parameters. When acquiring analog signals, traditional motherboards use fixed-gain amplifiers and single resistors and capacitors for signal conditioning; in terms of communication interfaces, they mostly use dedicated protocol cards with external slots to achieve industrial bus support; in terms of fault diagnosis, intermittent faults are located through software log recording and manual replacement of spare parts.
[0004] However, existing main control boards generally lack independent controllability. Key components such as processors and interface chips mostly rely on imported x86 architecture or foreign brands. Due to restrictions from the international supply chain and technical barriers, they cannot meet the independent needs of the industrial sector. In addition, most existing motherboards only support a single industrial bus protocol, requiring additional adapter modules to connect to different types of industrial equipment such as CAN FD, EtherCAT, and Profinet, which is cumbersome and increases costs. Utility Model Content
[0005] The purpose of this application is to provide a new type of industrial control motherboard, which solves the technical problems existing in the prior art, such as insufficient independent controllability, limited interface protocol compatibility, and low fault diagnosis efficiency.
[0006] To solve the above-mentioned technical problems, the solution adopted in this application is as follows:
[0007] A new type of industrial control motherboard includes a control module, a signal transmission module, and a multi-protocol interface module;
[0008] The control module includes a processor and an FPGA chip. The processor is a Phytium FT-2000 / 4 quad-core processor, and the FPGA chip is an Anlu EG4S20BG256. The signal transceiver port of the processor is connected to the FPGA chip through TX and RX differential lines.
[0009] The multi-protocol module is integrated into the industrial control motherboard and includes a CAN FD bus controller, an EtherCAT bus controller, a Profinet bus controller, a network port chip, a USB interface, and a PCIe slot.
[0010] The EtherCAT bus controller is connected to the first GPIO pin group of the FPGA chip via the data bus, address bus and interrupt request INT pin respectively.
[0011] The data bus pins, address bus pins, and control bus pins of the Profinet bus controller are respectively connected to the second GPIO pin group of the FPGA chip.
[0012] The RGMII interface pins of the network port chip are electrically connected to the dedicated I / O pin group of the network port chip of the FPGA chip.
[0013] The UTMI pin and interface pin of the USB interface are electrically connected to the USB3.0 PHY hard core of the FPGA, respectively.
[0014] The transmit differential pin of the PCIe slot is electrically connected to the receive pin of the processor's PCIe 4.0 controller; the receive differential pin of the PCIe slot is electrically connected to the transmit pin of the processor's PCIe 4.0 controller.
[0015] Preferably, the novel industrial control motherboard further includes a signal transmission module;
[0016] The signal port of the control module is electrically connected to the signal port of the signal transmission module; the signal transmission port of the signal transmission module is electrically connected to the signal port of the multi-protocol interface module.
[0017] The signal transmission module includes a differential analog input channel, a gain amplifier, an ADC chip, a magnetic isolation chip, and an optocoupler isolation chip.
[0018] The differential signal input terminal of the gain amplifier is connected to the differential signal output terminal of the differential analog input channel; the differential signal output terminal of the gain amplifier is connected to the differential signal input terminal of the magnetic isolation chip; the differential signal output terminal of the magnetic isolation chip is connected to the differential signal input terminal of the optocoupler isolation chip; the signal output terminal of the optocoupler isolation chip is connected to the AD input pin of the ADC chip; the AD output pin of the ADC chip is connected to the signal input pin of the processor.
[0019] The gain configuration pins of the gain amplifier include the SCLK pin, SDI pin, and CS pin, which are electrically connected to the processor's SPI controller pins SPICLK pin, SPIMOSI pin, and SPICS1 pin respectively via the SPI bus.
[0020] Preferably, the processor is connected to DDR4 ECC memory via its DDR4 controller; the processor is connected to a PCIe 4.0 NVMe solid-state drive interface via its PCIe 4.0 controller; and the processor is connected to SPI Nor Flash memory via its SPI controller.
[0021] The DDR4 ECC memory is electrically connected to the processor's DDR4 controller via a data bus, an ECC verification bus, an address bus, and control signal lines, forming an ECC memory channel.
[0022] The PCIe 4.0 NVMe solid-state drive interface is electrically connected to the processor's PCIe 4.0 controller via TX and RX differential signal lines;
[0023] The SPI Nor Flash memory is electrically connected to the processor's SPI controller via a data bus, clock line CLK, and chip select line CS.
[0024] Preferably, the parallel data bus pin, address bus pin, chip select pin, read enable pin, and write enable pin of the CAN FD bus controller are respectively connected to the GPIO pins of the FPGA chip;
[0025] The EtherCAT bus controller is connected to the GPIO pins of the FPGA chip via the data bus, address bus, and interrupt request INT pin, respectively.
[0026] The data bus pins, address bus pins, and control bus pins of the Profinet bus controller are respectively connected to the GPIO pins of the FPGA chip;
[0027] The RGMII interface pins of the network port chip are connected to the dedicated network port IO pins of the FPGA chip.
[0028] The UTMI pin and interface pin of the USB interface are respectively connected to the USB3.0 PHY hard core of the FPGA.
[0029] The transmit differential pin of the PCIe slot is connected to the receive pin of the processor's PCIe 4.0 controller; the receive differential pin of the PCIe slot is connected to the transmit pin of the processor's PCIe 4.0 controller.
[0030] Preferably, the industrial control motherboard further includes an industrial control board fault monitoring module; the industrial control board fault monitoring module includes a second ADC chip and an alarm buzzer;
[0031] The I2C pin of the second ADC chip is connected to the I2C control pin of the FPGA chip; the analog input pin of the second ADC chip is connected to the core voltage sampling point, power output voltage sampling point, bus signal amplitude sampling point and temperature sensor output terminal of the processor respectively; the control signal output pin of the second ADC chip is connected to the control signal input terminal of the alarm buzzer.
[0032] Preferably, the novel industrial control motherboard further includes a power supply module; the power output terminal of the power supply module is connected to the power input terminals of the control module, signal transmission module, multi-protocol interface module, and fault monitoring module.
[0033] The technical solution of this application has at least the following advantages and beneficial effects:
[0034] 1. This utility model adopts a multi-core collaborative architecture composed of a domestically produced Phytium FT-2000 / 4 quad-core processor and Anlogic EG4 series FPGA chips. Key components, including DDR4 ECC memory and SPI Nor Flash memory, are all domestically produced, avoiding the supply chain risks and technical barriers of imported x86 architecture processors and foreign interface chips, and achieving independent control from the processor to the peripheral circuits. The combination of the FT-2000 / 4 quad-core processor architecture and the hardware reconfigurable logic of Anlogic FPGAs allows for end-to-end development and verification without relying on foreign EDA toolchains, meeting the security and self-reliance requirements of critical infrastructure fields such as energy, rail transportation, and intelligent manufacturing.
[0035] 2. This utility model integrates three industrial bus controllers (CAN FD, EtherCAT, and Profinet) along with four network ports and two interface ports at the FPGA chip hardware level. It eliminates the traditional industrial control motherboard model that relies on external protocol cards via PCI / PCIe slots, enabling multi-protocol device interconnection on a single board. This design allows a single motherboard to interface with various types of devices such as industrial robots, drives, PLCs, and vision cameras without the need for adapter modules. It achieves higher integration, lower hardware costs, and solves the compatibility issues of existing motherboards, which suffer from single-protocol limitations and cumbersome expansion requirements. Attached Figure Description
[0036] Figure 1 This is a structural topology diagram of the industrial control motherboard in this utility model. Detailed Implementation
[0037] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0038] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. The terms "center," "upper," "lower," "inner," and "outer," indicating orientation or positional relationships based on the orientation or positional relationships shown in the figures, or the orientation or positional relationships commonly used when the product is in use, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and therefore should not be construed as a limitation on this application. It should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," and "connect" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0039] A novel industrial control motherboard includes a control module, a signal transmission module, a multi-protocol interface module, and an industrial control board fault monitoring module;
[0040] The signal ports of the control module and the signal ports of the signal transmission module are electrically connected; the signal transmission port of the signal transmission module and the signal transmission port of the multi-protocol interface module are electrically connected; the signal monitoring terminal of the industrial control board fault monitoring module is connected to the monitored terminals of the control module, the signal transmission module, and the multi-protocol interface module, respectively.
[0041] The control module is a central processing unit that works in conjunction with the signal transmission module, the multi-protocol interface module, and the industrial control board fault monitoring module to integrate an industrial control system that would otherwise require multiple boards onto a single motherboard.
[0042] In this embodiment, the control module adopts a multi-core collaborative architecture of processor and FPGA chip. The control module includes a processor, FPGA chip, memory, hard disk interface, and Flash memory; the memory is DDR4 ECC memory, the hard disk interface is a PCIe 4.0 NVMe solid-state drive interface, and the Flash memory is SPI Nor Flash memory; this achieves functional separation of main control and real-time signal processing, while avoiding dependence on imported technology. The processor is responsible for industrial control logic operations, protocol stack processing, etc.; the FPGA chip is responsible for parallel acquisition and real-time preprocessing of multiple industrial signals.
[0043] The processor's signal transceiver port is connected to the FPGA chip's signal transceiver port through 4 pairs of TX and RX differential lines; each pair of TX and RX differential lines has a channel bandwidth of 8GT / S, and the total bandwidth of the 4 pairs of TX and RX differential lines is 32GT / S;
[0044] DDR4 ECC memory is electrically connected to the processor's DDR4 controller via a 64-bit data bus, a 16-bit ECC check bus, an 18-bit address bus, and control signal lines, forming a total of 80-bit ECC memory channels (64+16). DDR4 ECC memory provides memory space for the industrial control board.
[0045] The PCIe 4.0 NVMe solid-state drive interface is electrically connected to the processor's PCIe 4.0 controller via four sets of TX and RX differential signal lines; each set of differential signal lines has a channel rate of 16GT / s, for a total bandwidth of 64GT / s.
[0046] The SPI Nor Flash memory is electrically connected to the processor's SPI controller via a 4-bit data bus (DQ0-DQ3), clock line CLK, and chip select line CS. The SPI Nor Flash memory is used for firmware storage, storing basic configuration parameters and other data of the industrial control board.
[0047] In this embodiment, the memory used is a DDR4 ECC memory with the model number Changxin Memory CXDQ3A8AM-WG, and the capacity is configurable from 4GB to 32GB.
[0048] In this embodiment, the Flash memory is model GigaDevice GD25B256E with a capacity of 256Mb, used to store UEFI firmware and configuration parameters.
[0049] The processor used in this embodiment is the domestic Phytium FT-2000 / 4 quad-core processor, and its technical specifications are shown in Table 1:
[0050] Table 1. Technical Specifications of Phytium FT-2000 / 4 Quad-Core Processor
[0051]
[0052]
[0053] The FPGA chip used in this embodiment is the Anlu EG4 series FPGA chip, and its technical specifications are shown in Table 2:
[0054] Table 2 FPGA Chip Technical Specifications
[0055]
[0056] In this embodiment, the signal transmission module includes a differential analog input channel, a gain amplifier, an ADC chip, a magnetic isolation chip, an optocoupler isolation chip, and a temperature sensor;
[0057] The differential analog input channel supports 0-10V voltage and 4-20mA current signal input; the gain amplifier is used for signal conditioning; the magnetic isolation chip and optocoupler isolation chip form a double isolation barrier to isolate external interference such as electromagnetic interference; the ADC chip is used for analog-to-digital conversion; the temperature sensor is used to monitor the chip junction temperature in real time; the entire signal transmission module is used to process and transmit signals from the input / output industrial control board.
[0058] The system has 16 differential analog input channels. The differential signal output of each analog input channel is connected to the differential signal input of a gain amplifier; the differential signal output of the gain amplifier is connected to the differential signal input of a magnetic isolation chip; the differential signal output of the magnetic isolation chip is connected to the differential signal input of an optocoupler isolation chip; the signal output of the optocoupler isolation chip is connected to the AD input pin of the ADC chip; and the AD output pin of the ADC chip is connected to the input pin of the processor.
[0059] The gain configuration pins of the gain amplifier include the SCLK pin, SDI pin, and CS pin, which are electrically connected to the processor's SPI controller pins SPICLK pin, SPIMOSI pin, and SPICS1 pin respectively via the SPI bus, so as to enable the processor to configure the gain of the gain amplifier.
[0060] The temperature sensor's SPI interface pins, including the SCK, CS, and SO pins, are connected to the GPIO pins of the FPGA chip to transmit temperature data to the FPGA chip via the SPI interface.
[0061] In this embodiment, the gain amplifier is model SGM8421; its technical specifications are shown in Table 3:
[0062] Gain range 1-128 times bandwidth 10MHz@-3dB Gain error ±0.5% (when G=1) Input offset voltage ±50uV Operating temperature -40℃-125℃ Packaging MSOP-10
[0063] In this embodiment, the magnetic isolation chip is model CSA8740 from Chuantu Microelectronics, with an isolation voltage of 3000Vdc and a common-mode transient immunity of ±kV / us; the optocoupler isolation chip is model 6N137, with an isolation voltage of 2500Vdc; and the temperature sensor is model MAX6675, with a temperature measurement range of 0℃-1024℃.
[0064] In this embodiment, the ADC chip model is AD9240; its technical specifications are shown in Table 3:
[0065] resolution 16-bit Sampling rate 1MSps Signal-to-noise ratio (SNR) 86dB@1MSps Differential nonlinear error ±1LSB Integral nonlinearity error ±3LSB Operating temperature -40℃-85℃ Packaging LOFP-48
[0066] In this embodiment, the multi-protocol module is integrated into the industrial control motherboard. The multi-protocol interface module includes a CAN FD bus controller, an EtherCAT bus controller, a Profinet bus controller, a network port chip, a USB interface, and a PCIe slot.
[0067] Among them, the multi-protocol interface module serves as the connection hub between the industrial control board and external devices, networks, and expansion cards. This module integrates various industrial bus controllers and high-speed communication interfaces, enabling interconnection with other devices, real-time data interaction, and functional expansion in various scenarios.
[0068] The parallel data bus pin, address bus pin, chip select pin, read enable pin, and write enable pin of the CAN FD bus controller are connected to the GPIO pins of the FPGA chip, respectively, to realize the burst transmission of the protocol through the 16-bit parallel bus;
[0069] The EtherCAT bus controller is connected to the GPIO pins of the FPGA chip via the data bus, address bus, and interrupt request INT pin, respectively, and the hardware acceleration logic of the EtherCAT bus controller is implemented through the FPGA.
[0070] The data bus pins, address bus pins, and control bus pins of the Profinet bus controller are connected to the GPIO pins of the FPGA chip, and the Profinet protocol stack is implemented through the FPGA.
[0071] The RGMII interface pins of the network port chip are connected to the dedicated network port IO pins of the FPGA chip. The network port chip provides standard Ethernet connectivity to the industrial control board and supports link aggregation and redundant communication.
[0072] The UTMI pin and interface pins of the USB interface are connected to the USB 3.0 PHY hard core of the FPGA. The USB interface provides USB connectivity and expansion capabilities for the industrial control board, supporting peripherals such as USB flash drives, touch screens, and debugging tools.
[0073] The PCIe slot's transmit differential pins are connected to the processor's PCIe 4.0 controller's receive pins; the PCIe slot's receive differential pins are connected to the processor's PCIe 4.0 controller's transmit pins; the PCIe slot provides high-speed expansion capabilities for industrial control boards, supporting expansion devices such as AI accelerator cards, GPUs, and high-speed acquisition cards;
[0074] The various components of the multi-protocol interface module implement hardware-level protocol conversion and data routing through FPGA chips. Specifically, the parallel data buses of the CAN FD bus controller, EtherCAT bus controller, and Profinet bus controller are buffered inside the FPGA and then uniformly packaged and transmitted to the processor via the PCIe 4.0 x16 bus; the FPGA chip extracts the processor system clock from the PCIe bus, divides it, and outputs it to the EtherCAT bus controller to synchronize the protocol clock with the system clock.
[0075] In this embodiment, the industrial control board fault monitoring module includes a second ADC chip and an alarm buzzer. The industrial control board fault monitoring module monitors the status of the industrial control board in real time, and when a motherboard fault is detected, it outputs a control signal to control the buzzer to sound an alarm.
[0076] The I2C pin of the second ADC chip is connected to the I2C control pin of the FPGA chip; the analog input pin of the second ADC chip is connected to the core voltage sampling point, power output voltage sampling point, bus signal amplitude sampling point and temperature sensor output terminal of the processor, respectively; the control signal output pin of the second ADC chip is connected to the control signal input terminal of the alarm buzzer; the core voltage, power output voltage, bus signal amplitude and industrial control board temperature of the processor are monitored respectively, and the alarm buzzer is controlled to sound an alarm when the parameters of the industrial control board are abnormal.
[0077] In this embodiment, the industrial control motherboard also includes a power module. The power output terminal of the power module is connected to the power input terminals of the control module, signal transmission module, multi-protocol interface module, and industrial control board fault monitoring module, respectively, to supply power to them and ensure their normal operation.
[0078] It should be noted that all the electronic devices mentioned in the above embodiments are available in domestic and international markets.
[0079] The various embodiments of this utility model have now been described in detail. To avoid obscuring the concept of this utility model, some details known in the art have not been described. Those skilled in the art will fully understand how to implement the technical solution of this utility model based on the above description. The scope of this utility model is defined by the appended claims.
Claims
1. A novel industrial control motherboard, characterized in that: Includes a control module and a multi-protocol interface module; The control module includes a processor and an FPGA chip. The processor is a Phytium FT-2000 / 4 quad-core processor, and the FPGA chip is an Anlu EG4S20BG256. The signal transceiver port of the processor is connected to the FPGA chip through TX and RX differential lines. The multi-protocol interface module is integrated into the industrial control motherboard and includes a CAN FD bus controller, an EtherCAT bus controller, a Profinet bus controller, a network chip, a USB interface, and a PCIe slot. The EtherCAT bus controller is connected to the first GPIO pin group of the FPGA chip via the data bus, address bus and interrupt request INT pin respectively. The data bus pins, address bus pins, and control bus pins of the Profinet bus controller are respectively connected to the second GPIO pin group of the FPGA chip. The RGMII interface pins of the network port chip are electrically connected to the dedicated I / O pin group of the network port chip of the FPGA chip. The UTMI pin and interface pin of the USB interface are electrically connected to the USB3.0 PHY hard core of the FPGA, respectively. The transmit differential pin of the PCIe slot is electrically connected to the receive pin of the processor's PCIe 4.0 controller; the receive differential pin of the PCIe slot is electrically connected to the transmit pin of the processor's PCIe 4.0 controller.
2. The novel industrial control motherboard according to claim 1, characterized in that, The new industrial control motherboard also includes a signal transmission module; The signal port of the control module is electrically connected to the signal port of the signal transmission module; the signal transmission port of the signal transmission module is electrically connected to the signal port of the multi-protocol interface module. The signal transmission module includes a differential analog input channel, a gain amplifier, an ADC chip, a magnetic isolation chip, and an optocoupler isolation chip. The differential signal input terminal of the gain amplifier is connected to the differential signal output terminal of the differential analog input channel; the differential signal output terminal of the gain amplifier is connected to the differential signal input terminal of the magnetic isolation chip; the differential signal output terminal of the magnetic isolation chip is connected to the differential signal input terminal of the optocoupler isolation chip; the signal output terminal of the optocoupler isolation chip is connected to the AD input pin of the ADC chip; the AD output pin of the ADC chip is connected to the signal input pin of the processor. The gain configuration pins of the gain amplifier include the SCLK pin, SDI pin, and CS pin, which are electrically connected to the processor's SPI controller pins SPICLK pin, SPIMOSI pin, and SPICS1 pin respectively via the SPI bus.
3. The novel industrial control motherboard according to claim 1, characterized in that, The processor is connected to DDR4 ECC memory via its DDR4 controller; the processor is connected to a PCIe 4.0 NVMe solid-state drive interface via its PCIe 4.0 controller; the processor is connected to SPI Nor Flash memory via its SPI controller. The DDR4 ECC memory is electrically connected to the processor's DDR4 controller via a data bus, an ECC verification bus, an address bus, and control signal lines, forming an ECC memory channel. The PCIe 4.0 NVMe solid-state drive interface is electrically connected to the processor's PCIe 4.0 controller via TX and RX differential signal lines; The SPI Nor Flash memory is electrically connected to the processor's SPI controller via a data bus, clock line CLK, and chip select line CS.
4. A novel industrial control motherboard according to claim 1, characterized in that, The parallel data bus pin, address bus pin, chip select pin, read enable pin, and write enable pin of the CAN FD bus controller are respectively connected to the GPIO pins of the FPGA chip; The EtherCAT bus controller is connected to the GPIO pins of the FPGA chip via the data bus, address bus, and interrupt request INT pin, respectively. The data bus pins, address bus pins, and control bus pins of the Profinet bus controller are respectively connected to the GPIO pins of the FPGA chip; The RGMII interface pins of the network port chip are connected to the dedicated network port IO pins of the FPGA chip. The UTMI pin and interface pin of the USB interface are respectively connected to the USB3.0 PHY hard core of the FPGA. The transmit differential pin of the PCIe slot is connected to the receive pin of the processor's PCIe 4.0 controller; the receive differential pin of the PCIe slot is connected to the transmit pin of the processor's PCIe 4.0 controller.
5. A novel industrial control motherboard according to claim 2, characterized in that, The industrial control motherboard also includes an industrial control board fault monitoring module; the industrial control board fault monitoring module includes a second ADC chip and an alarm buzzer. The I2C pin of the second ADC chip is connected to the I2C control pin of the FPGA chip; the analog input pin of the second ADC chip is connected to the core voltage sampling point, power output voltage sampling point, bus signal amplitude sampling point and temperature sensor output terminal of the processor respectively; the control signal output pin of the second ADC chip is connected to the control signal input terminal of the alarm buzzer.
6. A novel industrial control motherboard according to claim 5, characterized in that, It also includes a power supply module; the power output terminal of the power supply module is connected to the power input terminal of the control module, signal transmission module, multi-protocol interface module, and fault monitoring module.