Memory circuit

Abstract

The present disclosure relates to memory circuits. Disclosed herein is a self-timed memory circuit with a bypass mode for testing the output shadow logic. The circuit is applicable to various memory types, including ROM, HistoRAM, and TCAM. In normal operation, the memory array outputs data through sense amplifiers and latches controlled by self-timed circuitry. The output then passes through shadow logic for additional processing. The bypass mode allows direct testing of the shadow logic by inputting test patterns (address bits or search keys) that bypass the memory array. These test signals use the same self-timed mechanism as normal operation, providing an accurate timing representation. This approach enhances the fault coverage of the shadow logic, enabling detection of transient faults and full-speed errors that might be missed by conventional static testing.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 687,901, filed August 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of integrated circuit design and testing, with a specific focus on memory circuits and their associated logic. More specifically, this disclosure relates to methods and systems for testing shadow logic in various types of memory architectures, including but not limited to read-only memory (ROM), histogram random access memory (HistoRAM), and tri-state content-addressable memory (TCAM). Background Technology

[0004] refer to Figure 1 The figure shows a block diagram of a self-timed memory circuit 10. The memory circuit 10 includes a memory array 12 configured to store user data, a read / write row decoder circuit 14, and a data input / output circuit 16. The memory array 12 includes multiple memory cells arranged in a matrix of rows and columns. During a write operation, the read / write decoder circuit 14 decodes the input address and activates the word line coupled to a row of memory cells in the memory array 12. Data input to the input / output circuit 16 is written by the write circuit using write bit lines each connected to a column of memory cells in the memory array 12, for storage in that row of memory cells.

[0005] Crucially, the write circuitry of input / output circuitry 16 is activated for a sufficient amount of time via word line signals to ensure that data is successfully written to the memory cells in the accessed rows of memory array 12. Memory circuitry 10 includes a self-timing circuitry system formed by a dummy read / write decoder (DRD / DWD) 18, one or more dummy columns 20 of memory cells in array 12, one or more dummy rows 22 of memory cells in array 12, and dummy input / output (DIO) circuitry 24.

[0006] At the start of a write operation, when the read / write row decoder circuit 14 enables the word line in response to address decoding, the dummy decoder (DRD / DWD) 18 enables the dummy write word line coupled to a row of memory cells in dummy row 22 and further coupled to at least one memory cell in a column of memory cells in dummy column 20. The dummy input / output (DIO) circuit 24 writes data to the memory cells in the dummy column 20 and senses the completion of the write operation. In response to sensing completion, the memory control circuit 26 can control the read / write row decoder circuit 14 to terminate the enabling of the word line signal on the word line in a timely manner.

[0007] For write operations, dummy row 22 is designed and positioned to track (e.g., simulate) the worst-case latency of each SRAM cell in a selected row of memory array 12 to accept a new data value during a write operation. This accounts for the time spent by the SRAM cells in memory array 12 storing the input value. Dummy column 20 tracks the worst-case latency associated with establishing the correct data value on the bit lines, thereby ensuring that the target SRAM cell in memory array 12 stores the correct data value.

[0008] During a read operation, the read / write decoder circuit 18 decodes the input address and activates the read word line coupled to a row of memory cells in the memory array 12. Data stored in the memory cell at that row is output to a respective read bit line connected to a column of memory cells in the core memory region 12 and sensed by the read circuit of the input / output circuit 16 for output. Crucially, the sensing operation performed by the read circuit of the input / output circuit 16 is initiated no earlier than when the read data is available on the read bit line to ensure successful data reading from the memory cell in the accessed row of the core memory region 12. The memory circuit 10 includes a read-self-timing circuit system formed by a dummy read / write decoder (DRD / DWD) 18, one or more dummy columns 20 of memory cells in the array 12, one or more dummy rows 22 of memory cells in the array 12, and a dummy read input / output (DIO) circuit 24. At the start of a read operation, when the read / write row decoder circuit 14 enables the real word line in response to address decoding, the dummy read / write decoder (DRD / DWD) 18 enables the dummy read word line coupled to a row of memory cells in dummy row 22 and further coupled to at least one memory cell in a column of memory cells in dummy column 20. The dummy read input / output (DIO) circuit 24 senses the availability of read data from the memory cells in the dummy column 20. In response to the sensed availability, the memory control circuit 26 can time-control the actuation of the read sensing circuit of the input / output circuit 16 to sense read data on the read bit line.

[0009] For read operations, dummy row 22 is designed and positioned to track (e.g., simulate) the worst-case delay of each SRAM cell in the selected row of memory array 12 during read operations to reflect its state change on its corresponding bit line. Additionally, dummy column 20 is designed and positioned to track (e.g., simulate) the worst-case bit line delay during read operations, thereby ensuring that the read circuitry is activated in a timely manner to successfully sense the read data value.

[0010] After manufacturing, or at startup, it is desirable to be able to test the functionality of memory circuit 10.

[0011] To perform the first type of test, the BIST controller 34 is shown to transfer n-bit data words D[0], ..., D[n-1] into the input / output circuit 16 via multiplexer 36, and after being operated on by the memory circuit 10 for testing, the result is transferred out of the input / output circuit 16 as n-bit data words Q[0], ..., Q[n-1] and back to the BIST controller 34. This provides testing for the memory array 12 itself.

[0012] To perform a second test that tests the shadow logic (both input shadow logic 30 and output shadow logic 32) itself, n-bit data words D[0], ..., D[n-1] are transferred out of input shadow logic 30 and into output shadow logic 32 via multiplexer 30. If the output from output shadow logic 32 is as expected (determined by test circuit 40), it can be understood that the shadow logic is operating as expected; otherwise, it can be understood that the shadow logic is not operating as expected.

[0013] The problem with this test scheme for shadow logic is that, in actual operation, data is transferred from input shadow logic 30 to memory array 12 via multiplexer 36 and input / output circuitry 16, and then from memory array 12 to output shadow logic 32 via input / output circuitry 16 and multiplexer 38. This transfer via memory array 12 inevitably involves latency, and this specific latency varies with process, voltage, and temperature. Due to this problem, existing test schemes of the above type for shadow logic itself may be insufficient, as they may only detect certain types of errors (e.g., jamming errors) while missing other types of errors (e.g., at-speed failures).

[0014] To address this issue, a technique has been developed to route the output from the input shadow logic 30 through the input / output circuit 16, and this design works for SRAM memory. However, other types of memory exist, such as read-only memory (ROM), tri-state content-addressable memory (TCAM), and HistoRAM. These memories lack data inputs. Thus, the developed techniques are not suitable for such memories, and further development is necessary. Utility Model Content

[0015] One aspect of this disclosure relates to a memory circuit comprising: a memory array; an output circuit coupled to the memory array; a self-timing circuit including a dummy decoder, a dummy memory element, and a dummy output circuit; a control circuit; an input latch within the control circuit for receiving input data; a multiplexer coupled to the output circuit; an output latch coupled to the multiplexer and timed by the output of the dummy output circuit; and output shadow logic, the output shadow... The sub-logic is coupled to the output latch; wherein, in normal operating mode, the input data is used to access the memory array, and the output circuit provides output data from the accessed memory array to the multiplexer; and wherein, in normal operating mode, the multiplexer passes data from the output circuit to the latch, and wherein, in bypass mode activated by a bypass mode signal from the control circuit, the multiplexer passes the input data from the input latch to the output latch, thereby bypassing the memory array.

[0016] According to at least one embodiment of this disclosure, the latch is timed by the output of the dummy output circuit in both the normal operating mode and the bypass mode.

[0017] According to at least one embodiment of this disclosure, the memory array is a read-only memory (ROM) array, and wherein the input data includes address bits.

[0018] According to at least one embodiment of this disclosure, the memory array is a Histogram Random Access Memory (HistoRAM) array, and wherein the input data includes address bits.

[0019] According to at least one embodiment of this disclosure, the memory array is a tri-state content-addressable memory (TCAM) array, and wherein the input data includes search keyword bits.

[0020] According to at least one embodiment of this disclosure, the output shadow logic is configured to perform combinational logic operations on data received from the latch.

[0021] According to at least one embodiment of the present disclosure, the memory circuit further includes a test circuit coupled to the output of the output shadow logic, wherein, in the bypass mode, the test circuit verifies the correct operation of the output shadow logic.

[0022] According to at least one embodiment of the present disclosure, the self-timing circuit is configured to simulate the worst-case latency of the memory array in the normal operating mode.

[0023] According to at least one embodiment of this disclosure, the memory array lacks data input.

[0024] According to at least one embodiment of this disclosure, the bit length of the input data is less than that of the output data.

[0025] Another aspect of this disclosure relates to a memory circuit comprising: a memory array configured to store data; an output circuit system coupled to the memory array and configured to output data from the memory array; a shadow logic circuit system coupled to the output circuit system and configured to perform combinational logic operations on data received from the output circuit system; a bypass circuit system configured to selectively bypass the memory array and provide test data directly to the shadow logic circuit system; and a self-timing circuit system configured to control the timing of data propagation through the bypass circuit system using the same timing mechanism as that used for normal memory operation.

[0026] According to at least one embodiment of the present disclosure, the memory circuit further includes a test circuit coupled to the output of the shadow logic circuit system and configured to verify that the output from the shadow logic circuit system matches the expected result for a given test data.

[0027] According to at least one embodiment of the present disclosure, the bypass circuit system includes a multiplexer configured to selectively route data or test data from the memory array to the shadow logic circuit system based on a bypass mode signal.

[0028] A memory circuit includes a memory array, an output circuit coupled to the memory array, a self-timing circuit including a dummy decoder, dummy memory elements, and a dummy output circuit, a control circuit, an input latch within the control circuit for receiving input data, a multiplexer coupled to the output circuit, an output latch coupled to the multiplexer and timed by the output of the dummy output circuit, and output shadow logic coupled to the output latch. In normal operating mode, the memory array is accessed using input data, and the output circuit provides output data from the accessed memory array to the multiplexer. In normal operating mode, the multiplexer passes data from the output circuit to the latch, and in bypass mode, activated by a bypass mode signal from the control circuit, the multiplexer passes input data from the input latch to the output latch, thereby bypassing the memory array.

[0029] The latch can be timed by the output of the dummy output circuit in both normal operating mode and bypass mode.

[0030] The memory array can be a read-only memory (ROM) array, and the input data can be address bits.

[0031] The memory array can be a HistoRAM array, and the input data can be address bits.

[0032] The memory array can be a tri-state content-addressable memory (TCAM) array, and the input data can be search key bits.

[0033] The output shadow logic can be configured to perform combinational logic operations on the data received from the latch.

[0034] The memory circuit can have a test circuit coupled to the output of the output shadow logic, and in bypass mode, the test circuit can verify the correct operation of the output shadow logic.

[0035] The self-timing circuit can be configured to simulate the worst-case delay of the memory array in normal operating mode.

[0036] Memory arrays can function without data input.

[0037] The bit length of the input data can be less than that of the output data.

[0038] A method of operating a memory circuit includes receiving input data at an input latch within a control circuit. In a normal operating mode, the method includes accessing a memory array using the input data, providing output data from the accessed memory array to a multiplexer via an output circuit, passing output data from the multiplexer to an output latch, and timing the output latch using the output of a dummy output circuit from a self-timing circuit. In a bypass mode, the method includes activating a bypass mode signal from the control circuit, passing input data from the input latch to the output latch via a multiplexer, bypassing the memory array, and timing the output latch using the output of the dummy output circuit from the self-timing circuit. The method also includes processing data from the output latch using output shadow logic.

[0039] The memory array can be a read-only memory (ROM) array, and the input data can be address bits.

[0040] The memory array can be a HistoRAM array, and the input data can be address bits.

[0041] The memory array can be a tri-state content-addressable memory (TCAM) array, and the input data can be search key bits.

[0042] Processing data from the output latch can include performing combinational logic operations on the data.

[0043] The method may include: in bypass mode, using a test circuit coupled to the output of the output shadow logic to verify the correct operation of the output shadow logic.

[0044] This method may include using a self-timing circuit to simulate the worst-case latency of the memory array. Attached Figure Description

[0045] Figure 1 This is a block diagram of a prior art self-timed memory circuit.

[0046] Figure 2 This is a block diagram of a self-timed memory circuit with shadow logic testing capability.

[0047] Figure 3 This is a block diagram of a self-timed ROM of a HistoRAM memory circuit according to an embodiment of the present disclosure.

[0048] Figure 4 This is a block diagram of a self-timed TCAM circuit according to another embodiment of the present disclosure. Detailed Implementation

[0049] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but rather to be given the broadest scope consistent with the principles and features disclosed or suggested herein.

[0050] Now refer to Figure 2 This figure illustrates a technique for routing the output from the input shadow logic through the input / output circuit in a self-timing memory circuit with shadow logic testing capability. Here, in order to test the shadow logic (both input shadow logic 30 and output shadow logic 32) on its own, n-bit data words D[0], ..., D[n-1] are transferred out of the input shadow logic 30 and into the input / output circuit 16 via multiplexer 36, and then back to the output shadow logic 32 via multiplexer 41 and latch 42. To match the delay that will exist when the data is transferred through the memory array 12 itself, the latch 42 is timed by the self-timing operation previously described for the memory circuit 10 (i.e., when the dummy sense amplifier 43 in the dummy input / output circuit 24 has output the result of the dummy read operation).

[0051] Figure 2 This design works for SRAM memories, but not for ROM, TCAM, and HistoRAM memories.

[0052] Now refer to Figure 3 The figure shows a block diagram of a self-timed ROM or HistoRAM memory circuit 10. In a simplified manner, when the ROM receives an address, it responds by reading the corresponding data word at that address and outputting that data word. In contrast, when the HistoRAM receives an address, it responds by reading the data word stored at that address, internally incrementing its value, and writing the incremented value back to the same address—all within a single clock cycle.

[0053] First, a ROM embodiment is described. The memory circuit 10 includes a ROM array 12 for storing fixed data, a row decoder circuit 14, and a data output circuit 16. The ROM array 12 includes a plurality of memory cells arranged in a matrix of rows and columns.

[0054] The controller 34 outputs address bits A[0], ..., A[n-1] to the address latch 44 within the control circuit 26. During a read operation, the row decoder circuit 14 decodes the latched input address and activates the word line coupled to a row of memory cells in the ROM array 12. Data stored in the memory cell at that row is output to the respective bit line connected to a column of memory cells in the ROM array 12, and this data is sensed by the read circuitry (e.g., sense amplifier 45) of the output circuit 16 for output.

[0055] The sensing operation performed by the read sensing circuit 45 of the output circuit 16 will be initiated at the correct time, so that data can be successfully read from the memory cell in the accessed row of the ROM array 12. For this purpose, the memory circuit 10 includes a self-timing circuit system formed by a dummy read decoder (DRD) 18, one or more dummy columns 20, one or more dummy rows 22, and dummy input / output (DIO) circuitry 24.

[0056] At the start of a read operation, when the row decoder circuit 14 enables the read word line in response to address decoding, the dummy read decoder (DRD) 18 enables the dummy read word line. The dummy input / output (DIO) circuit 24 senses the availability of read data from the memory cells of the dummy column 20. In response to the sensed availability, the control circuit 26 of the memory 10 can time the activation of the read sensing circuit 45 of the output circuit 16 to sense the read data on the bit line. The output of the read sensing circuit 45 passes through a multiplexer 41 (in normal operating mode), through a latch 42 (tied by the dummy read result output by the dummy sensing amplifier 46 within the dummy output circuit 24), and arrives at the output shadow logic 32 as output bits Q[0], ..., Q[n-1]. Before generating the final output, the output shadow logic 32 performs combinational logic operations on the data. The test circuit 40 is connected to the output of the output shadow logic 32.

[0057] To perform a test on the output shadow logic 32, the bypass mode signal Bypass_Mode is enabled by the control circuit 26, which has the effect of causing the multiplexer 41 to output the address bits A[0], ..., A[n-1] provided to the address latches 44 to the latches 42, which are timed by the same self-timing mechanism described above (e.g., the output of the dummy sense amplifier 46). Therefore, in this bypass mode, the address bits A[0], ..., A[n-1] are output as output bits Q[0], ..., Q[n-1] to the output shadow logic 32, which performs combinational logic operations on the data before generating the final output. The test circuit 40 is connected to the output of the output shadow logic 32 and verifies that the output from the output shadow logic 32 is as expected. If the output from the shadow logic is as expected, it can be inferred that the shadow logic 32 itself is operating correctly. Conversely, if the output from the shadow logic is not as expected, it can be inferred that the shadow logic 32 itself is not operating correctly.

[0058] When array 12 is a HistoRAM array instead of a ROM array, the operation and testing process differs slightly. HistoRAM, or histogram RAM, is designed to increment the value stored at a given address each time it is accessed. When controller 34 outputs addresses A[0], ..., A[n-1] to address latch 44, HistoRAM array 12 reads the current value at that address, increments it, and writes the new value back to the same address, all within a single clock cycle. The incremented value is then output to output shadow logic 32 via sense amplifier 45, multiplexer 41, and latch 42. The self-timing mechanism remains crucial in this operation to ensure correct read, increment, and write-back timing.

[0059] To test the output shadow logic 32 in the HistoRAM configuration, the bypass mode operates similarly to the ROM version. When the Bypass_Mode signal is active, address bits A[0], ..., A[n-1] bypass the HistoRAM array and are sent directly to the output shadow logic 32 via multiplexer 41 and latch 42. This allows for isolated testing of the shadow logic independent of the HistoRAM's incrementing function. The test circuit 40 can then verify that the output shadow logic 32 correctly processes these bypassed address bits, thus allowing for fault detection specifically within the shadow logic circuitry system, independent of the HistoRAM array operation.

[0060] Now refer to Figure 4 The figure shows a block diagram of a self-timed tri-state content-addressable memory (TCAM) circuit 10. The TCAM circuit 10 includes a TCAM array 12, a row decoder 14, an output circuit 16, a dummy decoder 18, dummy TCAM rows 22, a dummy output 24, and a control circuit 26. The control circuit 26 includes a key latch 47 that receives search keywords K[0], ..., K[n-1].

[0061] In normal operation, TCAM array 12 compares search keywords against its stored contents to find matching entries. Row decoder 14 activates all rows in TCAM array 12 for parallel comparison. The sensing operation performed by output circuit 16 needs to be initiated at the correct time to ensure successful matching. To achieve this, the circuit includes a self-timing circuit system formed by dummy decoder 18, dummy TCAM rows 22, and dummy output 24. When the search operation begins, dummy decoder 18 activates dummy TCAM rows 22. Dummy output 24 senses the completion of the dummy search operation, thereby providing a timing signal to control the main TCAM array output.

[0062] Output circuit 16 includes a sense amplifier (not shown) that detects matches in each column of TCAM array 12. The results of these matches, represented as hit signals H[0], ..., H[n-1], are then passed through multiplexer 48 and latch 49. Latch 49 is timed by a self-timing operation (specifically through the output of dummy output 24). This ensures that the hit signal is captured at the appropriate time.

[0063] Then, the hit signals H[0], ..., H[n-1] are fed into the output shadow logic 32. Before generating the final output, the shadow logic performs additional processing on the hit signals, such as priority encoding or error checking.

[0064] To perform the test of output shadow logic 32 independently of TCAM array 12, a bypass mode is implemented. When control circuit 26 enables the bypass mode signal, multiplexer 48 is switched to bypass TCAM array 12 and its associated sense amplifier. Alternatively, search keyword bits K[0], ..., K[n-1] from keyword latch 47 are passed directly to latch 49 via multiplexer 48. These latches are still timed using the same self-timing mechanism as in normal operation (i.e., the output of dummy output 24).

[0065] In this bypass mode, the search key bits K[0], ..., K[n-1] are effectively used as analog hit signals and output as H[0], ..., H[n-1] to the output shadow logic 32. The shadow logic then performs its common combinational logic operations on these analog hit signals. The test circuit 40, connected to the output of the shadow logic 32, verifies whether the output from the shadow logic is as expected based on the known input (search key bits).

[0066] If the output from the shadow logic matches the expected result for a given input, it can be inferred that the shadow logic 32 itself is operating correctly. Conversely, if the output does not match the expectation, this indicates a potential problem within the shadow logic circuit system. Therefore, this bypass mode allows for isolated testing of the shadow logic independent of the search operation of the TCAM array, enabling efficient fault detection and diagnosis.

[0067] By implementing a bypass mode, the disclosed embodiments allow test patterns (such as address bits or search keywords) to be directly input into the shadow logic, thereby effectively simulating the output of the memory array. This bypass path incorporates the same self-timing mechanisms used in normal memory operation, including dummy decoders, dummy rows, and dummy output circuitry. This ensures that the delays in test signal propagation through the system accurately reflect the delays experienced during actual memory accesses, including variations due to process, voltage, and temperature (PVT) factors.

[0068] This method significantly enhances the fault coverage of shadow logic, thus addressing gaps in traditional memory testing methods. Specifically, it allows the detection of transient faults and full-rate errors that conventional static testing methods might miss. This is particularly valuable for testing shadow logic that generates output patterns based on memory addresses and other input pins, as these patterns can now be directly simulated and verified.

[0069] Furthermore, the flexibility of this testing method makes it applicable to a wide variety of memory types. Whether handling simple read operations of ROM, read-modify-write cycles of HistoRAM, or complex search operations of TCAM, the disclosed embodiment with bypass mode can accurately simulate the timing and behavior of each memory type. In fact, this testing method is applicable to any memory array that lacks data input for receiving data to be written to the memory array, or for which the bit length of the input data is smaller than the output data from the memory.

[0070] Finally, it is obvious that modifications and changes can be made to the content described and illustrated herein without departing from the scope of this disclosure.

[0071] Although this disclosure has been described with a limited number of embodiments, those skilled in the art who benefit from this disclosure will envision other embodiments without departing from the scope of the disclosure. Furthermore, those skilled in the art will envision embodiments representing various combinations of the embodiments disclosed herein made in various ways.

Claims

1. A memory circuit, characterized in that, The memory circuit includes: Memory array; Output circuit, the output circuit being coupled to the memory array; The self-timed circuit includes a dummy decoder, a dummy memory element, and a dummy output circuit. Control circuit; An input latch, located within the control circuit, is used to receive input data. A multiplexer, the multiplexer being coupled to the output circuit; An output latch, coupled to the multiplexer and timed by the output of the dummy output circuit; and The output shadow logic is coupled to the output latch; In normal operating mode, the input data is used to access the memory array, and the output circuit provides the output data from the accessed memory array to the multiplexer; and In the normal operating mode, the multiplexer transmits data from the output circuit to the latch, and in the bypass mode activated by the bypass mode signal from the control circuit, the multiplexer transmits the input data from the input latch to the output latch, thereby bypassing the memory array.

2. The memory circuit according to claim 1, characterized in that, The latch is timed by the output of the dummy output circuit in both the normal operating mode and the bypass mode.

3. The memory circuit according to claim 1, characterized in that, The memory array is a read-only memory (ROM) array, and the input data includes address bits.

4. The memory circuit according to claim 1, characterized in that, The memory array is a HistoRAM array, and the input data includes address bits.

5. The memory circuit according to claim 1, characterized in that, The memory array is a tri-state content-addressable memory (TCAM) array, and the input data includes search keyword bits.

6. The memory circuit according to claim 1, characterized in that, The output shadow logic is configured to perform combinational logic operations on the data received from the latch.

7. The memory circuit according to claim 1, characterized in that, The memory circuit also includes a test circuit coupled to the output of the output shadow logic, wherein, in the bypass mode, the test circuit verifies the correct operation of the output shadow logic.

8. The memory circuit according to claim 1, characterized in that, The self-timing circuit is configured to simulate the worst-case latency of the memory array in the normal operating mode.

9. The memory circuit according to claim 1, characterized in that, The memory array lacks data input.

10. The memory circuit according to claim 1, characterized in that, The bit length of the input data is less than that of the output data.

11. A memory circuit, characterized in that, The memory circuit includes: A memory array configured to store data; An output circuitry system coupled to the memory array and configured to output data from the memory array; A shadow logic circuit system, which is coupled to the output circuit system and configured to perform combinational logic operations on data received from the output circuit system; A bypass circuitry system configured to selectively bypass the memory array and provide test data directly to the shadow logic circuitry system; and A self-timing circuit system is configured to use the same timing mechanism as that used for normal memory operation to control the timing of data propagation through the bypass circuit system.

12. The memory circuit according to claim 11, characterized in that, The memory circuit also includes: A test circuit, coupled to the output of the shadow logic circuit system and configured to verify that the output from the shadow logic circuit system matches the expected result for a given test data.

13. The memory circuit according to claim 11, characterized in that, The bypass circuit system includes: A multiplexer configured to selectively route data or test data from the memory array to the shadow logic circuitry system based on a bypass mode signal.

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