A synchronous rectification anti-inrush circuit with output pre-bias

Abstract

The utility model relates to a kind of output pre-biased synchronous rectification anti-inrush circuit, including synchronous rectification unit, auxiliary winding unit, start or close detection unit and load discharge unit;Synchronous rectification unit is unidirectionally connected with auxiliary winding unit and load discharge unit respectively, auxiliary winding unit is unidirectionally connected with start or close detection unit, start or close detection unit is unidirectionally connected with load discharge unit bidirectionally;Synchronous rectification unit generates chopping signal according to PWM signal, transmits chopping signal to auxiliary winding unit, simultaneously transmits output voltage signal to load discharge unit;The utility model does not need external signal control, peripheral device is few, cost is lower, using this circuit can improve the reliability of DC-DC switching power supply, and with wide range of application, can be applicable to a variety of circuit topologies, degree of flexibility higher characteristics.

Description

Technical Field

[0001] This utility model relates to the field of switching power supply circuit technology, and in particular to a synchronous rectification anti-backflow circuit with output pre-biasing. Background Technology

[0002] In the field of power electronics, synchronous rectification technology is used in switching power supplies to reduce conduction losses in the high-frequency rectification stage, thereby improving the efficiency of the switching power supply and reducing heat loss. However, synchronous rectification technology faces a significant challenge in practical applications: the synchronous rectifier transistors experience backflow when the output is pre-biased. If the output capacitor has a pre-bias voltage, the negative current of the synchronous rectifier MOSFET is large during power-on or power-off, which can damage the MOSFET and result in poor reliability. Furthermore, most current anti-backflow circuits use digital chip control or specialized anti-backflow detection chips, which suffer from high cost and limited application topologies. Therefore, there is an urgent need for a synchronous rectification anti-backflow circuit that requires fewer external components, has a lower cost, and is applicable to various circuit topologies to solve the existing problems. Summary of the Invention

[0003] This invention provides a synchronous rectification anti-backflow circuit for output pre-biasing, which solves the problem of backflow in the synchronous rectifier tube during output pre-biasing.

[0004] The technical solution adopted in this utility model is: a synchronous rectification anti-backflow circuit with output pre-bias, including a synchronous rectification unit, an auxiliary winding unit, a start-up or stop-down detection unit, and a load bleeder unit; the synchronous rectification unit is unidirectionally connected to the auxiliary winding unit and the load bleeder unit respectively, the auxiliary winding unit is unidirectionally connected to the start-up or stop-down detection unit, and the start-up or stop-down detection unit is unidirectionally bidirectionally connected to the load bleeder unit; the synchronous rectification unit generates a chopping signal according to the PWM signal, transmits the chopping signal to the auxiliary winding unit, and simultaneously transmits the output voltage signal to the load bleeder unit; the auxiliary winding unit is used to... The chopper signal transmitted by the synchronous rectification unit is rectified to generate an auxiliary voltage signal. The auxiliary voltage signal is used to indicate the start or stop status of the circuit and is transmitted to the start or stop detection unit. The start or stop detection unit generates a dual-channel signal based on the auxiliary voltage signal transmitted by the auxiliary winding unit. This dual-channel signal is transmitted to the load bleeder unit to control the connection and disconnection between the output capacitor and the load bleeder resistor. The load bleeder unit controls the connection and disconnection between the output capacitor and the load bleeder resistor based on the output voltage signal transmitted by the synchronous rectification unit and the dual-channel signal from the start or stop detection unit.

[0005] The technical effects of this invention are as follows: This invention provides a synchronous rectification anti-backflow circuit with output pre-biasing. When the power supply is started, the synchronous rectification unit begins to work, sending the chopping signal from the synchronous rectification unit to the auxiliary winding unit via a high-frequency transformer. The auxiliary winding unit rectifies the chopping signal into a stable auxiliary voltage signal. The start-up or shutdown detection unit generates first and second load discharge control signals based on the rise and fall of the auxiliary voltage signal. The load discharge unit controls the conduction and shutdown of the discharge load according to the first and second load discharge control signals, consuming the charge of the output capacitor and reducing the load voltage, thereby reducing the negative current during startup. When the power supply is turned off, the voltage established on the auxiliary winding unit drops rapidly. The start-up or shutdown detection unit generates a second load discharge control signal based on the drop and fall of the auxiliary voltage signal. The load discharge unit controls the conduction and shutdown of the discharge load according to the second load discharge control signal, consuming the charge of the output capacitor and reducing the load voltage, preventing damage to the synchronous rectifier MOSFET during shutdown, thereby preventing current backflow.

[0006] Compared with other anti-backflow circuits, this invention has the following advantages: Other anti-backflow circuits require digital control chips for real-time sampling or can only perform anti-backflow detection for a single topology, resulting in complex control and high cost. This invention, a synchronous rectification anti-backflow circuit with output pre-bias, does not require additional integrated chips or digital control chips. It only needs the synchronous rectification PWM drive signal and the output voltage signal to determine whether there is a pre-bias voltage on the output capacitor. For both startup and shutdown, the first and second load discharge control signals are used to discharge the output capacitor C1, reducing the voltage on the output capacitor to a reasonable value, thereby reducing the negative current stress on the synchronous rectification field-effect transistor. The components used in the implementation of the circuit technology described in this invention are all simple components, with extremely low cost and low implementation difficulty, resulting in high cost-effectiveness. It can be applied to various topologies, including but not limited to forward circuits, push-pull circuits, and half-bridge circuits. Attached Figure Description

[0007] Figure 1 This is a circuit connection block diagram of the present invention; Figure 2 This is the circuit schematic diagram of this utility model; Figure 3 The waveforms of the synchronous rectifier drive signal, output voltage, and inductor current during the soft-start process of normal operation are shown. Figure 4 This is a waveform diagram of the synchronous rectifier drive signal, output voltage, and inductor current during the soft-start process in this embodiment of the invention. Figure 5 The waveforms of the synchronous rectifier drive signal, output voltage, and inductor current during the normal operation shutdown process are shown. Figure 6 The diagram shows the waveforms of the synchronous rectifier drive signal, output voltage, and inductor current during the shutdown process in this embodiment of the invention. Detailed Implementation

[0008] To understand this utility model, detailed structures and steps will be presented in the following description in order to illustrate the technical solution proposed by this utility model. The embodiments of this utility model will be clearly and completely described in conjunction with the accompanying drawings. The described embodiments are some embodiments of this utility model, but not all embodiments.

[0009] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0010] This embodiment provides a synchronous rectification anti-backflow circuit with output pre-biasing, which is applied in the synchronous rectification unit of a switching power supply. The topology of the applied circuit includes, but is not limited to, forward circuit, push-pull circuit, half-bridge circuit, etc.

[0011] like Figure 1 As shown, a synchronous rectification anti-backflow circuit with output pre-biased includes a synchronous rectification unit, an auxiliary winding unit, a start-up or shutdown detection unit, and a load discharge unit.

[0012] The synchronous rectification unit is connected to the auxiliary winding unit and the load discharge unit, outputting a chopping signal to the auxiliary winding unit and a load voltage signal to the load discharge unit. The auxiliary winding unit is connected to the synchronous rectification unit and the start-up or shutdown detection unit, and outputs an auxiliary voltage signal to the start-up or shutdown detection unit based on the chopping signal. The start-up or shutdown detection unit is connected to the auxiliary winding unit and the load discharge unit, and outputs a first load discharge control signal and a second load discharge control signal to the load discharge unit based on the auxiliary voltage signal. The load discharge unit is connected to the synchronous rectification unit and the start-up or shutdown detection unit, and connects or disconnects the connection between the load voltage signal and the load discharge unit based on the first load discharge control signal, the second load discharge control signal, and the load voltage signal.

[0013] like Figure 2As shown, the synchronous rectification unit includes a high-frequency transformer T1, field-effect transistors Q1 and Q2, an inductor L1, and a capacitor C1. The specific circuit connection is as follows: the first terminal of the high-frequency transformer T1 is connected to the drain of field-effect transistor Q1 and one end of inductor L1; the second terminal of the high-frequency transformer T1 is connected to the drain of field-effect transistor Q2; the third terminal of the high-frequency transformer T1 outputs a chopping signal connected to the positive terminal of diode D1 in the auxiliary winding unit; the fourth terminal of the high-frequency transformer T1 is connected to zero potential ground; the sources of field-effect transistors Q1 and Q2, and one end of capacitor C1 are connected to zero potential ground; the gate of field-effect transistor Q1 is connected to the PWM1 signal; the gate of field-effect transistor Q2 is connected to the PWM2 signal; the other end of inductor L1 is connected to the other end of capacitor C1 and is connected to the load discharge unit resistor R5 to output the load voltage signal.

[0014] The auxiliary winding unit includes diode D1, capacitor C2, resistor R1, diode D2, and capacitor C3. The specific circuit connection is as follows: the positive terminal of diode D1 is connected to the third terminal of the high-frequency transformer T1 of the synchronous rectification unit, which is connected to the chopping signal; the negative terminal of diode D1 is connected to one end of capacitor C2 and resistor R1, and outputs an auxiliary voltage signal connected to the start or stop detection unit; the other end of resistor R1 is connected to the negative terminal of diode D2 and one end of capacitor C3; the other ends of capacitors C2 and C3 and the positive terminal of diode D2 are connected to zero potential ground.

[0015] The start-up or shutdown detection unit includes capacitor C4, capacitor C5, transistor Q3, capacitor C6, resistor R2, diode D3, and capacitor C7. The specific circuit connection is as follows: one end of capacitor C4 is connected to one end of capacitor C5, the collector of transistor Q3, one end of resistor R2, and the negative terminal of diode D1 in the auxiliary winding unit, connected to the auxiliary voltage signal; the other end of capacitor C4 outputs a first load discharge control signal connected to the gate of the load discharge unit field-effect transistor Q4; the other end of capacitor C5 is connected to one end of capacitor C6 and the positive terminal of diode D3, and connected to zero potential ground; the emitter of transistor Q3 is connected to the other end of capacitor C6; the base of transistor Q3 is connected to the other end of resistor R2, the negative terminal of diode D3, and one end of capacitor C7; the other end of capacitor C7 outputs a second load discharge control signal connected to the gate of the load discharge unit field-effect transistor Q5.

[0016] The load discharge unit includes a field-effect transistor (FET) Q4, a resistor R3, a diode D4, a field-effect transistor Q5, and a resistor R5. The specific circuit connections are as follows: the source of FET Q4 is connected to one end of resistors R3 and R5, the drain of FET Q5 is connected to the negative terminal of diode D4, the gate of FET Q4 is connected to the other end of resistor R3 and the positive terminal of diode D4, and is connected to capacitor C4 in the start-up or stop-down detection unit, thus connecting to the first load discharge control signal. The drain of FET Q4, one end of resistor R4, and the source of FET Q5 are connected to zero potential ground. The other end of resistor R4 and the gate of FET Q5 are connected to capacitor C7 in the start-up or stop-down detection unit, thus connecting to the second load discharge control signal. The other end of resistor R5 is connected to inductor L1 in the synchronous rectification unit, thus connecting to the load voltage signal.

[0017] The field-effect transistor Q4 in the load bleed unit is a P-type field-effect transistor, and the field-effect transistor Q5 in the load bleed unit is an N-type field-effect transistor.

[0018] like Figure 3 The figure shows the waveforms of the synchronous rectifier drive signal, output voltage, and inductor current during the soft start process of normal operation. When the output capacitor has a high bias voltage, the output of the switching power supply is in a pre-biased state during normal startup. During the soft start process, the excitation time of the inductor L1 current is less than the demagnetization time. The inductor L1 will accumulate negative current in each cycle, resulting in negative current in the synchronous rectifier field-effect transistors Q1 and Q2. After multiple cycles, the accumulated negative current is too large, which will cause the synchronous rectifier field-effect transistor current over-stress, thereby damaging the synchronous rectifier field-effect transistor. like Figure 4 The diagram shown is a waveform of the synchronous rectifier drive signal, output voltage, and inductor current during the soft-start process in this embodiment of the invention. When the circuit starts, if there is a high bias voltage on the output capacitor, this invention will connect the discharge resistor to the output capacitor by turning on the first load discharge control signal and the second load discharge control signal, thereby releasing the bias voltage on the output capacitor and reducing the negative current of the synchronous rectifier field-effect transistor.

[0019] like Figure 5 The diagram shows the waveforms of the synchronous rectifier drive signal, output voltage, and inductor current during the normal operation and shutdown process. When the power supply changes from normal operation to shutdown, both PWM1 and PWM2 drives are turned off. Since the inductor current cannot change abruptly at this time, the inductor L1, capacitor C1, and the body diode of the synchronous rectifier field-effect transistor Q1 form a circuit. Because the output is in an unloaded state, the inductor L1 continuously charges the capacitor C1. When the voltage across the capacitor C1 exceeds the voltage stress of the synchronous rectifier field-effect transistor Q1, the synchronous rectifier field-effect transistor Q1 is damaged, and the current flows back into the synchronous rectifier field-effect transistor.

[0020] like Figure 6 The diagram shows the waveforms of the synchronous rectifier drive signal, output voltage, and inductor current during the shutdown process in this embodiment of the invention. When the circuit is shut down, if there is a high bias voltage on the output capacitor, this invention will activate the second load discharge control signal, connect the discharge resistor to the output capacitor, release the voltage on the output capacitor, and consume the current on the inductor, thereby achieving the purpose of protecting the synchronous rectifier field-effect transistor.

[0021] The working principle is as follows: When the power supply starts, it outputs two complementary PWM signals to generate a chopping signal. After being transmitted through the high-frequency transformer T1, the chopping signal is rectified by diode D1 and generates a voltage across capacitor C2. The rectified voltage is the auxiliary voltage signal, which changes from 0 until it reaches a stable voltage. Then, the voltage is clamped by the Zener diode D2 and capacitor C3 after passing through resistor R1.

[0022] The start or stop detection unit is activated based on the auxiliary voltage signal, which is clamped to the regulated value by the Zener diode D3 through resistor R2. Since the voltage across the capacitor cannot change abruptly, the voltage of the Zener diode D3 provides the second load discharge control signal to the load discharge unit through capacitor C7.

[0023] After the second load discharge control signal is set high, the MOSFET Q5 turns on. Resistor R5 is connected across the output capacitor C1 to discharge it. When the voltage across Zener diode D3 reaches a stable voltage, the DC signal cannot pass through capacitor C7, and MOSFET Q5 discharges naturally through resistor R4. This continues until the gate voltage is lower than the turn-on voltage of MOSFET Q5, at which point MOSFET Q5 turns off. The current in discharge resistor R5 drops to zero, and the source voltage of MOSFET Q4 rises. The voltage of capacitor C5 in the start-up or shutdown detection unit remains stable, and capacitor C4 provides the driving voltage for MOSFET Q4, generating the first load discharge control signal. MOSFET Q4 turns on, and resistor R5 continues to be connected across the output capacitor C1 to discharge it until the load voltage stabilizes, the source voltage of MOSFET Q4 stabilizes, the voltage difference across capacitor C4 is zero, the gate of MOSFET Q4 discharges naturally through resistor R3, MOSFET Q4 turns off, and the discharge resistor R5 is disconnected from the output capacitor C1. By connecting a bleeder resistor R5 to reduce the output voltage, the negative current is reduced, thereby protecting the synchronous rectifier field-effect transistors Q1 and Q2.

[0024] When the power is off, both PWM1 and PWM2 drives are off, the chopping signal disappears, and the voltage across capacitor C2 in the auxiliary winding unit gradually disappears, the auxiliary voltage signal becomes 0, a voltage difference exists across capacitor C4 in the start-up or shutdown detection unit, current flows through capacitor C4, generating a first load discharge control signal, the load discharge unit MOSFET Q4 turns on, resistor R5 is connected to the load voltage to consume the voltage across capacitor C1 in the synchronous rectification unit until the load voltage stabilizes, the voltage difference across capacitor C4 disappears, the first load discharge control signal turns off, the gate of MOSFET Q4 discharges naturally through resistor R3, and MOSFET Q4 turns off. Load resistor R5 provides a power dissipation path for capacitor C1, preventing capacitor C1 from being continuously charged.

[0025] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

[0026] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A synchronous rectification anti-backflow circuit with output pre-biasing, characterized in that: The circuit includes a synchronous rectification unit, an auxiliary winding unit, a start-up or shutdown detection unit, and a load bleeder unit. The synchronous rectification unit is unidirectionally connected to both the auxiliary winding unit and the load bleeder unit. The auxiliary winding unit is unidirectionally connected to the start-up or shutdown detection unit, and the start-up or shutdown detection unit is bidirectionally connected to the load bleeder unit. The synchronous rectification unit generates a chopping signal based on a PWM signal and transmits the chopping signal to the auxiliary winding unit, while simultaneously transmitting an output voltage signal to the load bleeder unit. The auxiliary winding unit generates an auxiliary voltage signal after rectifying the chopping signal transmitted from the synchronous rectification unit. This auxiliary voltage signal is used to display the start-up or shutdown status of the circuit and is transmitted to the start-up or shutdown detection unit. The start or stop detection unit is used to generate dual signals based on the auxiliary voltage signal transmitted by the auxiliary winding unit. These dual signals are transmitted to the load discharge unit to control the connection and disconnection between the output capacitor and the load discharge resistor. The load bleed unit is used to control the connection and disconnection between the output capacitor and the load bleed resistor based on the output voltage signal transmitted by the synchronous rectification unit and the dual-channel signal of the start or stop detection unit.

2. The synchronous rectification anti-backflow circuit with output pre-biasing as described in claim 1, characterized in that: The synchronous rectification unit includes a high-frequency transformer T1, field-effect transistors Q1 and Q2, an inductor L1, and a capacitor C1. The specific circuit connection is as follows: the first terminal of the high-frequency transformer T1 is connected to the drain of field-effect transistor Q1 and one end of inductor L1; the second terminal of the high-frequency transformer T1 is connected to the drain of field-effect transistor Q2; the third terminal of the high-frequency transformer T1 outputs a chopping signal and is connected to the positive terminal of diode D1 in the auxiliary winding unit; the fourth terminal of the high-frequency transformer T1 is connected to zero potential ground; the sources of field-effect transistors Q1 and Q2, and one end of capacitor C1 are connected to zero potential ground; the gate of field-effect transistor Q1 is connected to the PWM1 signal; the gate of field-effect transistor Q2 is connected to the PWM2 signal; the other end of inductor L1 is connected to the other end of capacitor C1 and is connected to the load discharge unit resistor R5 to output the load voltage signal.

3. The synchronous rectification anti-backflow circuit with output pre-bias as described in claim 1, characterized in that: The auxiliary winding unit includes diode D1, capacitor C2, resistor R1, diode D2, and capacitor C3. The specific circuit connection is as follows: the positive terminal of diode D1 is connected to the third terminal of the high-frequency transformer T1 of the synchronous rectification unit, which is connected to the chopping signal; the negative terminal of diode D1 is connected to one end of capacitor C2 and resistor R1, and outputs an auxiliary voltage signal connected to the start or stop detection unit; the other end of resistor R1 is connected to the negative terminal of diode D2 and one end of capacitor C3; the other ends of capacitors C2 and C3 and the positive terminal of diode D2 are connected to zero potential ground.

4. The synchronous rectification anti-backflow circuit with output pre-biasing as described in claim 1, characterized in that: The start-up or shutdown detection unit includes capacitor C4, capacitor C5, transistor Q3, capacitor C6, resistor R2, diode D3, and capacitor C7. The specific circuit connection is as follows: one end of capacitor C4 is connected to one end of capacitor C5, the collector of transistor Q3, one end of resistor R2, and the negative terminal of diode D1 in the auxiliary winding unit, connected to the auxiliary voltage signal; the other end of capacitor C4 outputs a first load discharge control signal connected to the gate of the load discharge unit field-effect transistor Q4; the other end of capacitor C5 is connected to one end of capacitor C6 and the positive terminal of diode D3, and connected to zero potential ground; the emitter of transistor Q3 is connected to the other end of capacitor C6; the base of transistor Q3 is connected to the other end of resistor R2, the negative terminal of diode D3, and one end of capacitor C7; the other end of capacitor C7 outputs a second load discharge control signal connected to the gate of the load discharge unit field-effect transistor Q5.

5. The synchronous rectification anti-backflow circuit with output pre-bias as described in claim 1, characterized in that: The load discharge unit includes a field-effect transistor (FET) Q4, a resistor R3, a diode D4, a field-effect transistor Q5, and a resistor R5. The specific circuit connection is as follows: the source of FET Q4 is connected to one end of resistors R3 and R5, the drain of FET Q5, and the cathode of diode D4; the gate of FET Q4 is connected to the other end of resistor R3 and the anode of diode D4, and is also connected to capacitor C4 of the start-up or shutdown detection unit, which is connected to the first load discharge control signal; the drain of FET Q4, one end of resistor R4, and the source of FET Q5 are connected to zero potential ground; the other end of resistor R4 and the gate of FET Q5 are connected to capacitor C7 of the start-up or shutdown detection unit, which is connected to the second load discharge control signal; the other end of resistor R5 is connected to inductor L1 of the synchronous rectification unit, which is connected to the load voltage signal.

6. The synchronous rectification anti-backflow circuit with output pre-bias as described in claim 1, characterized in that: The field-effect transistor Q4 in the load discharge unit is a P-type field-effect transistor.

7. The synchronous rectification anti-backflow circuit with output pre-bias as described in claim 1, characterized in that: The field-effect transistor Q5 of the load discharge unit is an N-type field-effect transistor.

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