Peak detector and radio frequency module

Abstract

The application relates to a peak detector and a radio frequency module. The peak detector comprises a peak detection core circuit configured to perform peak detection on an input radio frequency signal based on nonlinear rectification of a first transistor circuit and static operating point error cancellation of a second transistor circuit in a transistor pair circuit to obtain a differential output composed of a first signal and a second signal; wherein a direct current component of the radio frequency signal is determined according to the first signal and the second signal; and an output stage circuit configured to convert the differential output of the peak detection core circuit into a single-ended output and output the single-ended output through a source follower to obtain an output signal of the peak detector. The application provides a low-cost solution for implementing a complete system on chip (SOC) and improves the load capacity of the peak detector.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a peak detector and a radio frequency module. Background Technology

[0002] A peak detector, also known as a signal level detector, power detector, or envelope detector, is mainly used to detect power peaks and demodulate signals. It is widely used in wireless transceivers, for example, in millimeter-wave imaging and millimeter-wave high-speed communication systems, to obtain the signal power level of radio frequency (RF) signals received at the antenna of a wireless transceiver.

[0003] Because a complete System-on-a-Chip (SoC) has many advantages such as low cost, small size, and high integration, it is very suitable for the development of millimeter-wave frequencies and the increasing demand for data rates in modern mobile communication standards. Therefore, there is an urgent need for a CMOS-based radio frequency (RF) detector to provide a low-cost solution for realizing a complete SoC. Utility Model Content

[0004] In view of this, embodiments of this application provide a peak detector and a radio frequency module to solve at least one problem existing in the background art.

[0005] In a first aspect, embodiments of this application provide a peak detector, the peak detector comprising: The peak detection core circuit is configured to perform peak detection on the input radio frequency signal based on the nonlinear rectification of the first transistor circuit and the static operating point error cancellation of the second transistor circuit in the transistor pair circuit, so as to obtain a differential output composed of the first signal and the second signal; wherein, the DC component of the radio frequency signal is determined according to the first signal and the second signal; The output stage circuit is configured to convert the differential output of the peak detection core circuit into a single-ended output, and output the single-ended output through a source follower to obtain the output signal of the peak detector.

[0006] In conjunction with the first aspect, in an alternative implementation, The peak detection core circuit includes a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, a third capacitor, a fourth capacitor, a first bias current source, and a second bias current source. The gate of the first NMOS transistor is configured as the input terminal of the first transistor circuit and acquires the radio frequency signal, and is connected to the first terminal of the first resistor; the source of the first NMOS transistor is connected to the ground terminal through the first bias current source and is connected to the first terminal of the third capacitor, and is configured to output the first signal. The gate of the second NMOS transistor is configured as the input terminal of the second transistor circuit and connected to the first terminal of the second resistor; the source of the second NMOS transistor is connected to ground via the second bias current source and connected to the first terminal of the fourth capacitor, and configured to output the second signal. The drain of the first NMOS transistor, the second terminal of the first resistor, the drain of the second NMOS transistor, and the second terminal of the second resistor are respectively connected to the power supply terminal; the second terminals of the third capacitor and the fourth capacitor are respectively connected to the ground terminal.

[0007] In conjunction with the first aspect, in an alternative implementation, The peak detection core circuit also includes an input coupling module, configured to transmit only the radio frequency signal to the input terminal of the first transistor circuit.

[0008] In conjunction with the first aspect, in an alternative implementation, The input coupling module includes a first capacitor and a second capacitor; The first terminal of the second capacitor is configured to acquire radio frequency signals, and the second terminal of the second capacitor is connected to the input terminal of the first transistor circuit. The first terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the first capacitor is connected to ground.

[0009] In conjunction with the first aspect, in an alternative implementation, The output stage circuit includes: A subtractor configured to determine and output a third signal based on the first signal and the second signal; A source follower configured to determine the output signal based on the third signal.

[0010] In conjunction with the first aspect, in an alternative implementation, The subtractor includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an operational amplifier; The first terminal of the third resistor is configured to acquire the first signal, and the second terminal of the third resistor is connected to the first terminal of the fourth resistor and the first input terminal of the operational amplifier, respectively; the second terminal of the fourth resistor is connected to ground. The first terminal of the fifth resistor is configured to acquire the second signal, and the second terminal of the fifth resistor is connected to the second input terminal of the operational amplifier and the first terminal of the sixth resistor, respectively; the second terminal of the sixth resistor is configured to acquire the output signal. The output of the operational amplifier is configured to output a third signal.

[0011] In conjunction with the first aspect, in an alternative implementation, The source follower includes a third NMOS transistor and a third bias current source; The gate of the third NMOS transistor is configured to acquire a third signal; the drain of the third NMOS transistor is connected to the power supply terminal; the source of the third NMOS transistor is connected to the ground terminal via a third bias current source and is configured to output the output signal.

[0012] In conjunction with the first aspect, in an alternative implementation, The peak detector also includes: The bias circuit is configured based on a current mirror structure to provide a current source for the peak detection core circuit and the output stage circuit.

[0013] In conjunction with the first aspect, in an alternative implementation, The bias circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth PMOS transistor; The first bias current source of the peak detection core circuit includes a seventh NMOS transistor; The second bias current source of the peak detection core circuit includes an eighth NMOS transistor; The third bias current source of the output stage circuit includes a ninth NMOS transistor; The drain of the fourth NMOS transistor is configured to obtain a reference current and is connected to the gates of the fourth, fifth, seventh, eighth, and ninth NMOS transistors, respectively; the sources of the fourth, fifth, seventh, eighth, and ninth NMOS transistors are connected to ground. The drain of the fifth NMOS transistor is connected to the drain of the sixth PMOS transistor and the gate of the sixth PMOS transistor, respectively; the source of the sixth PMOS transistor is connected to the power supply terminal. The drain of the seventh NMOS transistor is connected to the source of the first NMOS transistor in the peak detection core circuit; the drain of the eighth NMOS transistor is connected to the source of the second NMOS transistor in the peak detection core circuit; and the drain of the ninth NMOS transistor is connected to the source of the third NMOS transistor in the source follower.

[0014] Secondly, embodiments of this application provide a radio frequency module, the radio frequency module including the peak detector as described in the first aspect.

[0015] The beneficial effects of the technical solution provided in this application include: a monolithic RF peak detector, comprising a peak detection core circuit, an output stage circuit, and a bias circuit, can be implemented using a transistor-pair circuit based on CMOS technology, thus providing a low-cost solution for realizing a complete system-on-a-chip (SoC). Furthermore, by utilizing a source follower for the single-ended output in the output stage circuit, the load-carrying capacity of the peak detector is improved, thereby meeting the application requirements where the load of the peak detector is often resistive. Moreover, the static operating point error cancellation effect of the second transistor circuit in the transistor-pair circuit eliminates peak detection distortion of the RF signal, improving detection accuracy.

[0016] Additional aspects and advantages of the embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of this application. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, are provided. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show details of those features. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a circuit diagram illustrating a specific example of a peak detector in an embodiment of this application. Figure 2 This is a circuit diagram illustrating a specific example of the peak detection core circuit in an embodiment of this application. Figure 3 This is a circuit diagram illustrating a specific example of the output stage circuit in an embodiment of this application. Detailed Implementation

[0018] To make the technical solution and beneficial effects of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0019] The embodiments described in this application are not exhaustive, but merely illustrative of some embodiments, and are not intended to limit the scope of protection of this application. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined with each other. For example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0020] In each embodiment of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0021] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application.

[0022] In the embodiments of this application, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the aforementioned," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular expression or a plural expression.

[0023] In the embodiments of this application, "multiple" refers to two or more.

[0024] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0025] The prefixes "first," "second," etc., used in the embodiments of this application are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects is based on the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, the numerical value of the descriptive object is not limited by ordinal numbers and can be one or more. Taking "first device" as an example, the numerical value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the descriptive object is "device," then "first device" and "second device" can be the same device or different devices, and their types can be the same or different.

[0026] In some embodiments, the term "connection" can refer to the transmission of electrical signals or data between the connected end and the connected end, and can be understood as "electrical connection," "communication connection," etc. A "connection" can be a direct connection between two components, an indirect connection established through other components, a connection within two components, or any other possible form of connection.

[0027] In some embodiments, the terms “greater than”, “greater than or equal to”, “not less than”, “more than”, “more than or equal to”, “not less than”, “higher than”, “higher than or equal to”, “not lower than”, “above”, “exceeding”, etc. can be used interchangeably, and the terms “less than”, “less than or equal to”, “not greater than”, “less than”, “less than or equal to”, “not more than”, “lower than”, “lower than or equal to”, “not higher than”, “below”, etc. can be used interchangeably.

[0028] In some embodiments, high voltage and low voltage, or high voltage and low voltage, or high level and low level, can be relative values, not necessarily absolute values.

[0029] In some embodiments, a transistor can be a single transistor; or it can be multiple transistors connected in series and / or parallel, each having functional electrodes corresponding to the individual functional electrodes of a single transistor, and also having the same operating states as a single transistor, such as on and off states. For example, a single transistor may include a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), whose functional electrodes may include a gate (G), a source (S), a drain (D), and a substrate (B). Multiple transistors connected in series and / or parallel have gate G, source S, drain D, and substrate B corresponding to the gate G, source S, drain D, and substrate B of a single MOSFET, and operating states corresponding to the single MOSFET. MOSFETs may include P-type MOSFETs (PMOS transistors) and N-type MOSFETs (NMOS transistors).

[0030] In some embodiments, a transistor may include a control terminal, a first signal terminal, and a second signal terminal. Its operating principle is that, under the control of a control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off, thereby connecting or blocking signal transmission between the first signal terminal and the second signal terminal. In exemplary embodiments, the transistor may include at least one of the following: a MOSFET; a BJT (bipolar junction transistor); an IGBT (insulated gate bipolar transistor); a GTO (gate turn-off thyristor); a SCR (silicon controlled rectifier); an MCT (MOS-controlled thyristor); an IGCT (integrated gate commutated thyristor); an IEGT (electron injection enhancement gate transistor); and so on.

[0031] This application provides a peak detector. Figure 1 A circuit diagram illustrating a specific example of a peak detector according to an embodiment of this application is shown. As shown, the peak detector includes: The peak detection core circuit 10 is configured to perform peak detection on the input radio frequency signal RF_IN based on the nonlinear rectification of the first transistor circuit and the static operating point error cancellation of the second transistor circuit in the transistor pair circuit, so as to obtain a differential output composed of the first signal vp and the second signal vn; wherein, the DC component V0 of the radio frequency signal RF_IN is determined according to the first signal vp and the second signal vn. The output stage circuit 20 is configured to convert the differential output of the peak detection core circuit 10 into a single-ended output, and output the single-ended output through a source follower to obtain the output signal Vout of the peak detector.

[0032] Thus, this embodiment of the application, through a peak detector including a peak detection core circuit, an output stage circuit, and a bias circuit, enables a monolithic RF peak detector implemented using transistor-pair circuits based on CMOS technology, providing a low-cost solution for realizing a complete system-on-a-chip (SoC). Furthermore, by utilizing a source follower for the single-ended output in the output stage circuit, the load-driving capability of the peak detector is improved, thus meeting the application requirements where the load of the peak detector is often resistive. Moreover, the static operating point error cancellation effect of the second transistor circuit in the transistor-pair circuit eliminates peak detection distortion of the RF signal, improving detection accuracy.

[0033] In the embodiments of this application, the transistor pair circuit may be an NMOS transistor pair, but is not limited to this. The transistor pair circuit may also be a PMOS transistor pair, a BJT transistor pair, etc.; or the transistor pair circuit may include other transistors in addition to transistor pairs.

[0034] Figure 2A circuit diagram of a specific example of the peak detection core circuit in an embodiment of this application is shown. As shown, in an optional embodiment, the peak detection core circuit 10 includes a first NMOS transistor M1, a second NMOS transistor M2, a first resistor R1, a second resistor R2, a third capacitor C3, a fourth capacitor C4, a first bias current source I1, and a second bias current source I2; The gate of the first NMOS transistor M1 is configured as the input terminal of the first transistor circuit and acquires the radio frequency signal RF_IN, and is connected to the first terminal of the first resistor R1; the source of the first NMOS transistor M1 is connected to the ground terminal GND through the first bias current source I1, and is connected to the first terminal of the third capacitor C3, and is configured to output the first signal vp. The gate of the second NMOS transistor M2 is configured as the input terminal of the second transistor circuit and connected to the first terminal of the second resistor R2; the source of the second NMOS transistor M2 is connected to ground GND through the second bias current source I2 and connected to the first terminal of the fourth capacitor C4, and configured to output the second signal vn. The drain of the first NMOS transistor M1, the second terminal of the first resistor R1, the drain of the second NMOS transistor M2, and the second terminal of the second resistor R2 are connected to the power supply terminal VDD, respectively; the second terminal of the third capacitor C3 and the second terminal of the fourth capacitor C4 are connected to the ground terminal GND, respectively.

[0035] In this embodiment, the first NMOS transistor M1 can be the first transistor circuit in a transistor pair circuit, and its function can be a nonlinear rectifier. The second NMOS transistor M2 can be the second transistor circuit in a transistor pair circuit, and its function can be to compensate for the error of the DC component V0 at the static operating point.

[0036] The first resistor R1 is connected between the gate and drain of the first NMOS transistor M1, and the second resistor R2 is connected between the gate and drain of the second NMOS transistor M2. This prevents the MOS transistor from being accidentally turned on and damaged due to a voltage difference between the drain and source (DS) if the gate is left floating. Simultaneously, when there is no gate drive signal, this resistor can fix the gate potential of the MOS transistor at a low state, thereby avoiding false triggering and ensuring reliable switching.

[0037] The capacitance value of the third capacitor C3 can be determined based on ensuring that the small signal ∆V0 changes on the output DC component V0. The function of the fourth capacitor C4 is to filter out noise and prevent it from affecting the DC component V0.

[0038] In an exemplary embodiment, the first resistor R1 and the second resistor R2 can be a single resistor, or multiple resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.

[0039] The third capacitor C3 and the fourth capacitor C4 can be a single capacitor, or multiple capacitors connected in series and / or in parallel. They can also be a passive capacitor network including resistors, capacitors, inductors, etc., or an active capacitor network.

[0040] In an optional embodiment, the capacitance value of the third capacitor C3 is calculated using the following formula:

[0041]

[0042] Where C3 represents the capacitance of the third capacitor C3, and I1 represents the output current of the first bias current source I1. This represents half the period of the radio frequency signal RF_IN (the input small AC signal). It represents the peak value of the small signal change on the DC component V0.

[0043] In an optional embodiment, the peak detection core circuit 10 further includes an input coupling module 101, configured to transmit only the radio frequency signal RF_IN to the input terminal of the first transistor circuit.

[0044] Thus, since there are some DC signals and spurious signals in the radio frequency circuit, these signals will affect the transmission of the radio frequency signal and interfere with the transmission of the radio frequency signal. The input coupling module can block the DC signal from passing through and filter out the spurious signal, while allowing the radio frequency signal to pass through, thereby ensuring the quality of the radio frequency signal.

[0045] In an optional embodiment, the input coupling module 101 includes a first capacitor C1 and a second capacitor C2; The first terminal of the second capacitor C2 is configured to acquire the radio frequency signal RF_IN, and the second terminal of the second capacitor C2 is connected to the input terminal of the first transistor circuit. The first terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2, and the second terminal of the first capacitor C1 is connected to the ground terminal GND.

[0046] In an exemplary embodiment, the second terminal of the second capacitor C2 can be connected to the first terminal of the first resistor R1 and the gate of the first NMOS transistor M1, respectively.

[0047] It is understood that the specific circuit structure of the input coupling module 101 is not limited to... Figure 2 The structure shown can also be modified to use other filtering and coupling circuits depending on actual needs.

[0048] Figure 3A circuit diagram illustrating a specific example of the output stage circuit in an embodiment of this application is shown. As shown, in an optional embodiment, the output stage circuit 20 includes: Subtractor 201 is configured to determine and output a third signal vq based on the first signal vp and the second signal vn; The source follower 202 is configured to determine the output signal Vout based on the third signal vq.

[0049] Thus, since the peak detection core circuit 10 has a differential output, it is not easy to measure in practical applications. Therefore, a subtractor is used to convert the differential output into a single-ended output, reducing the measurement difficulty. Furthermore, by using a source follower for the output stage, the peak detector can better drive larger loads.

[0050] In an optional embodiment, the subtractor 201 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and an operational amplifier U1; The first terminal of the third resistor R3 is configured to acquire the first signal vp. The second terminal of the third resistor R3 is connected to the first terminal of the fourth resistor R4 and the first input terminal of the operational amplifier U1, respectively. The second terminal of the fourth resistor R4 is connected to the ground terminal GND. The first terminal of the fifth resistor R5 is configured to acquire the second signal vn, and the second terminal of the fifth resistor R5 is connected to the second input terminal of the operational amplifier U1 and the first terminal of the sixth resistor R6 respectively; the second terminal of the sixth resistor R6 is configured to acquire the output signal Vout. The output of operational amplifier U1 is configured to output the third signal vq.

[0051] In an optional embodiment, the source follower 202 includes a third NMOS transistor M3 and a third bias current source I3; The gate of the third NMOS transistor M3 is configured to acquire the third signal vq; the drain of the third NMOS transistor M3 is connected to the power supply terminal VDD; the source of the third NMOS transistor M3 is connected to the ground terminal GND via the third bias current source I3 and is configured to output the output signal Vout.

[0052] In an exemplary embodiment, the source of the third NMOS transistor M3 is connected to the second terminal of the sixth resistor R6 and the third bias current source I3, respectively.

[0053] It is understandable that the specific circuit structure of subtractor 201 and source follower 202 is not limited to... Figure 3 The structure shown can also be adapted to other differential output to single-ended output circuits and source followers, depending on actual needs.

[0054] refer to Figure 1In an optional embodiment, the peak detector further includes: The bias circuit 30 is configured to provide a current source for the peak detection core circuit 10 and the output stage circuit 20 based on a current mirror structure.

[0055] Thus, the embodiments of this application improve the stability of the current source through the current mirror structure of the bias circuit, thereby improving the peak detection accuracy.

[0056] In an optional embodiment, the bias circuit 30 includes a fourth NMOS transistor M4, a fifth NMOS transistor M5, and a sixth PMOS transistor M6; The first bias current source I1 of the peak detection core circuit 10 includes the seventh NMOS transistor M7; The second bias current source I2 of the peak detection core circuit 10 includes an eighth NMOS transistor M8. The third bias current source I3 of the output stage circuit 20 includes the ninth NMOS transistor M9; The drain of the fourth NMOS transistor M4 is configured to obtain the reference current Iref, and is connected to the gates of the fourth NMOS transistor M4, the fifth NMOS transistor M5, the seventh NMOS transistor M7, the eighth NMOS transistor M8, and the ninth NMOS transistor M9, respectively; the sources of the fourth NMOS transistor M4, the fifth NMOS transistor M5, the seventh NMOS transistor M7, the eighth NMOS transistor M8, and the ninth NMOS transistor M9 are connected to the ground terminal GND, respectively. The drain of the fifth NMOS transistor M5 is connected to the drain and gate of the sixth PMOS transistor M6, respectively; the source of the sixth PMOS transistor M6 is connected to the power supply terminal VDD. The drain of the seventh NMOS transistor M7 is connected to the source of the first NMOS transistor M1 of the peak detection core circuit 10; the drain of the eighth NMOS transistor M8 is connected to the source of the second NMOS transistor M2 of the peak detection core circuit 10; and the drain of the ninth NMOS transistor M9 is connected to the source of the third NMOS transistor M3 of the source follower.

[0057] In this embodiment, the fourth NMOS transistor M4 and the fifth NMOS transistor M5 can form a current mirror structure, and the seventh NMOS transistor M7 and the fourth NMOS transistor M4, the eighth NMOS transistor M8 and the fourth NMOS transistor M4 can each form a current mirror structure, thereby providing a current source for the peak detection core circuit 10; the ninth NMOS transistor M9 and the fourth NMOS transistor M4 can form a current mirror structure, thereby providing a current source for the output stage circuit 20.

[0058] It is understandable that the specific circuit structure of the bias current source in the peak detection core circuit 10 and the output stage circuit 20 is not limited to... Figure 1 The structure shown can also be adapted to other current sources depending on actual needs.

[0059] Thus, this application provides a monolithic radio frequency peak detector (RF detector) implemented using NMOS transistors based on CMOS technology, which provides a low-cost solution for realizing a complete system-on-a-chip (SoC) and improves the load-carrying capacity of the RF detector.

[0060] The reference current Iref can be provided by an external reference circuit, or it can be set according to actual needs. The external reference circuit can be an existing circuit, which will not be described in detail here.

[0061] This application also provides a radio frequency module, which includes a peak detector as described in the above embodiments.

[0062] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this application. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A peak detector, characterized in that, The peak detector includes: The peak detection core circuit is configured to perform peak detection on the input radio frequency signal based on the nonlinear rectification of the first transistor circuit and the static operating point error cancellation of the second transistor circuit in the transistor pair circuit, so as to obtain a differential output composed of the first signal and the second signal; wherein, the DC component of the radio frequency signal is determined according to the first signal and the second signal; The output stage circuit is configured to convert the differential output of the peak detection core circuit into a single-ended output, and output the single-ended output through a source follower to obtain the output signal of the peak detector.

2. The peak detector according to claim 1, characterized in that, The peak detection core circuit includes a first NMOS transistor, a second NMOS transistor, a first resistor, a second resistor, a third capacitor, a fourth capacitor, a first bias current source, and a second bias current source. The gate of the first NMOS transistor is configured as the input terminal of the first transistor circuit and acquires the radio frequency signal, and is connected to the first terminal of the first resistor; the source of the first NMOS transistor is connected to the ground terminal through the first bias current source and is connected to the first terminal of the third capacitor, and is configured to output the first signal. The gate of the second NMOS transistor is configured as the input terminal of the second transistor circuit and is connected to the first terminal of the second resistor; The source of the second NMOS transistor is connected to ground via a second bias current source and connected to the first terminal of the fourth capacitor, and configured to output the second signal; The drain of the first NMOS transistor, the second terminal of the first resistor, the drain of the second NMOS transistor, and the second terminal of the second resistor are respectively connected to the power supply terminal; the second terminals of the third capacitor and the fourth capacitor are respectively connected to the ground terminal.

3. The peak detector according to claim 1, characterized in that, The peak detection core circuit also includes an input coupling module, configured to transmit only the radio frequency signal to the input terminal of the first transistor circuit.

4. The peak detector according to claim 3, characterized in that, The input coupling module includes a first capacitor and a second capacitor; The first terminal of the second capacitor is configured to acquire radio frequency signals, and the second terminal of the second capacitor is connected to the input terminal of the first transistor circuit. The first terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the first capacitor is connected to ground.

5. The peak detector according to claim 1, characterized in that, The output stage circuit includes: A subtractor configured to determine and output a third signal based on the first signal and the second signal; A source follower configured to determine the output signal based on the third signal.

6. The peak detector according to claim 5, characterized in that, The subtractor includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and an operational amplifier; The first terminal of the third resistor is configured to acquire the first signal, and the second terminal of the third resistor is connected to the first terminal of the fourth resistor and the first input terminal of the operational amplifier, respectively; the second terminal of the fourth resistor is connected to ground. The first terminal of the fifth resistor is configured to acquire the second signal, and the second terminal of the fifth resistor is connected to the second input terminal of the operational amplifier and the first terminal of the sixth resistor, respectively; the second terminal of the sixth resistor is configured to acquire the output signal. The output of the operational amplifier is configured to output a third signal.

7. The peak detector according to claim 5, characterized in that, The source follower includes a third NMOS transistor and a third bias current source; The gate of the third NMOS transistor is configured to acquire a third signal; the drain of the third NMOS transistor is connected to the power supply terminal; the source of the third NMOS transistor is connected to the ground terminal via a third bias current source and is configured to output the output signal.

8. The peak detector according to any one of claims 1-7, characterized in that, The peak detector also includes: The bias circuit is configured based on a current mirror structure to provide a current source for the peak detection core circuit and the output stage circuit.

9. The peak detector according to claim 8, characterized in that, The bias circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth PMOS transistor; The first bias current source of the peak detection core circuit includes a seventh NMOS transistor; The second bias current source of the peak detection core circuit includes an eighth NMOS transistor; The third bias current source of the output stage circuit includes a ninth NMOS transistor; The drain of the fourth NMOS transistor is configured to obtain a reference current and is connected to the gates of the fourth, fifth, seventh, eighth, and ninth NMOS transistors, respectively; the sources of the fourth, fifth, seventh, eighth, and ninth NMOS transistors are connected to ground. The drain of the fifth NMOS transistor is connected to the drain of the sixth PMOS transistor and the gate of the sixth PMOS transistor, respectively; the source of the sixth PMOS transistor is connected to the power supply terminal. The drain of the seventh NMOS transistor is connected to the source of the first NMOS transistor in the peak detection core circuit; the drain of the eighth NMOS transistor is connected to the source of the second NMOS transistor in the peak detection core circuit; and the drain of the ninth NMOS transistor is connected to the source of the third NMOS transistor in the source follower.

10. A radio frequency module, characterized in that, The radio frequency module includes a peak detector as described in any one of claims 1-9.

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