Reset circuit and intelligent board card system

Abstract

The utility model provides a kind of reset circuit and intelligent board card system, the reset circuit includes reset output circuit, keying circuit and latching circuit;One end of the reset output circuit is connected with the control circuit of the intelligent board card system;The keying circuit is connected with the control circuit;One end of the latching circuit is connected with the reset output circuit and the control circuit respectively, the other end of the latching circuit is connected with the control circuit, for according to the clear signal shutdown of the control circuit output;Wherein, when the keying circuit is conducted or when the control circuit outputs reset signal, the latching circuit is conducted, and the reset output circuit outputs reset signal to the control circuit.The utility model can avoid circuit always reset, improve stability and service life.

Description

Technical Field

[0001] This utility model relates to the field of circuit board technology, specifically to a reset circuit and an intelligent circuit board system. Background Technology

[0002] Traditional reset circuits are usually pure hardware reset circuits. However, pure hardware reset circuits are prone to abnormalities that can lead to a cycle of resets. For example, when the minimum system power supply is abnormal, the reset circuit will become paralyzed and unable to restart automatically, thus continuously resetting. This not only results in poor circuit stability but also reduces the service life of the circuit. Utility Model Content

[0003] This invention provides a reset circuit and an intelligent board system, aiming to solve the problems of poor stability and short service life of current reset circuits.

[0004] In a first aspect, this utility model provides a reset circuit applied to an intelligent board system. The reset circuit includes a reset output circuit, a button circuit, and a latch circuit. One end of the reset output circuit is connected to the control circuit of the intelligent board system. The button circuit is connected to the control circuit. One end of the latch circuit is connected to both the reset output circuit and the control circuit, and the other end of the latch circuit is connected to the control circuit, used to turn off according to a clear signal output by the control circuit. Specifically, when the button circuit is turned on or when the control circuit outputs a reset signal, the latch circuit is turned on, and the reset output circuit outputs a reset signal to the control circuit.

[0005] Furthermore, the button circuit includes a first switch, one end of which is connected to the control circuit, and the other end of which is grounded.

[0006] Furthermore, the button circuit also includes a first diode, a first resistor, and a second resistor; one end of the first resistor is connected to the control circuit, the other end of the first resistor is connected to a positive terminal of the first diode and the first switch respectively, the other positive terminal of the first diode is grounded, one end of the second resistor is connected to the power supply terminal, and the other end of the second resistor is connected to the first switch.

[0007] Furthermore, the latching circuit includes a first switching transistor and a second switching transistor; the controlled terminal of the first switching transistor is connected to the control circuit, the first electrode of the first switching transistor is connected to the control circuit, the second electrode of the first switching transistor is connected to the controlled terminal of the second switching transistor, the first electrode of the second switching transistor is grounded, and the second electrode of the second switching transistor is connected to the reset output circuit.

[0008] Furthermore, the latching circuit also includes a second diode, the negative terminal of which is connected to the control circuit and the reset output circuit, respectively, and the positive terminal of which is connected to the controlled terminal of the first switching transistor and the second terminal of the second switching transistor, respectively.

[0009] Furthermore, the latching circuit also includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first capacitor; one end of the third resistor is connected to the control circuit, the other end of the third resistor is connected to one end of the first capacitor, the first terminal of the first switching transistor, and one end of the fourth resistor, one end of the fifth resistor is connected to one end of the fourth resistor, the other end of the fifth resistor is connected to the power supply terminal, the other end of the fourth resistor is connected to the controlled terminal of the first switching transistor, one end of the sixth resistor is connected to the second terminal of the first switching transistor, and the other end of the sixth resistor is grounded.

[0010] Furthermore, the reset output circuit includes a reset chip and a third switching transistor; one end of the reset chip is connected to the latch circuit, the other end of the reset chip is connected to the controlled terminal of the third switching transistor, the first terminal of the third switching transistor is grounded, and the second terminal of the third switching transistor is connected to the control circuit.

[0011] Furthermore, the reset output circuit also includes a second capacitor, a third capacitor, a seventh resistor, and an eighth resistor; one end of the second capacitor is connected to the latch circuit, the other end of the second capacitor is connected to one end of the seventh resistor, the other end of the seventh resistor is connected to one end of the third capacitor and the reset chip respectively, the other end of the third capacitor is grounded, one end of the eighth resistor is connected to the power supply terminal, and the other end of the eighth resistor is connected to the reset chip.

[0012] Furthermore, the reset output circuit also includes a fourth capacitor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; one end of the fourth capacitor, one end of the ninth resistor, and one end of the tenth resistor are all connected to the reset chip, the other end of the fourth capacitor is grounded, the other end of the ninth resistor is connected to the controlled terminal of the third switching transistor, the other end of the tenth resistor is connected to the control circuit, one end of the eleventh resistor and one end of the twelfth resistor are both connected to the power supply terminal, the other end of the eleventh resistor is connected to the ninth resistor, and the other end of the twelfth resistor is connected to the control circuit.

[0013] Secondly, this utility model also provides an intelligent board system, which includes a control circuit and a reset circuit as described in any of the above claims.

[0014] The intelligent board system disclosed in this utility model includes a reset circuit and a control circuit. The reset circuit includes a reset output circuit, a key circuit, and a latch circuit. The key circuit is connected to the control circuit, and the latch circuit is connected to both the control circuit and the reset output circuit. The reset output circuit is connected to the control circuit. When the key circuit is turned on or when the control circuit outputs a reset signal, the latch circuit is turned on, and then outputs a reset signal to the reset output circuit. The reset output circuit outputs the reset signal to the control circuit for reset. When the reset is canceled, the control circuit can output a clear signal to the latch circuit, causing the latch circuit to turn off, thereby restoring normal operation and avoiding continuous reset of the circuit, thus improving the stability and service life of the circuit. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a block diagram of a reset circuit provided in an embodiment of the present invention;

[0017] Figure 2 This is a circuit diagram of a reset circuit provided in one embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0019] It should be understood that, when used in this specification and the appended claims, the terms “comprising” and “including” indicate the presence of the described features, integrals, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0021] Furthermore, the directional terms used in this invention, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are only for reference to the accompanying drawings and the product's usage state. Therefore, the directional terms used are for explaining and understanding this invention, and not for limiting it. Additionally, in the accompanying drawings, structures that are similar or identical are indicated by the same reference numerals.

[0022] See Figures 1 to 2 , Figure 1 This is a block diagram of a reset circuit 100 provided in an embodiment of the present invention; Figure 2 This is a circuit diagram of a reset circuit 100 provided in one embodiment of this utility model. Figure 1 As shown, the reset circuit 100 includes a reset output circuit 10, a button circuit 20, and a latch circuit 30. One end of the reset output circuit 10 is connected to the control circuit 200 of the intelligent board system. The button circuit 20 is connected to the control circuit 200. One end of the latch circuit 30 is connected to both the reset output circuit 10 and the control circuit 200, and the other end of the latch circuit 30 is connected to the control circuit 200, used to turn off according to the clear signal output by the control circuit 200. When the button circuit 20 is turned on or when the control circuit 200 outputs a reset signal, the latch circuit 30 is turned on, and the reset output circuit 10 outputs a reset signal to the control circuit 200.

[0023] Specifically, the intelligent board system may include a control circuit 200 and a reset circuit 100. The reset circuit 100 may include a reset output circuit 10, a button circuit 20, and a latch circuit 30. The reset output circuit 10 is connected to the control circuit 200 and can directly output a reset signal to the control circuit 200 to initialize the system when it is powered on. The button circuit 20 is connected to the control circuit 200 and may include a button. When the button is not pressed, the button circuit 20 is not conductive; when the button is pressed, the circuit is conductive and can pull down the signal output by the control circuit 200.

[0024] The latch circuit 30 is connected to both the reset output circuit 10 and the control circuit 200. When the latch circuit 30 is turned on, it can output a reset signal to reset the system. The latch circuit 30 can be turned on using either a hardware or software method. The hardware method involves turning on the button circuit 20 via a button, while the software method involves the control circuit 200 directly outputting a reset signal to turn on the latch circuit 30.

[0025] In actual use, if button circuit 20 is pressed, latch circuit 30 is activated, outputting a reset signal to reset output circuit 10. Reset output circuit 10 then sends a reset signal to control circuit 200 to reset the system. If control circuit 200 outputs a reset signal, latch circuit 30 is also activated, outputting a reset signal to reset output circuit 10. Reset output circuit 10 then sends a reset signal to control circuit 200. Once the system reset is complete, control circuit 200 can output a clear signal to latch circuit 30, thereby deactivating latch circuit 30. Latch circuit 30 then stops outputting reset signals, and the system returns to normal.

[0026] In a further embodiment, the button circuit 20 includes a first switch SW1, one end of which is connected to the control circuit 200, and the other end of which is grounded. Further, the button circuit 20 also includes a first diode D1, a first resistor R1, and a second resistor R2; one end of the first resistor R1 is connected to the control circuit 200, and the other end of the first resistor R1 is connected to both a positive terminal of the first diode D1 and the first switch SW1, with the other positive terminal of the first diode D1 grounded; one end of the second resistor R2 is connected to a power supply terminal, and the other end of the second resistor R2 is connected to the first switch SW1.

[0027] The button circuit 20 may include a first switch SW1, which may be a mechanical button switch. One end of the first switch SW1 is connected to the control circuit 200 through a first resistor R1. The first switch SW1 is also connected to the power supply terminal through a second resistor R2, and is powered by the power supply terminal.

[0028] like Figure 2As shown, RST_BTNn is used to simulate pressing the first switch SW1 when the system needs to be reset via software. That is, RST_BTNn is a software reset output port. When the software reset is in operation, RST_BTNn is a pure output; when the system resets and restarts, RST_BTNn is in input mode. The SOC typically has a 100K resistor pulling it up, and it is also pulled up by the second resistor R2. RST_BTNn is the reset signal output by the control circuit 200. When the first switch SW1 is pressed, the button circuit 20 is turned on, the RST_BTNn signal is pulled low, and the latch circuit 30 is turned on. That is, when a reset is not required, the RST_BTNn signal is high; when the first switch SW1 is pressed, RST_BTNn is low.

[0029] In a further embodiment, the latching circuit 30 includes a first switching transistor Q1 and a second switching transistor Q2; the controlled terminal of the first switching transistor Q1 is connected to the control circuit 200, the first electrode of the first switching transistor Q1 is connected to the control circuit 200, the second electrode of the first switching transistor Q1 is connected to the controlled terminal of the second switching transistor Q2, the first electrode of the second switching transistor Q2 is grounded, and the second electrode of the second switching transistor Q2 is connected to the reset output circuit 10. Further, the latching circuit 30 also includes a second diode D2, the cathode of the second diode D2 is connected to both the control circuit 200 and the reset output circuit 10, and the anode of the second diode D2 is connected to both the controlled terminal of the first switching transistor Q1 and the second electrode of the second switching transistor Q2. Furthermore, the latching circuit 30 also includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a first capacitor C1; one end of the third resistor R3 is connected to the control circuit 200, and the other end of the third resistor R3 is connected to one end of the first capacitor C1, the first terminal of the first switching transistor Q1, and one end of the fourth resistor R4, respectively; one end of the fifth resistor R5 is connected to one end of the fourth resistor R4, and the other end of the fifth resistor R5 is connected to the power supply terminal; the other end of the fourth resistor R4 is connected to the controlled terminal of the first switching transistor Q1; one end of the sixth resistor R6 is connected to the second terminal of the first switching transistor Q1, and the other end of the sixth resistor R6 is grounded.

[0030] The latching circuit 30 may include a first switching transistor Q1 and a second switching transistor Q2. Both the first switching transistor Q1 and the second switching transistor Q2 may be transistors. The base of the first switching transistor Q1 is connected to the control circuit 200, the emitter of the first switching transistor Q1 is connected to the control circuit 200, and the collector of the first switching transistor Q1 is grounded. The base of the second switching transistor Q2 is connected to the collector of the first switching transistor Q1, the emitter of the second switching transistor Q2 is grounded, and the collector of the second switching transistor Q2 is connected to the reset output circuit 10.

[0031] like Figure 2 As shown, the RST_BTN_LATCHn signal is output to the base of the first switching transistor Q1 through the third resistor R3 and the fourth resistor R4. The base of the first switching transistor Q1 is also connected to the RST_BTNn signal through the second diode D2. The base of the second switching transistor Q2 is connected to the collector of the first switching transistor Q1. When the button circuit 20 is turned on, the RST_BTNn signal is pulled low, the first switching transistor Q1 is turned on, and then the second switching transistor Q2 is turned on. The second switching transistor Q2 clamps the base of the first switching transistor Q1 at a level of about 0.1V. Therefore, the voltage at the emitter of the first switching transistor Q1 is about 0.8V. At this time, the RST_BTN_LATCHn signal serves as the output signal of the latch circuit 30. The control circuit 200 confirms through the RST_BTN_LATCHn signal that the voltage of the latch circuit 30 is 0.8V, which is less than 1V, and confirms that the circuit is in a reset state. Similarly, when the RST_BTNn signal is directly low, even if the button circuit 20 is not turned on, the first switch Q1 and the second switch Q2 will be turned on successively. When the reset is complete and the reset state needs to be released, the RST_BTN_LATCHn signal can be used as the input signal of the latch circuit 30. That is, the control circuit 200 can configure the interface connected to the RST_BTN_LATCHn signal from the input mode to the output mode and output a low level, i.e., the RST_BTN_LATCHn signal is a low level signal. At this time, the emitter of the first switch Q1 is pulled to 0V, the first switch Q1 and the second switch Q2 are turned off, and the latch circuit 30 stops outputting the reset signal. Then, the RST_BTN_LATCHn signal is configured as the input signal again, the emitter of the first switch Q1 is pulled up to a high level by the fifth resistor R5, the RST_BTN_LATCHn signal output is high level, and the control circuit 200 recognizes the high level signal to confirm that the circuit has returned to normal.

[0032] The purpose of the RST_BTN_LATCHn interface is to ensure that if the system is in a reset / reboot state, and the RST_BTN_LATCHn port reads a low level, the software system will know that the reboot was caused by pressing the reset button or being controlled by the RST_BTNn port, and will directly start the system and display the screen normally. Otherwise, after the system is set up for the first power-on, subsequent ACOFF / ON operations will not display the screen. This prevents the smart product from automatically restarting and disturbing the neighbors if power is interrupted and then restored. In this case, the reset button needs to be pressed for the display device to restart and display the screen normally.

[0033] In a further embodiment, the reset output circuit 10 includes a reset chip U1 and a third switching transistor Q3; one end of the reset chip U1 is connected to the latch circuit 30, and the other end of the reset chip U1 is connected to the controlled terminal of the third switching transistor Q3. The first terminal of the third switching transistor Q3 is grounded, and the second terminal of the third switching transistor Q3 is connected to the control circuit 200. Further, the reset output circuit 10 also includes a second capacitor C2, a third capacitor C3, a seventh resistor R7, and an eighth resistor R8; one end of the second capacitor C2 is connected to the latch circuit 30, and the other end of the second capacitor C2 is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to one end of the third capacitor C3 and the reset chip U1, respectively. The other end of the third capacitor C3 is grounded. One end of the eighth resistor R8 is connected to the power supply terminal, and the other end of the eighth resistor R8 is connected to the reset chip U1. Furthermore, the reset output circuit 10 also includes a fourth capacitor, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor; one end of the fourth capacitor, one end of the ninth resistor R9, and one end of the tenth resistor R10 are all connected to the reset chip U1, the other end of the fourth capacitor is grounded, the other end of the ninth resistor R9 is connected to the controlled terminal of the third switch Q3, the other end of the tenth resistor R10 is connected to the control circuit 200, one end of the eleventh resistor R11 and one end of the twelfth resistor are both connected to the power supply terminal, the other end of the eleventh resistor R11 is connected to the ninth resistor R9, and the other end of the twelfth resistor is connected to the control circuit 200.

[0034] The reset output circuit 10 may include a reset chip U1 and a third switching transistor Q3. The reset chip U1 is connected to the latch circuit 30 through a seventh resistor R7 and a second capacitor C2. The second capacitor C2 is used to isolate DC power and prevent false triggering, and the seventh resistor R7 is used to adjust the pulse. When the system is powered on, the reset chip U1 can output a reset signal to control the circuit 200, which is for system initialization.

[0035] like Figure 2As shown, when the system powers on, +3.3V is established, and the reset chip U1 outputs a reset signal. Alternatively, if the reset chip U1 is not configured, the SOC can have built-in voltage monitoring, and the SOC's internal logic can generate a reset signal, which is output as SOC_RST through the third switch Q3 to initialize the system. During circuit operation, if the latch circuit 30 is turned on, the third switch Q3 will be turned on, allowing the reset signal to be output to the control circuit 200 to reset the system.

[0036] This utility model provides an intelligent board system, which includes a control circuit 200 and a reset circuit 100 as described in any of the above embodiments. The reset circuit 100 includes a reset output circuit 10, a button circuit 20, and a latch circuit 30. One end of the reset output circuit 10 is connected to the control circuit 200 of the intelligent board system. The button circuit 20 is connected to the control circuit 200. One end of the latch circuit 30 is connected to both the reset output circuit 10 and the control circuit 200, and the other end of the latch circuit 30 is connected to the control circuit 200, for turning off according to a clear signal output by the control circuit 200. Specifically, when the button circuit 20 is turned on or when the control circuit 200 outputs a reset signal, the latch circuit 30 is turned on, and the reset output circuit 10 outputs a reset signal to the control circuit 200.

[0037] Specifically, the intelligent board system may include a control circuit 200 and a reset circuit 100. The reset circuit 100 may include a reset output circuit 10, a button circuit 20, and a latch circuit 30. The reset output circuit 10 is connected to the control circuit 200 and can directly output a reset signal to the control circuit 200 to initialize the system when it is powered on. The button circuit 20 is connected to the control circuit 200 and may include a button. When the button is not pressed, the button circuit 20 is not conductive; when the button is pressed, the circuit is conductive and can pull down the signal output by the control circuit 200.

[0038] The latch circuit 30 is connected to both the reset output circuit 10 and the control circuit 200. When the latch circuit 30 is turned on, it can output a reset signal to reset the system. The latch circuit 30 can be turned on using either a hardware or software method. The hardware method involves turning on the button circuit 20 via a button, while the software method involves the control circuit 200 directly outputting a reset signal to turn on the latch circuit 30.

[0039] In actual use, if button circuit 20 is pressed, latch circuit 30 is activated, outputting a reset signal to reset output circuit 10. Reset output circuit 10 then sends a reset signal to control circuit 200 to reset the system. If control circuit 200 outputs a reset signal, latch circuit 30 is also activated, outputting a reset signal to reset output circuit 10. Reset output circuit 10 then sends a reset signal to control circuit 200. Once the system reset is complete, control circuit 200 can output a clear signal to latch circuit 30, thereby deactivating latch circuit 30. Latch circuit 30 then stops outputting reset signals, and the system returns to normal.

[0040] The reset circuit disclosed in this utility model activates the latch circuit when the button circuit is turned on or when the control circuit outputs a reset signal. This causes the latch circuit to output a reset signal to the reset output circuit, which then outputs the reset signal to the control circuit for resetting. When the reset is canceled, the control circuit can output a clear signal to the latch circuit, causing the latch circuit to turn off and return to normal operation. This avoids the circuit from continuously resetting, thus improving the stability and service life of the circuit.

[0041] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A reset circuit, characterized in that, The reset circuit, used in intelligent board systems, includes: A reset output circuit, one end of which is connected to the control circuit of the intelligent board system; A button circuit, wherein the button circuit is connected to the control circuit; A latching circuit, one end of which is connected to the reset output circuit and the control circuit respectively, and the other end of which is connected to the control circuit, for use to turn off according to the clear signal output by the control circuit; Specifically, when the button circuit is turned on or when the control circuit outputs a reset signal, the latch circuit is turned on, and the reset output circuit outputs a reset signal to the control circuit.

2. The reset circuit as described in claim 1, characterized in that, The button circuit includes a first switch, one end of which is connected to the control circuit, and the other end of which is grounded.

3. The reset circuit as described in claim 2, characterized in that, The button circuit also includes a first diode, a first resistor, and a second resistor; One end of the first resistor is connected to the control circuit, and the other end of the first resistor is connected to one positive terminal of the first diode and the first switch respectively. The other positive terminal of the first diode is grounded. One end of the second resistor is connected to the power supply terminal, and the other end of the second resistor is connected to the first switch.

4. The reset circuit as described in claim 1, characterized in that, The latching circuit includes a first switching transistor and a second switching transistor; The controlled terminal of the first switching transistor is connected to the control circuit, the first electrode of the first switching transistor is connected to the control circuit, the second electrode of the first switching transistor is connected to the controlled terminal of the second switching transistor, the first electrode of the second switching transistor is grounded, and the second electrode of the second switching transistor is connected to the reset output circuit.

5. The reset circuit as described in claim 4, characterized in that, The latching circuit further includes a second diode, the negative terminal of which is connected to the control circuit and the reset output circuit, and the positive terminal of which is connected to the controlled terminal of the first switching transistor and the second terminal of the second switching transistor.

6. The reset circuit as described in claim 5, characterized in that, The latching circuit also includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first capacitor; One end of the third resistor is connected to the control circuit, and the other end of the third resistor is connected to one end of the first capacitor, the first terminal of the first switching transistor, and one end of the fourth resistor. One end of the fifth resistor is connected to one end of the fourth resistor, and the other end of the fifth resistor is connected to the power supply terminal. The other end of the fourth resistor is connected to the controlled terminal of the first switching transistor. One end of the sixth resistor is connected to the second terminal of the first switching transistor, and the other end of the sixth resistor is grounded.

7. The reset circuit as described in claim 1, characterized in that, The reset output circuit includes a reset chip and a third switching transistor; One end of the reset chip is connected to the latch circuit, and the other end of the reset chip is connected to the controlled terminal of the third switch transistor. The first terminal of the third switch transistor is grounded, and the second terminal of the third switch transistor is connected to the control circuit.

8. The reset circuit as described in claim 7, characterized in that, The reset output circuit also includes a second capacitor, a third capacitor, a seventh resistor, and an eighth resistor; One end of the second capacitor is connected to the latching circuit, and the other end of the second capacitor is connected to one end of the seventh resistor. The other end of the seventh resistor is connected to one end of the third capacitor and the reset chip. The other end of the third capacitor is grounded. One end of the eighth resistor is connected to the power supply terminal, and the other end of the eighth resistor is connected to the reset chip.

9. The reset circuit as described in claim 7, characterized in that, The reset output circuit also includes a fourth capacitor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; One end of the fourth capacitor, one end of the ninth resistor, and one end of the tenth resistor are all connected to the reset chip. The other end of the fourth capacitor is grounded. The other end of the ninth resistor is connected to the controlled terminal of the third switch. The other end of the tenth resistor is connected to the control circuit. One end of the eleventh resistor and one end of the twelfth resistor are both connected to the power supply terminal. The other end of the eleventh resistor is connected to the ninth resistor. The other end of the twelfth resistor is connected to the control circuit.

10. An intelligent board system, characterized in that, It includes a control circuit and a reset circuit as described in any one of claims 1-9.

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