An equalization circuit and receiver

Abstract

The equalization circuit and the receiver provided by the present disclosure comprise a first common-mode input sub-circuit, a second common-mode input sub-circuit, a load sub-circuit, a first current adjustment sub-circuit and a second current adjustment sub-circuit. The first common-mode input sub-circuit comprises a first transistor and a second transistor. The gates of the first transistor and the second transistor are used for input signals. The second common-mode input sub-circuit comprises a third transistor and a fourth transistor. The gates of the third transistor and the fourth transistor are used for input signals. One end of the load sub-circuit is connected to the sources of the first transistor, the second transistor, the third transistor and the fourth transistor, and the other end is grounded. The first current adjustment sub-circuit comprises a first operational amplifier, a fifth transistor, a sixth transistor and a first capacitor. The second current adjustment sub-circuit comprises a second operational amplifier, a seventh transistor, an eighth transistor and a second capacitor. The equalization circuit and the receiver provided by the present disclosure facilitate reducing the power consumption of the equalization circuit.

Description

Technical Field

[0001] This disclosure relates to the field of electronic and electrical technology, and in particular to an equalization circuit and receiver. Background Technology

[0002] A receiver can receive externally input signals, such as high-frequency signals. High-frequency signals typically experience signal loss when transmitted to the receiver via a transmission line. Furthermore, the signal loss on the transmission line increases with the signal frequency. In fact, when the signal loss on the transmission line reaches a certain level, it can even lead to signal distortion.

[0003] To reduce the impact of signal losses on transmission lines, receivers typically incorporate equalization circuitry at the signal input. The power consumption of this equalization circuitry is a crucial performance characteristic that is of concern to those skilled in the art. Utility Model Content

[0004] Some embodiments provide an equalization circuit and receiver to reduce the power consumption of the equalization circuit.

[0005] Some embodiments provide an equalization circuit, including: The first common-mode input sub-circuit includes a first transistor and a second transistor; the gates of the first transistor and the second transistor are respectively used for input signals. The second common-mode input sub-circuit includes a third transistor and a fourth transistor; the gates of the third transistor and the fourth transistor are respectively used for input signals; The load sub-circuit has one end connected to the source of the first transistor, the second transistor, the third transistor, and the fourth transistor, and the other end grounded. The first current regulation sub-circuit includes a first operational amplifier, a fifth transistor, a sixth transistor, and a first capacitor; wherein, the inverting input terminal of the first operational amplifier is connected to the source of the first transistor and the second transistor, the non-inverting input terminal of the first operational amplifier is connected to the drain of the fifth transistor and the sixth transistor, the output terminal of the first operational amplifier is connected to one end of the first capacitor and the gate of the fifth transistor, the other end of the first capacitor is connected to the drain of the fifth transistor and the drain of the sixth transistor, and the source of the sixth transistor is grounded; The second current regulation sub-circuit includes a second operational amplifier, a seventh transistor, an eighth transistor, and a second capacitor; wherein, the inverting input terminal of the second operational amplifier is connected to the sources of the third and fourth transistors, the non-inverting input terminal of the second operational amplifier is connected to the drains of the seventh and eighth transistors, the output terminal of the second operational amplifier is connected to one end of the second capacitor and the gate of the eighth transistor, the other end of the second capacitor is connected to the drains of the seventh and eighth transistors, and the source of the eighth transistor is grounded.

[0006] One of the above technical solutions has the following advantages or beneficial effects: The input terminals of both the first and second common-mode input sub-circuits are used to input high-frequency signals, and the output terminals of both are used to output the equalized high-frequency signal. The first, second, and load sub-circuits form a dual-channel input equalization circuit. Both the first and second common-mode input sub-circuits are used to perform gain equalization on the input high-frequency signal. A first current adjustment sub-circuit is connected to the first common-mode input sub-circuit, and this first current adjustment sub-circuit is used to dynamically adjust the current of the current bias transistor based on the source voltage of the input transistor of the first common-mode input sub-circuit, so that when the common-mode input of the first common-mode input sub-circuit changes, the first common-mode input sub-circuit can output correctly and stably in common mode. The second current adjustment sub-circuit is connected to the second common-mode input sub-circuit. This sub-circuit dynamically adjusts the current of the current bias transistor based on the source voltage of the input transistor in the second common-mode input sub-circuit, ensuring a correct and stable common-mode output when the input common-mode voltage changes. The first operational amplifier receives source signals from the first and second transistors through its inverting input. Simultaneously, its non-inverting input is connected to the drains of the fifth and sixth transistors, forming a feedback loop. The bias voltage source provides a stable gate voltage to the sixth transistor, ensuring it operates in the saturation region. The first capacitor in the first current adjustment sub-circuit acts as a filter and stabilizer, reducing the impact of high-frequency noise on the output of the first operational amplifier. The second operational amplifier receives source signals from the third and fourth transistors through its inverting input. Simultaneously, its non-inverting input is connected to the drains of the seventh and eighth transistors, forming a feedback loop. The bias voltage source provides a stable gate voltage to the seventh transistor, ensuring it operates in the saturation region. The second capacitor plays a filtering and stabilizing role in the second current regulation sub-circuit, reducing the impact of high-frequency noise on the output of the second operational amplifier.

[0007] In some embodiments, an equalization circuit is provided, wherein the first common-mode input sub-circuit further includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; The gates of the ninth transistor and the tenth transistor are connected to the gate of the fifth transistor; the drains of the ninth transistor and the eleventh transistor are both connected to the drain of the first transistor; the drains of the tenth transistor and the twelfth transistor are both connected to the drain of the second transistor; the gates of the eleventh transistor and the twelfth transistor are used to input bias voltage. The source of the thirteenth transistor is connected to the drain of the eleventh transistor, the source of the fourteenth transistor is connected to the drain of the twelfth transistor, the gate of the thirteenth transistor is connected to the gate of the fourteenth transistor, and the drains of the thirteenth transistor and the fourteenth transistor are connected to the load sub-circuit.

[0008] Another technical solution described above has the following advantages or beneficial effects: By using the ninth to fourteenth transistors, the stability and reliability of the circuit are effectively improved. Simultaneously, the common-mode rejection ratio is significantly improved, thereby maintaining high-quality signal transmission in complex operating environments. Furthermore, through precise control of the bias voltage, the linearity and dynamic range of the first common-mode input sub-circuit are further optimized, enabling the equalization circuit to exhibit superior performance when processing high-frequency signals.

[0009] In some embodiments, an equalization circuit is provided, wherein the first common-mode input sub-circuit further includes a third capacitor, a first resistor, a fifteenth transistor, and a sixteenth transistor; One end of the third capacitor is connected to the gate of the first transistor, and the other end of the third capacitor is connected to the gate of the second transistor; one end of the first resistor is connected to the gate of the first transistor, and the other end of the first resistor is connected to the gate of the second transistor. The drain of the fifteenth transistor is connected to the source of the first transistor, the drain of the sixteenth transistor is connected to the source of the second transistor, the sources of the fifteenth transistor and the sixteenth transistor are grounded, and the gates of the fifteenth transistor and the sixteenth transistor are used to input bias voltage.

[0010] Another technical solution described above has the following advantages or beneficial effects: The third capacitor and the first resistor effectively improve the anti-interference capability of the equalization circuit and optimize the stability of signal transmission. The fifteenth and sixteenth transistors further enhance the linearity of the first common-mode input sub-circuit, enabling it to maintain a high performance level under different operating conditions. Furthermore, the precise input of the bias voltage significantly improves the dynamic response characteristics of the circuit, thereby ensuring reliability and consistency in high-frequency signal processing.

[0011] The first current regulation sub-circuit can detect the common-mode voltage of the sources of the first and second transistors and dynamically adjust the currents of the ninth and tenth transistors so that the currents on the ninth and tenth transistors are consistent with the currents on the fifteenth and sixteenth transistors. When the input common-mode voltage changes, no current flows from the ninth and tenth transistors to the signal output terminal VON / VOP, so that the common-mode voltage at the signal output terminal is determined only by the currents of the eleventh and twelfth transistors and the load sub-circuit, which helps to reduce the power consumption of the first common-mode input sub-circuit.

[0012] In some embodiments, an equalization circuit is provided, wherein the second common-mode input sub-circuit further includes a seventeenth transistor, an eighteenth transistor, a fourth capacitor, and a second resistor; The drain of the seventeenth transistor, one end of the fourth capacitor, and one end of the second resistor are all connected to the source of the third transistor. The drain of the eighteenth transistor, the other end of the fourth capacitor, and the other end of the second resistor are all connected to the source of the fourth transistor. The gates of the seventeenth transistor and the eighteenth transistor are used to input bias voltage.

[0013] Another technical solution described above has the following advantages or beneficial effects: the fourth capacitor and the second resistor effectively improve the anti-interference capability of the equalization circuit and optimize the stability of signal transmission. The seventeenth and eighteenth transistors further enhance the linearity of the second common-mode input sub-circuit, enabling it to maintain a high performance level under different operating conditions. Furthermore, precise input of the bias voltage significantly improves the dynamic response characteristics of the circuit, thereby ensuring reliability and consistency in high-frequency signal processing.

[0014] In some embodiments, an equalization circuit is provided, wherein the second common-mode input sub-circuit further includes a nineteenth transistor and a twentieth transistor; The drain of the nineteenth transistor is connected to the drain of the third transistor, the drain of the twentieth transistor is connected to the drain of the fourth transistor, the source of the nineteenth transistor and the source of the twentieth transistor are respectively grounded, and the gate of the nineteenth transistor and the gate of the twentieth transistor are respectively connected to the output terminal of the second operational amplifier.

[0015] Another technical solution described above has the following advantages or beneficial effects: By using the nineteenth and twentieth transistors, the structure of the second common-mode input sub-circuit is further optimized, enhancing overall performance. This not only effectively reduces common-mode signal interference but also improves the processing accuracy of differential signals. Simultaneously, grounding the sources of the nineteenth and twentieth transistors ensures the stability of the second common-mode input sub-circuit under high load conditions and reduces unnecessary power loss.

[0016] The second current regulation sub-circuit can detect the common-mode voltage of the sources of the third and fourth transistors and dynamically adjust the nineteenth and twentieth transistors to ensure that the current on the nineteenth and twentieth transistors is consistent with the current on the seventeenth and eighteenth transistors. When the input common-mode voltage changes, the nineteenth and twentieth transistors will not draw current from the signal output terminals VON / VOP, so that the common-mode voltage at the signal output terminal is determined only by the load sub-circuit, which helps to reduce the power consumption of the second common-mode input sub-circuit.

[0017] In some embodiments, an equalization circuit is provided, wherein the load sub-circuit includes a third resistor, a fourth resistor, a fifth capacitor, and a sixth capacitor; one end of the third resistor is connected to the drain of the first transistor and the third transistor, one end of the fourth resistor is connected to the drain of the second transistor and the fourth transistor, and the other ends of the third resistor and the fourth resistor are both grounded; one end of the fifth capacitor is connected to one end of the third resistor, one end of the sixth capacitor is connected to one end of the fourth resistor, and the other ends of the fifth capacitor and the sixth capacitor are both grounded.

[0018] Another technical solution described above has the following advantages or beneficial effects: The third resistor and the fifth capacitor are connected in parallel to one output terminal of the first common-mode input sub-circuit and the second common-mode input sub-circuit; the fourth resistor and the sixth capacitor are connected in parallel to the other output terminal of the first common-mode input sub-circuit and the second common-mode input sub-circuit. This optimizes the performance of the load sub-circuit and facilitates improved stability of the equalization circuit. The third and fourth resistors not only effectively share the current but also reduce signal distortion under high-frequency operating conditions. The addition of the fifth and sixth capacitors significantly enhances the circuit's filtering capability, reduces noise interference to the signal, and thus ensures the purity and accuracy of the output signal.

[0019] In some embodiments, an equalization circuit is provided, wherein the first common-mode input sub-circuit further includes a fifth resistor and a sixth resistor; one end of the fifth resistor is connected to the source of the first transistor, the other end of the fifth resistor and one end of the sixth resistor are respectively connected to the inverting input of the first operational amplifier, and the other end of the sixth resistor is connected to the source of the second transistor.

[0020] Another technical solution in the above-mentioned technical solution has the following advantages or beneficial effects: by making the resistance value of the fifth resistor and the resistance value of the sixth resistor the same, the differential mode signal on both sides of the fifth resistor and the sixth resistor is not easily transmitted to the fifth resistor and the sixth resistor, which makes it easier for the first operational amplifier to obtain a stable common mode voltage.

[0021] In some embodiments, an equalization circuit is provided, wherein the second common-mode input sub-circuit further includes a seventh resistor and an eighth resistor; one end of the seventh resistor is connected to the source of the third transistor, the other end of the seventh resistor and one end of the eighth resistor are connected to the inverting input of the second operational amplifier, and the other end of the eighth resistor is connected to the source of the fourth transistor.

[0022] Another technical solution in the above-mentioned technical solution has the following advantages or beneficial effects: by making the resistance value of the seventh resistor and the resistance value of the eighth resistor the same, the differential mode signal on both sides of the seventh resistor and the eighth resistor is not easily transmitted to the seventh resistor and the eighth resistor, which makes it easier for the second operational amplifier to obtain a stable common mode voltage.

[0023] In some embodiments, an equalization circuit is provided, wherein the first current adjustment sub-circuit further includes a seventh capacitor, one end of which is connected to the inverting input of the first operational amplifier, and the other end of which is grounded; The second current adjustment sub-circuit also includes an eighth capacitor, one end of which is connected to the inverting input terminal of the operational amplifier, and the other end of which is grounded.

[0024] Another technical solution described above has the following advantages or beneficial effects: the seventh capacitor, used as a ground capacitor, can filter and make the common-mode voltage of the first and second transistors more stable. The eighth capacitor, used as a ground capacitor, can filter and make the common-mode voltage of the third and fourth transistors more stable.

[0025] In some embodiments, a receiver is provided, including an equalization circuit located at the signal input terminal of the receiver for equalizing the input signal; wherein the equalization circuit is the equalization circuit described in the above embodiments.

[0026] Another technical solution in the above-mentioned technical solution has the following advantages or beneficial effects: the receiver is equipped with the equalization circuit provided in the above embodiment, so that the receiver can use the equalization circuit to perform gain processing on the input signal to equalize the signal. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 This is a structural diagram of a receiver according to some embodiments; Figure 2 This is a structural diagram of an equalization circuit according to some embodiments; Figure 3 A partial structural diagram of an equalization circuit according to some embodiments; Figure 4 for Figure 3 The equalization effect diagram of the first common-mode input sub-circuit in the circuit; Figure 5 A partial structural diagram of another equalization circuit according to some embodiments; Figure 6 A partial structural diagram of another equalization circuit according to some embodiments; Figure 7 This is a structural diagram of another equalization circuit according to some embodiments; Figure 8 for Figure 7 Local structures in Figure 1 ; Figure 9 for Figure 7 Local structures in Figure 2 ; Figure 10 A partial structure of another equalization circuit according to some embodiments Figure 1 ; Figure 11 A partial structure of another equalization circuit according to some embodiments Figure 2 . Detailed Implementation

[0029] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0030] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," or "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0031] Figure 1 This is a structural diagram of a receiver according to some embodiments. Figure 1 As shown, in some embodiments, the receiver 100 is provided with an equalization circuit 200, which is located at the signal input terminal of the receiver 100. The high-frequency signal transmitted to the receiver 100 can be first processed by the equalization circuit 200 to equalize the loss of the high-frequency signal.

[0032] Figure 2 This is a structural diagram of an equalization circuit according to some embodiments. For example... Figure 2As shown, in some embodiments, the equalization circuit 200 includes a first common-mode input sub-circuit 210, a second common-mode input sub-circuit 220, a load sub-circuit 230, a first current adjustment sub-circuit 240, and a second current adjustment sub-circuit 250. The input terminals of both the first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220 are used to input high-frequency signals. The output terminals of both the first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220 are used to output the equalized high-frequency signals. Both the first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220 are used to perform gain equalization on the input high-frequency signals. For example, the first common-mode input sub-circuit 210 can be used for high common-mode equalization, and the second common-mode input sub-circuit 220 can be used for low common-mode equalization; or, the first common-mode input sub-circuit 210 can be used for low common-mode equalization, and the second common-mode input sub-circuit 220 can be used for high common-mode equalization. One end of the load sub-circuit 230 is connected to the output terminal of the first common-mode input sub-circuit 210 and the output terminal of the second common-mode input sub-circuit 220, and the other end of the load sub-circuit 230 is grounded. The first common-mode input sub-circuit 210, the second common-mode input sub-circuit 220, and the load sub-circuit 230 form a dual-channel input equalization circuit. The first current adjustment sub-circuit 240 is connected to the first common-mode input sub-circuit 210. The first current adjustment sub-circuit 240 is used to dynamically adjust the current of the current bias transistor in the first common-mode input sub-circuit 210 based on the source voltage of the input transistor of the first common-mode input sub-circuit 210, so that when the input common-mode voltage of the first common-mode input sub-circuit 210 changes, the first common-mode input sub-circuit 210 can output correctly and stably in common mode. The second current adjustment sub-circuit 250 is connected to the second common-mode input sub-circuit 220. The second current adjustment sub-circuit 250 is used to dynamically adjust the current of the current bias transistor in the second common-mode input sub-circuit 220 based on the source voltage of the input transistor of the second common-mode input sub-circuit 220, so that when the input common-mode of the second common-mode input sub-circuit 220 changes, the second common-mode input sub-circuit 220 can output correctly and stably in common mode.

[0033] In some embodiments, the first common-mode input sub-circuit 210, the second common-mode input sub-circuit 220, and the load sub-circuit 230 form an equalization circuit for NMOS and PMOS dual-channel inputs, which can support a common-mode input range of 0 to VDD. Thus, the NMOS and PMOS dual-channel inputs, combined with the common-mode feedback provided by the first current adjustment sub-circuit 240 and the second current adjustment sub-circuit 250, can reduce the power consumption of the NMOS and PMOS dual-channel inputs and the risk of output common-mode variations with input common-mode variations.

[0034] Figure 3 This is a partial structural diagram of an equalization circuit according to some embodiments. For example... Figure 3As shown, in some implementations, the first common-mode input sub-circuit 210 may include a first transistor 2101 and a second transistor 2102. The gates of the first transistor 2101 and the second transistor 2102 are used to input high-frequency signals. Exemplarily, the gate of the first transistor 2101 can be used as Vinp, and the gate of the second transistor 2102 can be used as Vinn, to input high-frequency differential signals through the first transistor 2101 and the second transistor 2102. The drains of both the first transistor 2101 and the second transistor 2102 are connected to the load sub-circuit 230. The first transistor 2101 can be an NMOS, and the second transistor 2102 can be an NMOS. One end of the load sub-circuit 230 can output the high-frequency signal after equalization processing by the first common-mode input sub-circuit 210.

[0035] In some embodiments, the load sub-circuit 230 may include a load capacitor and a load resistor. One end of the load capacitor may be connected to the drain of the first transistor 2101 or the second transistor 2102, and the other end of the load capacitor may be grounded. One end of the load resistor may be connected to the drain of the first transistor 2101 or the second transistor 2102, and the other end of the load resistor may be grounded or connected to a high level.

[0036] In some embodiments, the first common-mode input sub-circuit 210 may include a third capacitor 2103 and a first resistor 2104. One end of the third capacitor 2103 is connected to the source of the first transistor 2101, and the other end of the third capacitor 2103 is connected to the source of the second transistor 2102. One end of the first resistor 2104 is connected to the source of the first transistor 2101, and the other end of the first resistor 2104 is connected to the source of the second transistor 2102, such that the first resistor 2104 and the third capacitor 2103 are connected in parallel between the sources of the first transistor 2101 and the second transistor 2102. The parallel structure of the third capacitor 2103 and the first resistor 2104 can effectively adjust the transmission characteristics of the common-mode signal, thereby improving the stability of the circuit. By adjusting the capacitance value of the third capacitor 2103 and the resistance value of the first resistor 2104, the response performance of high-frequency signals can be optimized, facilitating more accurate signal processing under different operating conditions.

[0037] In some embodiments, the first common-mode input sub-circuit 210 may include a fifteenth transistor 2105 and a sixteenth transistor 2106. The drain of the fifteenth transistor 2105 is connected to the source of the first transistor 2101, and the source of the fifteenth transistor 2105 is grounded. The drain of the sixteenth transistor 2106 is connected to the source of the second transistor 2102, and the source of the sixteenth transistor 2106 is grounded. The gates of the fifteenth transistor 2105 and the sixteenth transistor 2106 are connected to a bias voltage source to input a bias voltage. The fifteenth transistor 2105 and the sixteenth transistor 2106 can enhance the common-mode rejection capability of the first common-mode input sub-circuit 210. By connecting the drain of the fifteenth transistor 2105 to the source of the first transistor 2101 and the drain of the sixteenth transistor 2106 to the source of the second transistor 2102, unwanted common-mode signals can be effectively shunted. The bias voltage source provides a stable drive voltage to the gates of the fifteenth transistor 2105 and the sixteenth transistor 2106, enabling the circuit to maintain consistent performance under different operating conditions. The fifteenth transistor 2105 and the sixteenth transistor 2106 can both be NMOS.

[0038] Figure 4 for Figure 3 The equalization effect diagram of the first common-mode input sub-circuit in the circuit. (See diagram for example.) Figure 4 As shown, before the equalization peak of the first common-mode input sub-circuit 210, the channel frequency response after equalization processing by the first common-mode input sub-circuit 210 is approximately a straight line.

[0039] Figure 5 This is a partial structural diagram of another equalization circuit according to some embodiments. For example... Figure 5 As shown, in some embodiments, the second common-mode input sub-circuit 220 includes a third transistor 2201 and a fourth transistor 2202. The gates of the third transistor 2201 and the fourth transistor 2202 are used to input high-frequency signals. Exemplarily, the gate of the third transistor 2201 can be used as Vinp, and the gate of the fourth transistor 2202 can be used as Vinn, to input high-frequency differential signals through the third transistor 2201 and the fourth transistor 2202. The drains of both the third transistor 2201 and the fourth transistor 2202 are connected to the load sub-circuit 230. The third transistor 2201 can be a PMOS, and the fourth transistor 2202 can be a PMOS. One end of the load sub-circuit 230 can output the high-frequency signal after equalization processing by the second common-mode input sub-circuit 220.

[0040] In some embodiments, the second common-mode input sub-circuit 220 may include a fourth capacitor 2203 and a second resistor 2204. One end of the fourth capacitor 2203 is connected to the source of the third transistor 2201, and the other end is connected to the source of the fourth transistor 2202. One end of the second resistor 2204 is connected to the source of the third transistor 2201, and the other end is connected to the source of the fourth transistor 2202, such that the second resistor 2204 and the fourth capacitor 2203 are connected in parallel between the sources of the third transistor 2201 and the fourth transistor 2202. The parallel structure of the second resistor 2204 and the fourth capacitor 2203 can effectively adjust the transmission characteristics of the common-mode signal, thereby improving the stability of the circuit. By adjusting the resistance value of the second resistor 2204 and the capacitance value of the fourth capacitor 2203, the response performance of high-frequency signals can be optimized, facilitating more accurate signal processing under different operating conditions.

[0041] In some embodiments, the second common-mode input sub-circuit 220 may include a seventeenth transistor 2205 and an eighteenth transistor 2206. The source of the seventeenth transistor 2205 is connected to a high level, and the drain of the seventeenth transistor 2205 is connected to the source of the third transistor 2201. The source of the eighteenth transistor 2206 is connected to a high level, and the drain of the eighteenth transistor 2206 is connected to the source of the fourth transistor 2202. The gates of the seventeenth transistor 2205 and the eighteenth transistor 2206 are connected to a bias voltage source to input a bias voltage. The seventeenth transistor 2205 and the eighteenth transistor 2206 can enhance the common-mode rejection capability of the second common-mode input sub-circuit 220. By connecting the drain of the seventeenth transistor 2205 to the source of the third transistor 2201 and the drain of the eighteenth transistor 2206 to the source of the fourth transistor 2202, unwanted common-mode signals can be effectively shunted. The bias voltage source provides a stable drive voltage to the gates of the seventeenth transistor 2205 and the eighteenth transistor 2206, enabling the circuit to maintain consistent performance under different operating conditions. The seventeenth transistor 2205 can be a PMOS, and the eighteenth transistor 2206 can be a PMOS.

[0042] Figure 6 This is a partial structural diagram of another equalization circuit according to some embodiments. For example... Figure 6As shown, in some embodiments, the first common-mode input sub-circuit 210 can be a ninth transistor 2107 and a tenth transistor 2108. The drain of the ninth transistor 2107 is connected to the drain of the first transistor 2101, and the source of the ninth transistor 2107 is connected to a high level. The drain of the tenth transistor 2108 is connected to the drain of the second transistor 2102, and the source of the tenth transistor 2108 is connected to a high level. The gates of the ninth transistor 2107 and the tenth transistor 2108 are used to connect to the first current adjustment sub-circuit 240. By receiving signals from the first current adjustment sub-circuit 240, the gates of the ninth transistor 2107 and the tenth transistor 2108 can dynamically adjust their conduction states, thereby effectively suppressing common-mode signals. The high level of the sources of the ninth transistor 2107 and the tenth transistor 2108 provides a stable driving voltage, which helps to enhance the reliability of the circuit. The ninth transistor 2107 can be a PMOS, and the tenth transistor 2108 can be a PMOS.

[0043] In some embodiments, the first common-mode input sub-circuit 210 may include an eleventh transistor 2109 and a twelfth transistor 2110. The drain of the eleventh transistor 2109 is connected to the drain of the first transistor 2101 and the drain of the ninth transistor 2107, and the source of the eleventh transistor 2109 is connected to a high level. The drain of the twelfth transistor 2110 is connected to the drain of the second transistor 2102 and the drain of the tenth transistor 2108, and the source of the twelfth transistor 2110 is connected to a high level. The gates of both the eleventh transistor 2109 and the twelfth transistor 2110 are connected to a bias voltage source to input a bias voltage, which helps to ensure and improve the stability of the first common-mode input sub-circuit 210. The high level of the sources of both the eleventh transistor 2109 and the twelfth transistor 2110 facilitates the provision of a stable power supply environment for the eleventh transistor 2109 and the twelfth transistor 2110, which can enhance the anti-interference capability of the first common-mode input sub-circuit 210. The eleventh transistor 2109 can be a PMOS, and the twelfth transistor 2110 can also be a PMOS.

[0044] In some embodiments, the first common-mode input sub-circuit 210 may include a thirteenth transistor 2111 and a fourteenth transistor 2112. The source of the thirteenth transistor 2111 is connected to the drain of the eleventh transistor 2109, and the drain of the thirteenth transistor 2111 is connected to the load sub-circuit 230. The source of the fourteenth transistor 2112 is connected to the drain of the twelfth transistor 2110, and the drain of the fourteenth transistor 2112 is connected to the load sub-circuit 230. The gates of both the thirteenth transistor 2111 and the fourteenth transistor 2112 are connected to a bias voltage source to input a bias voltage. By connecting the source of the thirteenth transistor 2111 to the drain of the eleventh transistor 2109 and connecting its drain to the load sub-circuit 230, efficient signal transmission can be achieved, while enhancing the driving capability of the circuit. Correspondingly, the source of the fourteenth transistor 2112 is connected to the drain of the twelfth transistor 2110, and its drain is also connected to the load sub-circuit 230, which helps to balance the current distribution in the circuit and improve overall stability. The gates of both the thirteenth transistor 2111 and the fourteenth transistor 2112 are connected to a bias voltage source to ensure precise control of their operating points, thereby improving the circuit's anti-interference capability and response speed. The thirteenth transistor 2111 and the fourteenth transistor 2112 can both be PMOS.

[0045] In some embodiments, the second common-mode input sub-circuit 220 may include a nineteenth transistor 2207 and a twentieth transistor 2208. The drain of the nineteenth transistor 2207 is connected to the drain of the third transistor 2201, and the source of the nineteenth transistor 2207 is grounded. The drain of the twentieth transistor 2208 is connected to the drain of the fourth transistor 2202, and the source of the twentieth transistor 2208 is grounded. The gates of both the nineteenth transistor 2207 and the twentieth transistor 2208 are connected to the second current adjustment sub-circuit 250. The nineteenth transistor 2207 and the twentieth transistor 2208 can operate at common-mode voltage. By connecting the drain of the nineteenth transistor 2207 to the drain of the third transistor 2201 and grounding the source of the nineteenth transistor 2207, precise control of the common-mode signal can be achieved. The drain of the twentieth transistor 2208 is connected to the drain of the fourth transistor 2202, and the source of the twentieth transistor 2208 is grounded, which enhances the anti-interference capability of the second common-mode input sub-circuit 220.

[0046] Figure 6The first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220 shown are combined to form an NMOS and PMOS input equalization circuit 200, realizing the combination of a folded NMOS input equalization circuit and a PMOS input equalization circuit. When the input common-mode ratio is high, the first transistor 2101 and the second transistor 2102 mainly provide the gain; when the input common-mode ratio is low, the third transistor 2201 and the fourth transistor 2202 mainly provide the gain, so that the equalization circuit 200 can support a common-mode input range of 0~VDD.

[0047] When the input common-mode voltage changes, the current flowing through the first transistor 2101 and the second transistor 2102 may decrease or even turn off, while the ninth transistor 2107 and the tenth transistor 2108, acting as current bias transistors, will not turn off. For example, when the input common-mode voltage is at an intermediate level, the first transistor 2101 and the second transistor 2102 operate normally, and the current flowing through the ninth transistor 2107 and the tenth transistor 2108 flows to the first transistor 2101 and the second transistor 2102. At this time, the current flowing to the load sub-circuit 230 is provided by the eleventh transistor 2109 and the twelfth transistor 2110. When the input common-mode voltage is low, the current flowing through the first transistor 2101 and the second transistor 2102 decreases or even turns off. At this time, the current flowing through the ninth transistor 2107 and the tenth transistor 2108 flows to the signal output terminal VON / VOP, causing the output common-mode voltage to become high, thereby affecting the subsequent circuits.

[0048] Furthermore, changes in the input common-mode voltage may reduce the current flowing through the third transistor 2201 and the fourth transistor 2202, or even cause them to turn off, while the nineteenth transistor 2207 and the twentieth transistor 2208, acting as current bias transistors, will not turn off. For example, when the input common-mode voltage is at an intermediate level, the third transistor 2201 and the fourth transistor 2202 operate normally, and the nineteenth transistor 2207 and the twentieth transistor 2208 draw current from the third transistor 2201 and the fourth transistor 2202. The current flowing to the load sub-circuit 230 is provided by the eleventh transistor 2109 and the twelfth transistor 2110. When the input common-mode voltage is high, the nineteenth transistor 2207 and the twentieth transistor 2208 draw current from the signal output terminal VON / VOP, thereby reducing the output common-mode voltage and affecting subsequent circuits.

[0049] The first current adjustment sub-circuit 240 can dynamically adjust the currents of the ninth transistor 2107 and the tenth transistor 2108 based on the detection of common-mode voltage changes at the sources of the first transistor 2101 and the second transistor 2102, so that the currents on the ninth transistor 2107 and the tenth transistor 2108 are consistent with the currents on the fifteenth transistor 2105 and the sixteenth transistor 2106. The second current adjustment sub-circuit 250 can dynamically adjust the nineteenth transistor 2207 and the twentieth transistor 2208 based on the detection of common-mode voltages at the sources of the third transistor 2201 and the fourth transistor 2202, so that the currents on the nineteenth transistor 2207 and the twentieth transistor 2208 are consistent with the currents on the seventeenth transistor 2205 and the eighteenth transistor 2206. Based on the dynamic adjustment of the first current adjustment sub-circuit 240 and the second current adjustment sub-circuit 250, when the input common mode changes, no current will flow from the ninth transistor 2107 and the tenth transistor 2108 to the signal output terminal VON / VOP, and the nineteenth transistor 2207 and the twentieth transistor 2208 will not draw current from the signal output terminal VON / VOP. This makes the common mode voltage at the signal output terminal determined only by the current of the eleventh transistor 2109 and the twelfth transistor 2110 and the load sub-circuit 230, which helps to maintain stability.

[0050] Figure 7 This is a structural diagram of another equalization circuit according to some embodiments. Figure 7 As shown, in some embodiments, the load sub-circuit 230 includes a third resistor 231, a fourth resistor 232, a fifth capacitor 233, and a sixth capacitor 234. One end of the third resistor 231 is connected to the output terminals of the first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220, and the other end of the third resistor 231 is grounded. One end of the fifth capacitor 233 is connected to the output terminals of the first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220, and the other end of the fifth capacitor 233 is grounded. The third resistor 231 and the fifth capacitor 233 are connected in parallel. One end of the fourth resistor 232 is connected to the output terminals of the first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220, and the other end of the fourth resistor 232 is grounded. One end of the sixth capacitor 234 is connected to the output terminals of the first common-mode input sub-circuit 210 and the second common-mode input sub-circuit 220, and the other end of the sixth capacitor 234 is grounded. The fourth resistor 232 and the sixth capacitor 234 are connected in parallel.

[0051] In some embodiments, one end of the third resistor 231 is connected to the drain of the thirteenth transistor 2111 and the drain of the third transistor 2201, one end of the fifth capacitor 233 is connected to the drain of the thirteenth transistor 2111 and the drain of the third transistor 2201, one end of the fourth resistor 232 is connected to the drain of the fourteenth transistor 2112 and the drain of the fourth transistor 2202, and one end of the sixth capacitor 234 is connected to the drain of the fourteenth transistor 2112 and the drain of the fourth transistor 2202.

[0052] Figure 8 for Figure 7 Local structures in Figure 1 .like Figure 8 As shown, in some embodiments, the first current adjustment sub-circuit 240 includes a first operational amplifier 241, a fifth transistor 242, a sixth transistor 243, and a first capacitor 244. The inverting input of the first operational amplifier 241 is connected to the sources of the first transistor 2101 and the second transistor 2102. The non-inverting input of the first operational amplifier 241 is connected to the drains of the fifth transistor 242 and the sixth transistor 243. The output of the first operational amplifier 241 is connected to one end of the first capacitor 244 and the gate of the fifth transistor 242. The other end of the first capacitor 244 is connected to the drains of the fifth transistor 242 and the sixth transistor 243. The source of the fifth transistor 242 is connected to a high level, and the source of the sixth transistor 243 is grounded. The gate of the sixth transistor 243 is connected to a bias voltage source to receive a bias voltage.

[0053] The first operational amplifier 241 receives source signals from the first transistor 2101 and the second transistor 2102 through its inverting input. Simultaneously, the non-inverting input of the first operational amplifier 241 is connected to the drains of the fifth transistor 242 and the sixth transistor 243, forming a feedback loop. A bias voltage source provides a stable gate voltage to the sixth transistor 243, ensuring that the sixth transistor 243 operates in the saturation region. The first capacitor 244 plays a filtering and stabilizing role in the first current regulating sub-circuit 240, reducing the impact of high-frequency noise on the output of the first operational amplifier 241.

[0054] When the common-mode voltage input to the first transistor 2101 and the second transistor 2102 decreases, the common-mode voltage at the sources of the first transistor 2101 and the second transistor 2102 also decreases. This means the voltage at the inverting input of the first operational amplifier 241 decreases, consequently increasing the output voltage of the first operational amplifier 241 and the gate voltage of the fifth transistor 242. This results in a decrease in the current flowing through the fifth transistor 242 and a decrease in the drain voltage of the fifth transistor 242. Due to the virtual short characteristic of the first operational amplifier 241, the voltages at its non-inverting input and inverting input will remain consistent. At this time, the drain voltage of the sixth transistor 243 is the same as the drain voltage of the fifteenth transistor 2105 and the sixteenth transistor 106. The gate of the sixth transistor 243 is connected to the same bias voltage as the gates of the fifteenth transistor 2105 and the sixteenth transistor 106. The sources of the sixth transistor 243, the fifteenth transistor 2105 and the sixteenth transistor 106 are grounded. Therefore, the currents on the sixth transistor 243, the fifteenth transistor 2105 and the sixteenth transistor 106 are the same. Since the sixth transistor 243 and the fifth transistor 242 are in the same current path, the current on the fifth transistor 242 is also consistent with the current on the sixth transistor 243. Since the fifth transistor 242 has the same gate bias voltage as the ninth transistor 2107 and the tenth transistor 2108, the currents on the fifth transistor 242, the ninth transistor 2107 and the tenth transistor 2108 are also consistent. Therefore, the first current adjustment sub-circuit 240 achieves the consistency of the currents on the ninth transistor 2107 and the tenth transistor 2108 with the currents on the fifteenth transistor 2105 and the sixteenth transistor 2106.

[0055] In some embodiments, the first common-mode input sub-circuit 210 may include a fifth resistor 2113 and a sixth resistor 2114. One end of the fifth resistor 2113 is connected to the source of the first transistor 2101, and the other end is connected to the inverting input of the first operational amplifier 241. One end of the sixth resistor 2114 is connected to the inverting input of the first operational amplifier 241, and the other end is connected to the source of the second transistor 2102. The resistance values ​​of the fifth resistor 2113 and the sixth resistor 2114 are the same, making it difficult for differential-mode signals across the fifth resistor 2113 and the sixth resistor 2114 to propagate between the fifth resistor 2113 and the sixth resistor 2114, thus facilitating the first operational amplifier 241 to obtain a stable common-mode voltage. The resistance values ​​of the fifth resistor 2113 and the sixth resistor 2114 may be 100KΩ.

[0056] Figure 9 for Figure 7 Local structures in Figure 2 .like Figure 9As shown, in some embodiments, the second current adjustment sub-circuit 250 includes a second operational amplifier 251, a seventh transistor 252, an eighth transistor 253, and a second capacitor 254. The inverting input of the second operational amplifier 251 is connected to the source of the third transistor 2201 and the source of the fourth transistor 2202. The non-inverting input of the second operational amplifier 251 is connected to the drain of the seventh transistor 252 and the drain of the eighth transistor 253. The output of the second operational amplifier 251 is connected to one end of the second capacitor 254 and the gate of the eighth transistor 253. The source of the eighth transistor 253 is grounded. The source of the seventh transistor 252 is connected to a high level, and the gate of the seventh transistor 252 is connected to a bias voltage source to input a bias voltage. The output of the second operational amplifier 251 is connected to the gate of the nineteenth transistor 2207 and the gate of the twentieth transistor 2208.

[0057] The second operational amplifier 251 receives source signals from the third transistor 2201 and the fourth transistor 2202 through its inverting input. Simultaneously, its non-inverting input is connected to the drains of the seventh transistor 252 and the eighth transistor 253, forming a feedback loop. A bias voltage source provides a stable gate voltage to the seventh transistor 252, ensuring it operates in the saturation region. The second capacitor 254 acts as a filter and stabilizer in the second current regulation circuit 250, reducing the impact of high-frequency noise on the output of the second operational amplifier 251.

[0058] When the common-mode voltage input to the third transistor 2201 and the fourth transistor 2202 increases, the common-mode voltage at the sources of the third transistor 2201 and the fourth transistor 2202 also increases. This means the voltage at the inverting input of the second operational amplifier 251 increases, consequently the output voltage of the second operational amplifier 251 decreases, and the gate voltage of the seventh transistor 252 decreases. This results in a larger current flowing through the seventh transistor 252 and a higher drain voltage. Due to the virtual short characteristic of the second operational amplifier 251, the voltages at its non-inverting input and inverting input will remain consistent. At this point, the drain voltage of the eighth transistor 253 is the same as that of the nineteenth transistor 2207 and the twentieth transistor 2208. The gate of the eighth transistor 253 shares the same bias voltage as the gates of the nineteenth and twentieth transistors 2207 and 2208. Since the source and base of the eighth, nineteenth, and twentieth transistors 2207 and 2208 are the same, the currents on these transistors are also the same. Because the seventh transistor 252 and the eighth transistor 253 share the same current path, the current on the seventh transistor 252 is also the same as that on the eighth transistor 253. Furthermore, because the gate bias voltages of the seventh transistor 252, seventeenth, and eighteenth transistors 2205 and 2206 are the same, the currents on the seventh, seventeenth, and eighteenth transistors 2206 are also the same. Therefore, the second current regulating sub-circuit 250 is used to make the current on the nineteenth transistor 2207 and the twentieth transistor 2208 the same as the current on the seventeenth transistor 2205 and the eighteenth transistor 2206.

[0059] In some embodiments, the second common-mode input sub-circuit 220 may include a seventh resistor 2209 and an eighth resistor 2210. One end of the seventh resistor 2209 is connected to the source of the third transistor 2201, and the other end is connected to the inverting input of the second operational amplifier 251. One end of the eighth resistor 2210 is connected to the inverting input of the second operational amplifier 251, and the other end is connected to the source of the fourth transistor 2202. The resistance values ​​of the seventh resistor 2209 and the eighth resistor 2210 are the same, making it difficult for differential-mode signals across the seventh resistor 2209 and the eighth resistor 2210 to propagate between the seventh resistor 2209 and the eighth resistor 2210, thus facilitating the second operational amplifier 251 to obtain a stable common-mode voltage. The resistance values ​​of the seventh resistor 2209 and the eighth resistor 2210 can be 100KΩ.

[0060] Figure 10 A partial structure of another equalization circuit according to some embodiments Figure 1 .like Figure 10As shown, in some embodiments, the first current regulating sub-circuit 240 further includes a seventh capacitor 245. One end of the seventh capacitor 245 is connected to the inverting input of the first operational amplifier 241, and the other end of the seventh capacitor 245 is grounded. The seventh capacitor 245 acts as a ground capacitor, which can filter and make the common-mode voltage of the first transistor 2101 and the second transistor 2102 more stable.

[0061] Figure 11 A partial structure of another equalization circuit according to some embodiments Figure 2 .like Figure 11 As shown, in some embodiments, the second current regulation sub-circuit 250 further includes an eighth capacitor 255. One end of the eighth capacitor 255 is connected to the inverting input of the second operational amplifier 251, and the other end of the eighth capacitor 255 is grounded. The eighth capacitor 255 acts as a capacitor to ground, which can filter and make the common-mode voltage of the third transistor 2201 and the fourth transistor 2202 more stable.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An equalization circuit, characterized in that, include: The first common-mode input sub-circuit includes a first transistor and a second transistor; the gates of the first transistor and the second transistor are respectively used for input signals. The second common-mode input sub-circuit includes a third transistor and a fourth transistor; the gates of the third transistor and the fourth transistor are respectively used for input signals; The load sub-circuit has one end connected to the source of the first transistor, the second transistor, the third transistor, and the fourth transistor, and the other end grounded. The first current regulation sub-circuit includes a first operational amplifier, a fifth transistor, a sixth transistor, and a first capacitor; wherein, the inverting input terminal of the first operational amplifier is connected to the source of the first transistor and the second transistor, the non-inverting input terminal of the first operational amplifier is connected to the drain of the fifth transistor and the sixth transistor, the output terminal of the first operational amplifier is connected to one end of the first capacitor and the gate of the fifth transistor, the other end of the first capacitor is connected to the drain of the fifth transistor and the drain of the sixth transistor, and the source of the sixth transistor is grounded; The second current regulation sub-circuit includes a second operational amplifier, a seventh transistor, an eighth transistor, and a second capacitor; wherein, the inverting input terminal of the second operational amplifier is connected to the sources of the third and fourth transistors, the non-inverting input terminal of the second operational amplifier is connected to the drains of the seventh and eighth transistors, the output terminal of the second operational amplifier is connected to one end of the second capacitor and the gate of the eighth transistor, the other end of the second capacitor is connected to the drains of the seventh and eighth transistors, and the source of the eighth transistor is grounded.

2. The equalization circuit according to claim 1, characterized in that, The first common-mode input sub-circuit further includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; The gates of the ninth transistor and the tenth transistor are connected to the gate of the fifth transistor; the drains of the ninth transistor and the eleventh transistor are both connected to the drain of the first transistor; the drains of the tenth transistor and the twelfth transistor are both connected to the drain of the second transistor; the gates of the eleventh transistor and the twelfth transistor are used to input bias voltage. The source of the thirteenth transistor is connected to the drain of the eleventh transistor, the source of the fourteenth transistor is connected to the drain of the twelfth transistor, the gate of the thirteenth transistor is connected to the gate of the fourteenth transistor, and the drains of the thirteenth transistor and the fourteenth transistor are connected to the load sub-circuit.

3. The equalization circuit according to claim 1 or 2, characterized in that, The first common-mode input sub-circuit also includes a third capacitor, a first resistor, a fifteenth transistor, and a sixteenth transistor; One end of the third capacitor is connected to the gate of the first transistor, and the other end of the third capacitor is connected to the gate of the second transistor; one end of the first resistor is connected to the gate of the first transistor, and the other end of the first resistor is connected to the gate of the second transistor. The drain of the fifteenth transistor is connected to the source of the first transistor, the drain of the sixteenth transistor is connected to the source of the second transistor, the sources of the fifteenth transistor and the sixteenth transistor are grounded, and the gates of the fifteenth transistor and the sixteenth transistor are used to input bias voltage.

4. The equalization circuit according to claim 1, characterized in that, The second common-mode input sub-circuit also includes a seventeenth transistor, an eighteenth transistor, a fourth capacitor, and a second resistor; The drain of the seventeenth transistor, one end of the fourth capacitor, and one end of the second resistor are all connected to the source of the third transistor. The drain of the eighteenth transistor, the other end of the fourth capacitor, and the other end of the second resistor are all connected to the source of the fourth transistor. The gates of the seventeenth transistor and the eighteenth transistor are used to input bias voltage.

5. The equalization circuit according to claim 1 or 4, characterized in that, The second common-mode input sub-circuit also includes a nineteenth transistor and a twentieth transistor; The drain of the nineteenth transistor is connected to the drain of the third transistor, the drain of the twentieth transistor is connected to the drain of the fourth transistor, the source of the nineteenth transistor and the source of the twentieth transistor are respectively grounded, and the gate of the nineteenth transistor and the gate of the twentieth transistor are respectively connected to the output terminal of the second operational amplifier.

6. The equalization circuit according to claim 1, characterized in that, The load sub-circuit includes a third resistor, a fourth resistor, a fifth capacitor, and a sixth capacitor; one end of the third resistor is connected to the drain of the first transistor and the third transistor, one end of the fourth resistor is connected to the drain of the second transistor and the fourth transistor, and the other ends of the third resistor and the fourth resistor are both grounded; one end of the fifth capacitor is connected to one end of the third resistor, one end of the sixth capacitor is connected to one end of the fourth resistor, and the other ends of the fifth capacitor and the sixth capacitor are both grounded.

7. The equalization circuit according to claim 1, characterized in that, The first common-mode input sub-circuit further includes a fifth resistor and a sixth resistor; one end of the fifth resistor is connected to the source of the first transistor, the other end of the fifth resistor and one end of the sixth resistor are respectively connected to the inverting input of the first operational amplifier, and the other end of the sixth resistor is connected to the source of the second transistor.

8. The equalization circuit according to claim 1, characterized in that, The second common-mode input sub-circuit further includes a seventh resistor and an eighth resistor; one end of the seventh resistor is connected to the source of the third transistor, the other end of the seventh resistor and one end of the eighth resistor are connected to the inverting input of the second operational amplifier, and the other end of the eighth resistor is connected to the source of the fourth transistor.

9. The equalization circuit according to claim 1, characterized in that, The first current adjustment sub-circuit also includes a seventh capacitor, one end of which is connected to the inverting input terminal of the first operational amplifier, and the other end of which is grounded. The second current adjustment sub-circuit also includes an eighth capacitor, one end of which is connected to the inverting input terminal of the operational amplifier, and the other end of which is grounded.

10. A receiver, characterized in that, The receiver includes an equalization circuit located at its signal input terminal for equalizing the input signal; wherein the equalization circuit is the equalization circuit described in any one of claims 1-9.

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