An ultrasonic receiving circuit and an ultrasonic imaging device

Abstract

The utility model provides a kind of ultrasonic receiving circuit and ultrasonic imaging equipment, belong to industrial ultrasonic imaging technical field, including switching circuit, sampling circuit, communication circuit, logic control unit being electrically connected in turn, and multistage power supply circuit;Multistage power supply circuit, configured to be powered on signal output in response to logic control unit, switching circuit, sampling circuit and communication circuit are powered respectively;Switching circuit, configured to be level signal output in response to logic control unit, signal loop between ultrasonic signal source and sampling circuit is turned on;Sampling circuit, configured to sample ultrasonic signal transmitted in signal loop;Communication circuit, configured to be powered on signal, after sampling data is transmitted to logic control unit and is handled.Response.

Description

Technical Field

[0001] This utility model belongs to the field of industrial ultrasonic imaging technology, specifically relating to an ultrasonic receiving circuit and an ultrasonic imaging device. Background Technology

[0002] In traditional ultrasound receiver circuits, conventional ultrasound and phased array ultrasound require two independent receiving links. Switching modes necessitates re-initializing the FPGA (Field-Programmable Gate Array) configuration, leading to switching delays. Furthermore, each part of the circuit in a traditional ultrasound receiver requires independent power supply, making power supply coordination difficult and resulting in significant power supply ripple, which negatively impacts image quality. Summary of the Invention

[0003] In view of the above problems, this application provides an ultrasonic receiving circuit and an ultrasonic imaging device to overcome or at least partially solve the above problems.

[0004] In a first aspect, this application provides an ultrasonic receiving circuit, including a switching circuit, a sampling circuit, a communication circuit, and a logic control unit that are connected in sequence, and a multi-stage power supply circuit that is electrically connected to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit respectively. The multi-stage power supply circuit is configured to supply power to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the logic control unit respectively in response to a power-on signal; The switching circuit is configured to, in response to the level signal output by the logic control unit, connect the signal loop between the ultrasonic signal source and the sampling circuit; wherein, the ultrasonic signal source includes: a conventional ultrasonic signal source and a phased array ultrasonic signal source; The sampling circuit is configured to sample the ultrasonic signal transmitted in the signal loop; The communication circuit is configured to transmit the sampled data to the logic control unit for processing in response to the ultrasonic signal.

[0005] Furthermore, the switching circuit includes: An analog switch includes input terminals, output terminals, and control terminals; among which, The input terminal is electrically connected to the conventional ultrasonic signal source and the phased array ultrasonic signal source, respectively. The control terminal is electrically connected to the logic control unit; The output terminal is electrically connected to the sampling circuit and is configured to, in response to the level signal, connect the sampling circuit between the sampling circuit and the conventional ultrasonic signal source or the phased array ultrasonic signal source corresponding to the level signal.

[0006] Furthermore, the analog switch also includes a first power supply terminal and a second power supply terminal; The switching circuit further includes a bipolar power supply unit, which is electrically connected to the first power supply terminal and the second power supply terminal respectively, and is configured to provide a positive voltage to the first power supply terminal and a negative voltage to the second power supply terminal.

[0007] Furthermore, the sampling circuit includes: An amplification and filtering circuit, electrically connected to the output of the switching circuit, is configured to amplify and filter the ultrasonic signal output from the output of the switching circuit, and to output the processed ultrasonic signal to the communication circuit.

[0008] Furthermore, the communication circuit includes: A high-speed serial interface, electrically connected to the logic control unit, is configured to transmit the processed ultrasonic signal to the logic control unit in the form of a differential signal; The clock signal unit, electrically connected to the logic control unit, is configured to perform phase alignment processing on the signals transmitted through the high-speed serial interface.

[0009] Furthermore, the communication circuit also includes: The common-mode unit, electrically connected to the transmitter of the high-speed serial interface and the logic control unit, is configured to reduce common-mode noise on the transmission line where the differential signal is located.

[0010] Furthermore, the multi-stage power supply circuit includes: a primary power supply circuit, and multiple secondary power supply circuits electrically connected to the output terminal of the primary power supply circuit; wherein, The primary power supply circuit is electrically connected to the switching circuit, the sampling circuit, and the communication circuit, respectively, and is configured to output a first voltage to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the plurality of secondary power supply circuits in response to the power-on signal; The secondary power supply circuit is electrically connected to the switching circuit, the sampling circuit, and the communication circuit, respectively, and is configured to reduce the first voltage to a second voltage in response to the first voltage and output it to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit.

[0011] Furthermore, the primary power supply circuit includes: a power supply, a synchronous step-down unit, and a first filter unit; The synchronous buck unit is configured to, in response to the power-on signal, reduce the supply voltage output by the power supply to the first voltage and output it to the first filter unit. The first filtering unit is configured to, upon receiving the first voltage, filter out high-frequency noise in the first voltage and then output the first voltage to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the plurality of secondary power supply circuits.

[0012] Furthermore, the secondary power supply circuit includes: a voltage regulator unit and a second filter unit; The voltage regulator unit is configured to reduce the first voltage and stabilize it at the second voltage when it receives the first voltage, and then output it to the second filter unit. The second filtering unit is configured to, upon receiving the second voltage, filter out high-frequency noise in the second voltage and then output the second voltage to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit.

[0013] A second aspect of this application provides an ultrasonic imaging device, including the ultrasonic receiving circuit described in the first aspect of this application.

[0014] The ultrasonic receiving circuit provided by the embodiments of this application includes a switching circuit, a sampling circuit, a communication circuit, and a logic control unit that are connected in sequence, as well as a multi-stage power supply circuit that is electrically connected to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit respectively. Firstly, through a multi-stage power supply circuit, it is configured to respond to the power-on signal output by the logic control unit and supply power to the switching circuit, sampling circuit, and communication circuit respectively. Through the multi-stage power supply circuit, the switching circuit, sampling circuit, and communication circuit can be powered on at different times or with different voltages according to the instructions of the logic control unit, avoiding the ineffective power consumption caused by the traditional unified power supply and meeting different voltage requirements.

[0015] Then the switching circuit is configured to respond to the level signal output by the logic control unit and conduct the signal loop between the ultrasonic signal source and the sampling circuit. Since the ultrasonic signal source includes a conventional ultrasonic signal source and a phased array ultrasonic signal source, the receiving circuit of the sampling circuit and the communication circuit can be shared by the signal loops of the conventional ultrasonic source and the phased array ultrasonic signal source, which can avoid the problem of re-initializing the configuration of the logic control unit during switching and the excessive delay time.

[0016] In addition, the sampling circuit is configured to sample the ultrasonic signal transmitted in the signal loop. Therefore, the sampling circuit can start sampling immediately after the signal loop is turned on. The low ripple power supply provided by the multi-stage power supply circuit reduces noise. The communication circuit is configured to respond to the ultrasonic signal and transmit the sampled data to the logic control unit for processing. The sampled data can be transmitted to the logic control unit for further processing to make the switching circuit, sampling circuit, communication circuit and logic control unit a complete closed loop. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a system schematic diagram of an ultrasonic receiving circuit provided in an embodiment of this application; Figure 2 This application's embodiments are aimed at Figure 1 A detailed schematic diagram of the provided ultrasonic receiving circuit; Figure 3 This is a schematic diagram of a switching circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the circuit structure of a bipolar power supply unit provided in an embodiment of this application; Figure 5 This is a schematic diagram of a sampling circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a communication circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the circuit structure of a clock signal unit provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of the primary power supply circuit provided in the embodiment of this application; Figure 9 This is a schematic diagram of the structure of multiple secondary power supply circuits provided in the embodiments of this application.

[0018] Figure label: 1-Analog switch, 2-First power supply terminal, 3-Second power supply terminal, 4-Input impedance matching and filtering circuit, 5-High-speed serial interface, 6-Common mode unit, 7-Power supply, 8-Synchronous step-down unit, 9-First filtering unit, 10-Voltage regulation unit, 11-Second filtering unit. Detailed Implementation

[0019] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] Since the ultrasonic receiving equipment required in this embodiment typically needs to accommodate both conventional ultrasonic signals and phased array ultrasonic signals, the conventional ultrasonic channels generally do not exceed four, while the phased array ultrasonic channels range from 32 to 256. Furthermore, conventional and phased array functions are not used simultaneously. If the internal receiving circuit can be compatible with both functions, compared to having separate receiving channels, it solves the problem of needing two independent receiving links for conventional and phased array ultrasound, requiring FPGA re-initialization during switching, which results in a delay exceeding 500μs.

[0021] Therefore, the ultrasonic receiving circuit provided in this embodiment, through the electrical connection between the switching circuit, sampling circuit, communication circuit, logic control unit and multi-stage power supply circuit, the switching circuit responds to the level signal output by the logic control unit and conducts the signal loop between the ultrasonic signal source corresponding to the level signal and the sampling circuit. The sampling circuit and communication circuit are shared throughout the process, which can reduce the time delay caused by switching different signal loops, and there is no need to overload the logic control unit.

[0022] Secondly, the multi-level power supply circuit can also provide independent power to the switching circuit, sampling circuit, communication circuit, and logic control unit, which not only improves the signal-to-noise ratio, but also eliminates the need for power supply coordination design and greatly simplifies the complexity of the hardware.

[0023] The ultrasonic receiving circuit provided in this embodiment will be described in detail below: Reference Figure 1 , Figure 1 This is a system schematic diagram of an ultrasonic receiving circuit provided in an embodiment of this application. Figure 1 As can be seen from the diagram, the ultrasonic receiving circuit includes a switching circuit, a sampling circuit, a communication circuit, and a logic control unit that are connected in sequence, as well as a multi-stage power supply circuit that is electrically connected to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit respectively.

[0024] The switching circuit, the sampling circuit, the communication circuit, and the logic control unit are each configured with the following functions: The multi-stage power supply circuit is configured to supply power to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the logic control unit respectively in response to a power-on signal; the switching circuit is configured to conduct the signal loop between the ultrasonic signal source and the sampling circuit in response to a level signal output by the logic control unit; wherein, the ultrasonic signal source includes: a conventional ultrasonic signal source and a phased array ultrasonic signal source; the sampling circuit is configured to sample the ultrasonic signal transmitted in the signal loop; the communication circuit is configured to transmit the sampled data to the logic control unit for processing in response to the ultrasonic signal.

[0025] In this embodiment, the multi-level power supply circuit can be a distributed power supply architecture to achieve power supply at different levels. Specifically, different levels of power supply refer to providing power at different voltages. When the system or device containing the multi-level power supply circuit is powered on, the multi-level power supply circuit responds to the power-on signal and outputs power to the electronic devices or circuits electrically connected to it. The switching circuit can be a dynamic switching architecture, specifically composed of a U23 chip (NXP PN5180 high-integration NFC front-end chip) + four-channel analog switches. It can dynamically switch the conduction channels via digital control signals (such as GPIO (General-Purpose Input / Output) / SPI (Serial Peripheral Interface)) without mechanical action, achieving nanosecond-level path reconstruction. The sampling circuit can be a circuit that converts the dynamically switched and selected ultrasonic signal into a digital code stream in real time, with low noise and high precision. The communication circuit can be a circuit that transmits the high-speed digital code stream output by the sampling circuit to the logic control unit in real time, with low bit error rate, and synchronously via a differential link, realizing high-speed bidirectional interaction between ultrasonic data and system control signals.

[0026] Therefore, by connecting the switching circuit, sampling circuit, communication circuit, logic control unit, and multi-stage power supply circuit, a switching mechanism can be constructed using the level signal output by the logic control unit to switch between a conventional ultrasonic signal source and a phased array ultrasonic signal source. The level signal can be set according to the different ultrasonic signal sources. Assuming a high-level signal corresponds to a conventional ultrasonic signal source and a low-level signal corresponds to a phased array ultrasonic signal source, when the logic control unit outputs a high-level signal, the switching circuit will connect the signal loop between the conventional ultrasonic signal source and the sampling circuit. The sampling circuit can then collect the ultrasonic signal from this loop and transmit it to the communication circuit. The communication circuit then transmits the ultrasonic signal to the logic control unit via a differential signal, and the logic control unit performs the next action based on the received ultrasonic signal. Similarly, when the logic control unit outputs a low-level signal, the switching circuit will connect the signal loop between the conventional ultrasonic signal source and the sampling circuit. The actions of the sampling circuit, communication circuit, and logic control unit can be referenced in the explanation of the conventional ultrasonic signal source, and will not be repeated here.

[0027] In summary, the ultrasonic receiving circuit provided in this embodiment, through the electrical connection between the switching circuit, sampling circuit, communication circuit, logic control unit, and multi-stage power supply circuit, allows the switching circuit to respond to the level signal output by the logic control unit and conduct the signal loop between the ultrasonic signal source and the sampling circuit corresponding to the level signal. This enables the switching of the signal loop between the conventional ultrasonic source and the sampling circuit, as well as the signal loop between the conventional ultrasonic source and the sampling circuit. Furthermore, by sharing the receiving circuit of the sampling circuit and the communication circuit with the signal loops of the conventional ultrasonic source and the phased array ultrasonic signal source, the re-initialization of the logic control unit configuration during switching can be avoided, thus preventing excessive delay time.

[0028] Secondly, the multi-stage power supply circuit of this application can also provide low ripple power, further reducing the signal-to-noise ratio of the sampling circuit and communication circuit when receiving signals. Furthermore, through the multi-stage power supply circuit, different voltage sources can be provided to the switching circuit, sampling circuit, communication circuit and logic control unit separately, eliminating the need for power supply coordination design for the switching circuit, sampling circuit, communication circuit and logic control unit, thus reducing the complexity of the entire ultrasonic receiving circuit.

[0029] In one specific embodiment, the switching circuit includes: an analog switch, comprising an input terminal, an output terminal, and a control terminal; wherein the input terminal is electrically connected to the conventional ultrasonic signal source and the phased array ultrasonic signal source respectively; the control terminal is electrically connected to the logic control unit; and the output terminal is electrically connected to the sampling circuit and configured to, in response to the level signal, conduct the sampling loop between the sampling circuit and the conventional ultrasonic signal source or the phased array ultrasonic signal source corresponding to the level signal.

[0030] In this embodiment, refer to Figure 2 , Figure 2 This application's embodiments are aimed at Figure 1 A detailed schematic diagram of the provided ultrasonic receiving circuit system. Figure 2 The switching circuit includes analog switches. Figure 3 This is a schematic diagram of a switching circuit provided in an embodiment of this application. Figure 3 As can be seen from the diagram, the analog switch is UP3, and the switching circuit includes the analog switch. The analog switch includes input terminals, control terminals, and output terminals. The control terminals can be IN1-IN4, and the input terminals can be pins D1-D4. Figure 2In this diagram, UT_PA_SW represents the level signal output by the logic control unit. It is assumed that a high-level signal selects the conventional ultrasonic signal, and a low-level signal selects the phased array ultrasonic signal. The input terminals of the analog switches are electrically connected to both the conventional and phased array ultrasonic signal sources, respectively; the control terminals of the analog switches are electrically connected to the logic control unit. When the logic control unit outputs a high-level signal, the sampling circuit between the sampling circuit and the conventional ultrasonic signal source is activated, and D1~D4 connect to the four conventional ultrasonic signals from V_SMA_CLAMP_R1~V_SMA_CLAMP_R4. When the logic control unit outputs a low-level signal, the sampling circuit between the sampling circuit and the phased array ultrasonic signal source is activated, and D1~D4 connect to the four phased array ultrasonic signals from ALT_RX_R61~ALT_RX_R64.

[0031] In one specific embodiment, the analog switch further includes a first power supply terminal and a second power supply terminal; the switching circuit further includes a bipolar power supply unit, which is electrically connected to the first power supply terminal and the second power supply terminal respectively, and is configured to provide a positive voltage to the first power supply terminal and a negative voltage to the second power supply terminal.

[0032] In this embodiment, refer to Figure 3 The analog switch also includes a first power supply terminal 2 and a second power supply terminal 3. The first power supply terminal 2 can be VDD, and the second power supply terminal 3 can be VSS, as shown in the reference. Figure 4 , Figure 4 This is a circuit structure diagram of a bipolar power supply unit provided in an embodiment of this application. Figure 4 As can be seen from the diagram, the bipolar power supply unit is electrically connected to the first power supply terminal 2 and the second power supply terminal 3 respectively, and can provide a positive voltage to the first power supply terminal 2 and a negative voltage to the second power supply terminal 3 when the analog switch is working.

[0033] In one specific embodiment, the sampling circuit includes: an amplification and filtering circuit electrically connected to the output terminal of the switching circuit, configured to amplify and filter the ultrasonic signal output from the output terminal of the switching circuit, and output the processed ultrasonic signal to the communication circuit.

[0034] In this embodiment, the sampling circuit includes an amplification and filtering circuit, with an input impedance matching and filtering circuit 4 in its peripheral components. The amplification and filtering circuit can amplify and filter the sampled ultrasonic signal. The amplification and filtering circuit includes a variable gain amplifier and a third-order Butterworth filter. The gain of the gain amplifier can be switched between 18 dB, 21 dB, 24 dB, and 27 dB. The cutoff frequency of the third-order Butterworth filter can be 20 MHz, and the stopband rejection is >60 dB@38 MHz, which can filter out high-frequency noise. Therefore, the amplification and filtering circuit can amplify and filter the ultrasonic signal output from the switching circuit and output the processed ultrasonic signal to the communication circuit.

[0035] For example, refer to Figure 5 , Figure 5 This is a schematic diagram of a sampling circuit provided in an embodiment of this application. Figure 5 From this, we can know that Figure 5 The sampling circuit U4A uses AFE58JD48 as the AFE chip, which implements the functions of amplification and filtering circuits, and input impedance matching and filtering circuit 4 ( Figure 5 (Circled in dashed box) This serves as the peripheral circuit for the AFE chip, achieving input impedance matching and filtering. A 0.1μF C0G capacitor (ESR < 10mΩ) is coupled in series in the front stage of the AFE chip to filter out DC bias. For details, please refer to the connection of the front end of the INP61~INP64 pins. Since the front stage is coupled in series with C250~C253 capacitors (low ESR), the amplification and filtering circuit in this implementation can filter out DC bias and the coupling cutoff frequency.

[0036] Secondly, the ACT13~ACT16 pins are connected to the chip's internal variable active termination resistors. By configuring different resistance values, signal reflection is reduced and axial resolution is improved.

[0037] In addition, the U4A has a built-in PGA (Programmable Gain Amplifier) ​​and a 16-bit ADC (bit Analog-to-Digital Converter), supporting a maximum sampling rate of 125MSPS. The gain can be set between 18dB, 21dB, 24dB and 27dB. The AFE chip has a built-in third-order Butterworth filter to filter out high-frequency noise.

[0038] In one specific embodiment, the communication circuit includes: a high-speed serial interface electrically connected to the logic control unit and configured to transmit the processed ultrasonic signal to the logic control unit in the form of a differential signal; and a clock signal unit electrically connected to the logic control unit and configured to perform phase alignment processing on the signal transmitted by the high-speed serial interface.

[0039] In this embodiment, the communication circuit includes a high-speed serial interface 5, which is electrically connected to the logic control unit. The high-speed serial interface 5 is configured as a JEDEC 204B standard serial interface. JEDEC 204B is a high-speed data transmission protocol used as a standard serial interface between converters (such as ADCs (Analog-to-Digital Converters) or DACs (Digital-to-Analog Converters)) and digital processing units (such as FPGAs). Standard serial interface signals are all differential signals. Therefore, the communication circuit can transmit the processed ultrasonic signal to the logic control unit in differential signal form. Transmitting in differential signal form reduces electromagnetic radiation and enhances anti-interference. To improve signal integrity, the traces within the group must be of equal length with an error not exceeding 10 mil, and the matching impedance must be 100 ohms to reduce reflection and signal distortion.

[0040] For example, refer to Figure 6 , Figure 6 This is a schematic diagram of a communication circuit provided in an embodiment of this application. From... Figure 6 As can be seen from the diagram, U4C is a communication circuit chip. The U4C chip has two built-in ADC DIEs (Analog-to-Digital Converter Dies). ADC DIEs are bare dies of integrated circuit chips used for analog-to-digital signal conversion. They transmit data to the logic control unit through the JESD204B interface. The JESD204B interface can be configured in 80X mode. The first ADC DIE corresponds to two differential data channels, D_CML1_OUTP and D_CML2_OUTP, used for high-speed communication. The second ADC DIE corresponds to two differential data channels, D_CML7_OUTP and D_CML8_OUTP, used for high-speed communication. Therefore, the JESD204B transmitter can use differential CML (Current Mode Logic) levels. The ultrasonic signal can be transmitted to the logic control unit in differential signal form through the two ADC DIEs.

[0041] In addition, the logic control unit also needs to be connected to an external clock signal unit, as shown in the reference. Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of a clock signal unit provided in an embodiment of this application. Figure 7It is known that the logic control unit can align all internal clock phases using the external D_SYSREF_SERDES1 (Device SYSREF Serializer / Deserializes, Device Reference Clock 1) or D_SYNC_SERDES 2 (Subclass 2) signals, and align the local multi-frame clocks to a specific sampling clock edge. Therefore, the clock signal unit can perform phase alignment processing on the signals transmitted through the high-speed serial interface. In addition, this embodiment also needs to emphasize that, in order to ensure the quality of signal transmission, the SYSREF (System Reference, System Reference Clock) trace length error does not exceed 5mil and is aligned with the device clock phase; the SYNC (Synchronization, Synchronization Signal) trace length error does not exceed 5mil and the synchronization establishment time is <10ms.

[0042] In one specific embodiment, the communication circuit further includes a common-mode unit electrically connected to the transmitting end of the high-speed serial interface and the logic control unit, configured to reduce common-mode noise on the transmission line where the differential signal is located.

[0043] In this embodiment, refer to Figure 6 The communication circuit also includes a common-mode unit 6, which consists of AC coupling capacitors C316 to C323 and terminating resistors R690 to R697. It is electrically connected to the transmitting end of the high-speed serial interface 5 and the logic control unit. Specifically, a 0.1μF NP0 AC coupling capacitor is connected in series at the transmitting end of the high-speed serial interface 5, and a 50-ohm terminating resistor is connected in parallel at the receiving end of the logic control unit to reduce common-mode noise on the transmission line where the differential signal is located.

[0044] In one specific embodiment, the multi-stage power supply circuit includes: a primary power supply circuit and a plurality of secondary power supply circuits electrically connected to the output terminal of the primary power supply circuit; wherein, the primary power supply circuit is electrically connected to the switching circuit, the sampling circuit, and the communication circuit respectively, and is configured to output a first voltage to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the plurality of secondary power supply circuits in response to the power-on signal; the secondary power supply circuits are electrically connected to the switching circuit, the sampling circuit, and the communication circuit respectively, and are configured to reduce the first voltage to a second voltage in response to the first voltage and output it to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit.

[0045] In this embodiment, to ensure the different power supply voltage requirements of the switching circuit, sampling circuit, communication circuit, and logic control unit, refer to Figure 2Therefore, the multi-stage power supply circuit includes a primary power supply circuit and multiple secondary power supply circuits electrically connected to the output of the primary power supply circuit. The primary power supply circuit can respond to a power-on signal, which can be the power-on signal of the primary power supply circuit. After the primary power supply circuit is powered on, it will output a first voltage to the switching circuit, sampling circuit, communication circuit, logic control unit, and multiple secondary power supply circuits. The secondary power supply circuits can respond to the first voltage and reduce the primary power supply voltage to a second voltage adapted to the switching circuit, sampling circuit, and communication circuit. Since there are multiple secondary power supply circuits, they can provide multiple second voltage values ​​to meet the power supply requirements of the switching circuit, sampling circuit, communication circuit, and logic control unit to achieve different functions.

[0046] In one specific embodiment, the primary power supply circuit includes: a power supply, a synchronous buck unit, and a first filter unit; the synchronous buck unit is configured to, in response to the power-on signal, reduce the supply voltage output by the power supply to the first voltage and output it to the first filter unit; the first filter unit is configured to, upon receiving the first voltage, filter out high-frequency noise in the first voltage and then output the first voltage to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the plurality of secondary power supply circuits.

[0047] In this embodiment, refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of the primary power supply circuit provided in the embodiments of this application. Figure 8 As can be seen, the power supply circuit includes a power supply 7, a synchronous buck unit 8, and a first filter unit 9. The power supply 7 can be an external DC adapter, providing a raw power supply voltage of 12~24V. The positive and negative terminals of the power supply can be connected to the VIN and GND pins of the synchronous buck unit 8, respectively. The synchronous buck unit 8 can reduce the raw power supply voltage to a first voltage of 5V. To reduce the influence of high-frequency noise inherent in the power supply 7, it is also possible to... Figure 8 The SYNC and INTVCC pins are shorted to form the first filter unit 9. When the first voltage is received, the first filter unit 9 can greatly reduce the EMI (Electromagnetic Interference) emission noise (high-frequency noise) of the power supply in the first voltage by modulating the spread spectrum frequency. Then, the first voltage with the high-frequency noise filtered out is output to power the switching circuit, sampling circuit, communication circuit, logic control unit and multiple secondary power supply circuits.

[0048] In addition, this embodiment provides Figure 8It consists of a U27 chip and peripheral circuitry forming a synchronous buck unit, outputting a high +5V current to power loads such as FPGA, AFE, and MUX chips; by shorting the SYNC and INTVCC pins and modulating the spread spectrum frequency, the EMI emission noise of the power supply is greatly reduced. The primary power supply circuit provided in this embodiment is an AP1501S-5.0RG synchronous buck circuit (input 12V → output 5V, ripple < 5mV@3A), with an efficiency of 95%, and is equipped with a π-type filter (100μF / 16V ceramic capacitor + 15uH alloy integral molded inductor); its conducted EMI characteristics do not exceed 40dbuV (0-30MHz), and its radiated EMI characteristics are 32dbuμV (30–200MHz).

[0049] In one specific embodiment, the secondary power supply circuit includes: a voltage regulator unit and a second filter unit; the voltage regulator unit is configured to reduce and stabilize the first voltage to the second voltage when receiving the first voltage, and output the second voltage to the second filter unit; the second filter unit is configured to filter out high-frequency noise in the second voltage when receiving the second voltage, and then output the second voltage to the switching circuit, the sampling circuit, the communication circuit and the logic control unit.

[0050] In this embodiment, refer to Figure 9 , Figure 9 This is a schematic diagram of the structure of multiple secondary power supply circuits provided in the embodiments of this application. Figure 9 As can be seen from the diagram, each secondary power supply circuit includes a voltage regulator unit 10 and a second filter unit 11. The voltage regulator unit 10 can be a low-dropout linear regulator (LDO) chip, which can reduce the first voltage to a second voltage and output it to the second filter unit 11. Figure 8 The capacitors and resistors in each secondary power supply circuit are connected in parallel between the IN pin and the GND pin in a π-type filter to form a second filter unit 11. Then, after filtering out the high-frequency noise in the second voltage, the second filter unit 11 outputs the second voltage to the switching circuit, the sampling circuit and the communication circuit.

[0051] For example, Figure 9 The image shows four secondary power supply circuits, providing secondary voltages of 1.8V, 3.3V, 1.15V, and 2V respectively.

[0052] Figure 9(a) The 1.8V digital power supply is based on the U26 high-precision ultra-low noise LDO chip, outputting a +1.8V high current to the FPGA and AFE chip load. A ferrite bead isolates the digital AVDD_1.8V and analog DVDD_1.8V to absorb interference. The analog 1.8V mainly includes the ADC reference voltage, ADC clock buffer, and power supply for the bandgap circuit; the digital 1.8V mainly includes the ADC PLL power supply, TPS7A85A-1.8 (input 5V→1.8V, typical noise 4.4μV RMS), with a load regulation of ±0.75%; the combined ground pin is 200mV+800mV; the 3.3V interface power supply is TPS7A85A-3.3 (input 5V→3.3V, typical noise 4.4μV RMS), with a load regulation of ±0.75%; the combined ground pin is 100mV+800mV+1.6V. Figure 9 (b) 3.3V core power supply: Specifically, it is based on the U24 high-precision, ultra-low-noise LDO chip, outputting a +3.3V high current to the FPGA and AFE chip loads. The AFE load mainly includes the internal VCA die power supply. The TPS7A85A-3.3 (input 5V→3.3V, typical noise 4.4μV RMS) has a load regulation of ±0.75%; the combined grounding pins are: 100mV +800mV +1.6V.

[0053] Figure 9 (c) 1.15V core power supply: Specifically, it is based on the U24 high-precision ultra-low noise LDO chip, outputting a +1.15V high current to the AFE chip load. The AFE load includes power supply for the JESD interface PLL and CML buffer, TPS7A84-1.15 (input 5V→1.15V, typical noise 4.4μV RMS), with a load regulation of 1%; the combined grounding pins are: 50mV + 100mV + 200mV.

[0054] In summary, the peak-to-peak ripple of the three secondary power supply circuits can be reduced to no more than 3mV after decoupling with a GRM155R61E475ME15D (MLCC low ESR, 4.7μF) capacitor and interference absorption with a BLM21PG121SN1D (3A, 0805, 120 ohm impedance, 30 milliohm resistance) ferrite bead.

[0055] This application also provides an ultrasonic imaging device, including the ultrasonic receiving circuit described in the first aspect of this application.

[0056] For example, the following will combine Figures 1-9 The application of the ultrasonic receiving circuit provided in this embodiment in ultrasonic imaging equipment is described below: First, the ultrasound imaging equipment is powered on. The multi-stage power supply circuit responds to the power-on signal, supplying power to the switching circuit, sampling circuit, communication circuit, and logic control unit respectively. Then, the logic control unit receives the operation from the equipment operator and outputs a level signal to the switching circuit. If the equipment operator activates the conventional ultrasound signal mode, the logic control unit outputs a high-level signal to the switching circuit to enable the switching circuit to conduct the signal loop between the conventional ultrasound signal source and the sampling circuit. If the equipment operator activates the phased array ultrasound mode, the logic control unit outputs a low-level signal to the switching circuit to enable the switching circuit to conduct the signal loop between the phased array ultrasound signal source and the sampling circuit.

[0057] Assuming the signal loop between the conventional ultrasound signal source and the sampling circuit is established, the sampling circuit will sample the ultrasound signal in the signal loop and transmit the ultrasound signal to the communication circuit. The communication circuit can then transmit the ultrasound signal in the form of a differential signal to the logic control unit for ultrasound imaging processing.

[0058] Furthermore, when the phased array ultrasound mode is required, the logic control unit can directly send a low-level signal to the switching circuit to switch the switching circuit to the phased array ultrasound mode, thus connecting the signal loop between the phased array ultrasound signal source and the sampling circuit. Similarly, the ultrasound signal in the phased array ultrasound mode is transmitted to the logic control unit for processing using the sampling circuit and the communication circuit. This process does not require restarting the logic control unit, which can shorten the switching time. Secondly, sharing the signal transmission link between the sampling circuit and the communication circuit can reduce the circuit structure, making the synthesized ultrasound imaging device smaller and more portable.

[0059] Furthermore, the multi-stage power supply circuit in the ultrasonic receiving circuit of this embodiment can meet the different voltage requirements of the switching circuit, sampling circuit, communication circuit, and logic control unit, thereby reducing the difficulty of power supply coordination design.

[0060] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0061] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0062] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. An ultrasonic receiving circuit, characterized in that, It includes a switching circuit, a sampling circuit, a communication circuit, and a logic control unit that are connected in sequence, as well as a multi-stage power supply circuit that is electrically connected to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit respectively; The multi-stage power supply circuit is configured to supply power to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the logic control unit respectively in response to a power-on signal; The switching circuit is configured to, in response to the level signal output by the logic control unit, connect the signal loop between the ultrasonic signal source and the sampling circuit; wherein, the ultrasonic signal source includes: a conventional ultrasonic signal source and a phased array ultrasonic signal source; The sampling circuit is configured to sample the ultrasonic signal transmitted in the signal loop; The communication circuit is configured to transmit the sampled data to the logic control unit for processing in response to the ultrasonic signal.

2. The ultrasonic receiving circuit according to claim 1, characterized in that, The switching circuit includes: An analog switch includes input terminals, output terminals, and control terminals; among which, The input terminal is electrically connected to the conventional ultrasonic signal source and the phased array ultrasonic signal source, respectively. The control terminal is electrically connected to the logic control unit; The output terminal is electrically connected to the sampling circuit and is configured to, in response to the level signal, connect the sampling circuit between the sampling circuit and the conventional ultrasonic signal source or the phased array ultrasonic signal source corresponding to the level signal.

3. The ultrasonic receiving circuit according to claim 2, characterized in that, The analog switch also includes a first power supply terminal and a second power supply terminal; The switching circuit further includes a bipolar power supply unit, which is electrically connected to the first power supply terminal and the second power supply terminal respectively, and is configured to provide a positive voltage to the first power supply terminal and a negative voltage to the second power supply terminal.

4. The ultrasonic receiving circuit according to claim 1, characterized in that, The sampling circuit includes: An amplification and filtering circuit, electrically connected to the output of the switching circuit, is configured to amplify and filter the ultrasonic signal output from the output of the switching circuit, and to output the processed ultrasonic signal to the communication circuit.

5. The ultrasonic receiving circuit according to claim 4, characterized in that, The communication circuit includes: A high-speed serial interface, electrically connected to the logic control unit, is configured to transmit the processed ultrasonic signal to the logic control unit in the form of a differential signal; The clock signal unit, electrically connected to the logic control unit, is configured to perform phase alignment processing on the signals transmitted through the high-speed serial interface.

6. The ultrasonic receiving circuit according to claim 5, characterized in that, The communication circuit also includes: The common-mode unit, electrically connected to the transmitter of the high-speed serial interface and the logic control unit, is configured to reduce common-mode noise on the transmission line where the differential signal is located.

7. The ultrasonic receiving circuit according to claim 1, characterized in that, The multi-stage power supply circuit includes: a primary power supply circuit, and multiple secondary power supply circuits electrically connected to the output terminal of the primary power supply circuit; wherein, The primary power supply circuit is electrically connected to the switching circuit, the sampling circuit, and the communication circuit, respectively, and is configured to output a first voltage to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the plurality of secondary power supply circuits in response to the power-on signal. The secondary power supply circuit is electrically connected to the switching circuit, the sampling circuit, and the communication circuit, respectively, and is configured to reduce the first voltage to a second voltage in response to the first voltage and output it to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit.

8. The ultrasonic receiving circuit according to claim 7, characterized in that, The primary power supply circuit includes: a power supply, a synchronous step-down unit, and a first filter unit; The synchronous buck unit is configured to, in response to the power-on signal, reduce the supply voltage output by the power supply to the first voltage and output it to the first filter unit. The first filtering unit is configured to, upon receiving the first voltage, filter out high-frequency noise in the first voltage and then output the first voltage to the switching circuit, the sampling circuit, the communication circuit, the logic control unit, and the plurality of secondary power supply circuits.

9. The ultrasonic receiving circuit according to claim 7, characterized in that, The secondary power supply circuit includes: a voltage regulator unit and a second filter unit; The voltage regulator unit is configured to reduce the first voltage and stabilize it at the second voltage when it receives the first voltage, and then output it to the second filter unit. The second filtering unit is configured to, upon receiving the second voltage, filter out high-frequency noise in the second voltage and then output the second voltage to the switching circuit, the sampling circuit, the communication circuit, and the logic control unit.

10. An ultrasonic imaging device, characterized in that, Includes the ultrasonic receiving circuit as described in any one of claims 1 to 9.

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