An optimally arranged trench gate power mosfet device
Patent Information
- Application Number
- CN202522419167.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-10-13
- Estimated Expiration
- 2035-11-14
AI Technical Summary
[0004]本实用新型的目的在于提供一种优化排布的沟槽栅功率MOSFET器件，以解决上述背景技术中提出的现有技术中尝试通过场环或浮空沟槽改善终端性能，但往往牺牲有源区面积或增加工艺步骤的问题
本实用新型通过体区掺杂浓度从中心向边缘递减，结合沟槽深度由中心向边缘逐渐变浅，有效调控了横向电场分布，缓解了边缘电场集中现象，其次，沟槽栅结构采用非对称交错排布并在芯片角落区域局部弯曲，进一步优化了电流路径与电场均匀性，抑制局部热点生成，同时，接触孔密度从中心向边缘递减，与电流密度分布相匹配，降低了边缘区域的焦耳热与寄生电阻，此外，有源区最外侧设置接地屏蔽沟槽，与有源沟槽保持隔离间距，增强了终端耐压能力，防止边缘提前击穿，配合边缘沟槽侧壁倾角更小、顶部多晶硅凹陷结构及梯形截面设计，多重手段协同抑制电场尖峰，整体结构在不增加工艺复杂度的前提下，实现了高击穿电压、低导通电阻、优异热稳定性与高可靠性的统一。
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Figure CN224852488U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of trench gate power MOSFET devices, specifically an optimized trench gate power MOSFET device. Background Technology
[0002] Traditional trench gate power MOSFETs typically employ a bulk structure with uniform cell arrangement, equal-depth trenches, and constant doping concentration.
[0003] However, under high-voltage operating conditions, such structures are prone to severe electric field concentration in the chip edge and corner areas, resulting in limited breakdown voltage and reduced reliability. At the same time, the uniformly distributed contact holes and fixed trench depths are difficult to match the actual current density distribution, causing Joule heat accumulation in the edge area, triggering local hot spots or even thermal runaway. Conventional terminal structures have limited ability to regulate electric fields and cannot effectively suppress premature breakdown at the edges. Although existing technologies have attempted to improve terminal performance through field rings or floating trenches, they often sacrifice the active area or increase process steps. Utility Model Content
[0004] The purpose of this invention is to provide an optimized trench gate power MOSFET device to solve the problem mentioned in the background art that attempts to improve terminal performance through field rings or floating trenches often sacrifices the active area or increases the number of process steps.
[0005] To achieve the above objectives, this utility model provides the following technical solution: an optimized trench gate power MOSFET device, comprising: Semiconductor substrate, serving as the bottom layer of the device; A drift region is formed on the upper surface of the semiconductor substrate and covers the entire active region; Multiple body regions are embedded in the upper region of the drift region and are distributed in an orderly manner. The doping concentration of the body regions in the edge region is lower than that in the center region, forming a lateral doping concentration gradient. A source doped region is disposed on the upper part of each of the bulk regions; The trench gate structure is provided in multiple groups. The trench of each trench gate structure extends downward from the chip surface, penetrates the corresponding body region and partially extends into the drift region. The trench sidewall of each trench gate structure is provided with a gate oxide layer. The trench is filled with a polysilicon gate. The multiple groups of trench gate structures are arranged asymmetrically in the active region. Adjacent rows of trench gate structures are staggered by half a cell spacing in the horizontal direction. The source metal layer covers the front of the chip; The contact hole penetrates the dielectric layer and connects the source metal layer to the underlying source doped region and body region. The distribution density of the contact hole decreases from the center to the edge. A shielding trench is provided on the outermost side of the active region, and an isolation gap is provided between the shielding trench and the outermost trench grid structure. The interior of the trench is filled with grounded polysilicon.
[0006] Furthermore, the trench gate structure is locally curved in the corner area of the chip, the depth of the trench gate structure in the central area of the chip is greater than that in the edge area, the trench depth gradually becomes shallower from the center to the edge, the cross-section of the trench of the trench gate structure is a trapezoid with a narrow top and a wide bottom, and the sidewall inclination angle of the trench in the edge area is smaller than that of the trench in the central area.
[0007] Furthermore, a local recessed structure is provided on top of the polysilicon gate in the edge region to alleviate electric field concentration.
[0008] Furthermore, the depth of the shielding trench is the same as the trench depth of the trench gate structure in the edge region, and it is electrically connected to the semiconductor substrate.
[0009] Furthermore, the contact holes are multiple strip-shaped openings distributed at the junction of the source doped region and the body region, so that the source metal layer can simultaneously form ohmic contact with both the source doped region and the body region.
[0010] Furthermore, the drift region is an N-type epitaxial layer, the bulk region is a P-type doped region, and the source doped region is an N-type doped region. + Heavy doped region.
[0011] Furthermore, a drain metal is provided on the back side of the semiconductor substrate, and the drain metal forms an ohmic contact with the semiconductor substrate. The gate metal is electrically connected to the polysilicon gate through a gate lead-out hole.
[0012] The technical solution provided by this utility model has the following advantages compared with the known prior art: This invention effectively regulates the lateral electric field distribution and alleviates the phenomenon of electric field concentration at the edges by decreasing the doping concentration in the body region from the center to the edge, combined with the gradual shallowing of the trench depth from the center to the edge. Secondly, the trench gate structure adopts an asymmetrical staggered arrangement and local bending in the corner area of the chip, which further optimizes the current path and electric field uniformity and suppresses the generation of local hot spots. At the same time, the contact hole density decreases from the center to the edge, matching the current density distribution, which reduces Joule heating and parasitic resistance in the edge area. In addition, a grounding shield trench is set on the outermost side of the active region to maintain an isolation distance from the active trench, which enhances the terminal withstand voltage capability and prevents premature breakdown at the edge. Combined with the smaller inclination angle of the edge trench sidewall, the top polysilicon recessed structure and trapezoidal cross-section design, multiple means work together to suppress electric field peaks. The overall structure achieves a unity of high breakdown voltage, low on-resistance, excellent thermal stability and high reliability without increasing the process complexity. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0014] Figure 1 This is a schematic diagram of the overall structure of this utility model; Figure 2 This is a schematic diagram of the source doped region structure of this utility model; Figure 3 This is a cross-sectional schematic diagram of the grooved grid structure of this utility model; Figure 4 For the present utility model Figure 3 A schematic diagram of the structure at point A; Figure 5 This is a top view of the arrangement of the grooved grid structure of this utility model; Figure 6 This is a schematic cross-sectional view of the shielding trench of this utility model.
[0015] In the figure: 1. Semiconductor substrate; 2. Drift region; 3. Body region; 4. Trench gate structure; 5. Source doped region; 6. Gate oxide layer; 7. Polysilicon gate; 8. Recessed structure; 9. Shielding trench; 10. Source metal layer; 11. Contact hole; 12. Drain metal; 13. Gate metal. Detailed Implementation
[0016] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.
[0017] The present invention will be further described below with reference to the embodiments.
[0018] Example: An optimized trench gate power MOSFET device, such as Figures 1-6 As shown, it includes: Semiconductor substrate 1, serving as the bottom layer of the device, is, in this embodiment, heavily doped N-type semiconductor substrate 1. + Type of silicon wafer, used to form the drain region of the device.
[0019] A drift region 2 is epitaxially grown on the upper surface of the semiconductor substrate 1. It is a lightly doped N-type epitaxial layer with a thickness and doping concentration designed according to the target voltage rating. The drift region 2 laterally covers the entire active region, which is the core area of the device containing cellular structures used to realize the main current conduction and switching functions.
[0020] In the upper region of the drift region 2, multiple body regions 3 are embedded. The body regions 3 are P-type doped regions and are arranged in an orderly manner, such as periodic linear or matrix arrangement, to form the channel region of the MOSFET. In particular, the body regions 3 in the edge region form a doping concentration gradient that decreases from the center to the edge in the lateral direction. This design helps to smooth the edge electric field distribution and suppress electric field concentration.
[0021] A source doped region 5 is provided on the upper part of each body region 3. The source doped region 5 is an N+ type heavily doped region, which together with the body region 3 forms the source contact region to ensure low-resistance ohmic connection.
[0022] like Figure 3 As shown, a trench gate structure 4 is provided through the above structure. The trench gate structure 4 is provided in multiple sets. The trench of each trench gate structure 4 is etched downward from the chip surface, passing through the source doped region 5 and the body region 3 in sequence, and further extending into the drift region 2. The inner sidewall of each trench is covered with a gate oxide layer 6 as a gate dielectric. The inside of the trench is completely filled with polysilicon to form a polysilicon gate 7.
[0023] like Figure 5 As shown, the trench gate structure 4 adopts an asymmetric staggered arrangement in the active region: adjacent rows of trenches are staggered by half a cell spacing in the horizontal direction to improve cell density and optimize current distribution uniformity. In addition, in the four corner regions of the chip, the trench direction is not straight, but locally curved along the tangent direction of the concentric circle with the chip center as the center, in order to adapt to the electric field distribution characteristics at the corner and avoid excessive concentration of electric field at right angles.
[0024] Furthermore, the trench depth of the trench gate structure 4 gradually decreases from the central region of the chip to the edge region, that is, the trench depth is the largest in the central region and the shallowest in the edge region. At the same time, the trench cross-section has a trapezoidal structure that is narrow at the top and wide at the bottom, and the sidewall inclination angle of the trench in the edge region is smaller than that in the central region, making the sidewall of the edge trench more vertical, which helps to improve the gate control capability and alleviate the surface electric field spikes.
[0025] A local recessed structure 8 is also provided on the top of the polysilicon gate 7 in the edge region. This recessed structure 8 is formed by process back etching, which can effectively reduce the electric field strength at the top corner of the trench and further improve the withstand voltage reliability.
[0026] A shielding trench 9 is arranged around the outermost part of the active region. A predetermined isolation distance is maintained between the shielding trench 9 and the outermost trench gate structure 4 to achieve electrical isolation. The shielding trench 9 is filled with polysilicon and is electrically connected to the semiconductor substrate 1, which plays the role of shielding the edge electric field and improving the terminal breakdown voltage. Its depth is the same as the depth of the trench gate structure 4 in the edge region to ensure a smooth electric field transition.
[0027] On the front side of the chip, a source metal layer 10 is covered, typically made of aluminum or an aluminum-silicon-copper alloy. To achieve electrical connection, contact holes 11 are provided between the source metal layer 10 and the underlying body region 3. The contact holes 11 are multiple strip-shaped openings, formed in the dielectric layer and distributed in the source doped region 5, so that the deposited source metal can simultaneously interact with the N-doped region. + The source doped region and the P-type body region form an ohmic contact, which effectively suppresses the conduction of parasitic bipolar transistors.
[0028] The distribution density of contact holes 11 decreases from the center of the chip to the edge, which matches the actual current density distribution trend and avoids local current congestion and Joule heat accumulation in the edge area due to excessively dense contact holes 11.
[0029] Finally, a drain metal 12 is formed on the semiconductor substrate 1 to form a low-resistance ohmic contact with the semiconductor substrate 1 as the drain terminal of the device. At the same time, a gate metal 13 is provided in a specific area on the front side of the chip, which is electrically connected to the polysilicon gate 7 through a gate lead-out hole for applying a gate control signal.
[0030] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of this utility model.
Claims
1. An optimized trench gate power MOSFET device, characterized in that, include: Semiconductor substrate (1) serves as the bottom layer of the device; A drift region (2) is formed on the upper surface of the semiconductor substrate (1) and covers the entire active region; Multiple body regions (3) are embedded in the upper region of the drift region (2) and are distributed in an orderly manner. The doping concentration of the body regions (3) in the edge region is lower than that in the center region, forming a lateral doping concentration gradient. A source doped region (5) is disposed on the upper part of each of the body regions (3); The trench gate structure (4) is provided in multiple sets. The trench of each trench gate structure (4) extends downward from the chip surface, penetrates the corresponding body region (3) and partially extends into the drift region (2). The trench sidewall of each trench gate structure (4) is provided with a gate oxide layer (6). The trench is filled with a polysilicon gate (7). The multiple sets of trench gate structures (4) are arranged asymmetrically in the active region. The adjacent rows of trench gate structures (4) are staggered by half a cell spacing in the horizontal direction. A source metal layer (10) is applied to the front side of the chip. Contact holes (11) penetrate the dielectric layer and connect the source metal layer (10) to the source doped region (5) and the body region (3) below. The distribution density of the contact holes (11) decreases from the center to the edge. A shielding trench (9) is provided on the outermost side of the active area. An isolation gap is provided between the shielding trench (9) and the outermost trench grid structure (4). The interior of the trench is filled with grounded polysilicon.
2. The trench gate power MOSFET device with optimized arrangement according to claim 1, characterized in that: The trench gate structure (4) is locally bent in the corner area of the chip. The depth of the trench gate structure (4) in the central area of the chip is greater than that in the edge area. The trench depth gradually becomes shallower from the center to the edge. The cross-section of the trench of the trench gate structure (4) is a trapezoid with a narrow top and a wide bottom. The sidewall inclination angle of the trench in the edge area is smaller than that of the trench in the central area.
3. The trench gate power MOSFET device with optimized arrangement according to claim 2, characterized in that: A local recessed structure (8) is provided on top of the polysilicon gate (7) in the edge region to alleviate electric field concentration.
4. The trench gate power MOSFET device with optimized arrangement according to claim 1, characterized in that: The depth of the shielding trench (9) is the same as the trench depth of the trench gate structure (4) in the edge region, and is electrically connected to the semiconductor substrate (1).
5. The trench gate power MOSFET device with optimized arrangement according to claim 1, characterized in that: The contact hole (11) is a plurality of strip-shaped openings distributed at the junction of the source doped region (5) and the body region (3), so that the source metal layer (10) forms an ohmic contact with both the source doped region (5) and the body region (3).
6. The trench gate power MOSFET device with optimized arrangement according to claim 1, characterized in that: The drift region (2) is an N-type epitaxial layer, the body region (3) is a P-type doped region, and the source doped region (5) is an N-type doped region. + Heavy doped region.
7. The trench gate power MOSFET device with optimized arrangement according to claim 6, characterized in that: The back side of the semiconductor substrate (1) is provided with a drain metal (12), which forms an ohmic contact with the semiconductor substrate (1), and the gate metal (13) is electrically connected to the polysilicon gate (7) through the gate lead-out hole.