Radio frequency integrated circuit structure and heterojunction bipolar transistor

Abstract

The utility model discloses a radio frequency integrated circuit structure and heterojunction bipolar transistor, including collector layer, emitter metal, first passivation layer, base metal and capacitor lower polar plate. Collector layer is equipped with active area and isolated area, and active area is equipped with base step and emitter step, and emitter step sets up on base step, emitter metal sets up on emitter step and forms ohmic contact with emitter step, first passivation layer covers on base step, emitter step and emitter metal, and first passivation layer is equipped with first windowing position, base metal sets up at first windowing position and forms ohmic contact with base step, capacitor lower polar plate and base metal set up in same metal layer, and capacitor lower polar plate is located isolated area and is connected with collector layer. Such can integrate source device and capacitor passive component, and can avoid capacitor passive component and lead to metal electrode surface rough because of forming intermetallic compound, is favorable for the performance of capacitor passive component.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a radio frequency integrated circuit structure and a heterojunction bipolar transistor. Background Technology

[0002] In gallium arsenide (GaAs) heterojunction bipolar transistors (HBTs), to achieve the design goals of high integration and low cost, the same metal layer as the collector metal of the HBT device is typically used as the lower electrode plate when manufacturing metal-insulator-metal (MIM) capacitors, and this is formed through a single photolithography and evaporation process. The collector metal is usually made of gold-germanium alloy (Au / Ge / Ni / Au), which forms an ohmic contact with the n-type GaAs epitaxial layer after a high-temperature annealing process. However, the surface of the collector metal becomes significantly rough after annealing. This rough surface can lead to problems such as poor uniformity of dielectric layer thickness, early breakdown risk in the dielectric layer, and easy induction of dielectric layer cracks. Utility Model Content

[0003] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a radio frequency integrated circuit structure and a heterojunction bipolar transistor, which can integrate active devices and passive capacitors, and can avoid the surface roughness of the metal electrodes caused by the formation of intermetallic compounds in passive capacitors, thereby improving the performance of passive capacitors.

[0004] On one hand, this utility model embodiment provides a radio frequency integrated circuit structure, including: The collector layer is provided with an active region and an isolation region. The active region is provided with a base step and an emitter step, and the emitter step is disposed on the base step. An emitter metal is disposed on the emitter step and forms an ohmic contact with the emitter step; A first passivation layer covers the base step, the emitter step, and the emitter metal, and a first window is provided on the first passivation layer; The base metal is disposed at the first window position and forms an ohmic contact with the base step; The lower electrode of the capacitor is disposed on the same metal layer as the base metal, and the lower electrode of the capacitor is located in the isolation region and connected to the current collector layer.

[0005] According to some embodiments of the present invention, the radio frequency integrated circuit structure further includes a second passivation layer, which covers the surfaces of the active region and the isolation region. The second passivation layer is provided with a second window position adapted to the first window position. The base metal is disposed at the first window position and the second window position and forms an ohmic contact with the base step.

[0006] According to some embodiments of the present invention, the second passivation layer is provided with a third window position, and the lower electrode plate of the capacitor is disposed at the third window position and connected to the current collector layer.

[0007] According to some embodiments of the present invention, the lower electrode of the capacitor is disposed on the second passivation layer.

[0008] According to some embodiments of the present invention, the base step has an inclined sidewall, and the second passivation layer covers the inclined sidewall.

[0009] According to some embodiments of the present invention, the first end of the base metal forms an ohmic contact with the base step, and the second end of the base metal extends along the inclined sidewall to the isolation region.

[0010] According to some embodiments of the present invention, there is an isolation gap between the second end of the base metal and the lower electrode plate of the capacitor.

[0011] According to some embodiments of the present invention, a recess is provided on the current collector layer and on the adjacent side of the base step, and a current collector metal is provided in the recess.

[0012] According to some embodiments of the present invention, a recess is provided on the current collector layer and on the adjacent side of the base step, and a current collector metal is provided in the recess. The second passivation layer also covers the current collector metal and the recess.

[0013] On the other hand, embodiments of the present invention provide a heterojunction bipolar transistor, including the above-described radio frequency integrated circuit structure.

[0014] The embodiments of this utility model have at least the following beneficial effects: The collector layer has an active region and an isolation region. The active region has a base step and an emitter step, and an emitter metal is disposed on the emitter step. A first passivation layer covers the base step, emitter step, and emitter metal. A first window is provided on the first passivation layer, and the base metal is disposed in the first window, forming an ohmic contact with the base step. The lower electrode of the capacitor is disposed on the same metal layer as the base metal and is located in the isolation region and connected to the collector layer. In this way, active devices and passive capacitors can be integrated. The lower electrode of the passive capacitor is disposed on the same metal layer as the base metal, which can avoid the surface roughness of the metal electrode caused by the formation of intermetallic compounds in the passive capacitor. This solves the problem caused by surface roughness at the source and is beneficial to improving the performance of the passive capacitor.

[0015] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the structural schematic diagrams of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 2 This is a second schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 3 This is the third schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 4 This is the fourth schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 5 This is the fifth schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 6 This is the sixth schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 7 This is the seventh schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 8 This is the eighth schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model; Figure 9 This is the ninth schematic diagram of the radio frequency integrated circuit structure according to an embodiment of the present utility model.

[0017] Figure label: Collector layer 100, active region 101, isolation region 102, recess 103, collector metal 104, base step 110, base metal 111, inclined sidewall 112, emitter step 120, emitter metal 121, first passivation layer 130, first window position 131, second passivation layer 140, second window position 141, third window position 142, fourth window position 143, lower electrode plate of capacitor 200, isolation gap 201. Detailed Implementation

[0018] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0019] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0020] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first," "second," etc., are used in the description, they are only for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the sequential relationship of the indicated technical features.

[0021] In the description of this utility model, unless otherwise explicitly defined, terms such as "setting", "connection", and "ohmic contact" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in conjunction with the specific content of the technical solution.

[0022] Gallium arsenide heterojunction bipolar transistors (GaAs HBTs), with their high electron mobility, high cutoff frequency, and excellent RF performance, have become core devices in applications such as power amplifiers, low-noise amplifiers, and RF switches. In GaAs HBT RF monolithic integrated circuits, metal-insulator-metal capacitors, as key passive components, are widely used for functions such as DC blocking, RF bypass, matching networks, and decoupling.

[0023] To achieve high integration and low cost design goals, MIM capacitors typically use the same metal layer as the collector metal 104 in HBT devices as the lower electrode, formed through a single photolithography and evaporation process. The collector metal 104 is usually a gold-germanium alloy (Au / Ge / Ni / Au), which forms an ohmic contact with an n-type GaAs epitaxial layer after high-temperature annealing. However, the surface of the annealed collector metal 104 becomes significantly rough. This is because the gold-germanium alloy reacts with gallium during annealing, forming a complex phase transition and an uneven morphology with numerous tiny peaks. This rough surface is directly covered by the subsequently deposited dielectric layer (such as a silicon nitride dielectric layer). When covering these microscopic peaks, the dielectric layer becomes thinner in localized areas, and its thickness uniformity deteriorates. When an operating voltage is applied, the electric field of the peaks becomes significantly concentrated, greatly increasing the risk of premature breakdown of the dielectric layer. In addition, rough interfaces can become concentration points of mechanical stress, making it easier to induce and propagate cracks in the dielectric layer during thermal cycling or electrical stress testing.

[0024] Therefore, this embodiment discloses a radio frequency integrated circuit structure and a heterojunction bipolar transistor, which integrates the source device and the passive capacitor component. Moreover, the lower electrode 200 of the passive capacitor component and the base metal 111 are disposed in the same metal layer (such as Pt / Ti / Pt / Au or Ti / Pt / Au, etc., which are diffusible materials or combinations of materials), avoiding the roughness of the metal electrode surface caused by the formation of intermetallic compounds. This can avoid a series of reliability problems caused by surface roughness from the source.

[0025] Example 1 This embodiment discloses a heterojunction bipolar transistor, including a radio frequency integrated circuit structure, please refer to... Figure 1 and Figure 2 The radio frequency integrated circuit structure includes a collector layer 100, an emitter metal 121, a first passivation layer 130, a base metal 111, and a lower capacitor plate 200. The collector layer 100 has active regions 101 and isolation regions 102. Multiple active regions 101 and multiple isolation regions 102 can be disposed on the collector layer 100. Isolation regions 102 are located between adjacent active regions 101 to achieve electrical signal isolation between adjacent active regions 101. The active regions 101 and isolation regions 102 can be implemented by doping the collector layer 100 with different impurity elements using an ion implantation process. The active region 101 has a base step 110 and an emitter step 120. The emitter step 120 is disposed on the base step 110, and the emitter metal 121 is disposed on the emitter step 120 and forms an ohmic contact with the emitter step 120. A first passivation layer 130 covers the base step 110, the emitter step 120, and the emitter metal 121. A first window 131 is provided on the first passivation layer 130. The first window 131 can be obtained by etching the first passivation layer 130 using an etching process. The shape of the first window 131 can be adjusted according to the shape of the base metal 111, for example, it can be a circular hole or a rectangular hole. The base metal 111 is disposed at the first window 131 and forms an ohmic contact with the base step 110. It should be noted that the area of ​​the base step 110 is larger than the area of ​​the emitter step 120. The lower capacitor plate 200 is disposed on the same metal layer as the base metal 111. The lower capacitor plate 200 is located in the isolation region 102 and connected to the current collector layer 100. In this way, active devices and passive capacitors can be integrated. The lower electrode 200 of the passive capacitor and the base metal 111 are disposed on the same metal layer, which avoids surface roughness of the metal electrode caused by the formation of intermetallic compounds. This solves the problem caused by surface roughness at its source and is beneficial to improving the performance of the passive capacitor. Figure 1 The structure shown is a schematic diagram of the first semi-finished product state during the processing. Figure 2 In order to be in Figure 1 A schematic diagram of the second semi-finished product state after the base metal 111 and the lower electrode plate 200 of the capacitor have been processed from the first semi-finished product state shown.

[0026] In one related technology, the collector metal is a gold-germanium alloy, which has a low eutectic point (typically around 360°C). This system involves alloying and recrystallization of the metal on the GaAs surface. During annealing, the gold-germanium alloy melts to form a liquid eutectic phase. Due to the high surface tension of the liquid metal, it tends to agglomerate into spheres to reduce surface area. This morphology leads to uneven reaction between the metal and GaAs, resulting in some areas reacting violently while others react only slightly. This uneven reaction is the direct cause of the uneven metal surface and the formation of spikes. However, when a base metal system (such as Pt / Ti / Pt / Au or Ti / Pt / Au, etc., diffusible materials or combinations thereof) is used, Pt / Ti has a high melting point and remains solid during annealing, forming intermetallic compounds with GaAs. The absence of a liquid phase during the reaction makes the reaction more controllable and uniform. By eliminating microscopic spikes, the uniformity of the dielectric layer is greatly improved, electric field concentration is avoided, and the capacitor's breakdown voltage and reliability are significantly enhanced.

[0027] Furthermore, the relatively flat lower electrode plate of the capacitor provided in this embodiment can eliminate the risks of uneven dielectric layer thickness and electric field concentration caused by the traditional rough metal electrode plate of the capacitor. It can safely use a thinner capacitor dielectric layer without worrying about early breakdown caused by local thinning. The capacitance density is significantly improved, which means that the physical size of the capacitor element can be greatly reduced while achieving the same capacitance. This is beneficial to improving the area utilization efficiency of GaAs wafers and reducing the cost of a single chip.

[0028] Example 2 Please refer to Figure 1 , Figure 3 and Figure 4Based on the structure of Embodiment 1, the RF integrated circuit structure further includes a second passivation layer 140. The second passivation layer 140 covers the surfaces of the active region 101 and the isolation region 102. The second passivation layer 140 is provided with a second window position 141 adapted to the first window position 131. The base metal 111 is disposed at the first window position 131 and the second window position 141, and forms an ohmic contact with the base step 110. It should be understood that after processing, the base step 110 and the emitter metal 121 are stacked on the surface of the active region 101 of the collector layer 100. Therefore, the second passivation layer 140 also covers the base step 110 and the emitter metal 121. The second passivation layer 140 can block environmental moisture, contaminants and mechanical stress, prevent device performance degradation, and regulate the electric field distribution to improve reliability and stability. The position and size of the second window 141 are adapted to the position and size of the first window 131. For example, during processing, a second passivation layer 140 is deposited on the surface of the first passivation layer 130, and windows are etched into the second passivation layer 140 and the first passivation layer 130 based on an etching process, thereby creating a window that extends through the first passivation layer 130 and the second passivation layer 140. Metal is deposited in the first window 131 and the second window 141 to form the base metal 111, achieving ohmic contact between the base metal 111 and the base step 110.

[0029] Example 3 Please refer to Figure 3 and Figure 4 Based on the structure of Embodiment 2, the second passivation layer 140 is provided with a third window position 142, and the lower electrode plate 200 of the capacitor is disposed at the third window position 142 and connected to the current collector layer 100. The position of the third window position 142 is adapted to the position of the lower electrode plate 200 of the capacitor, that is, the third window position 142 is formed in the isolation region 102 of the current collector layer 100, and the third window position 142 can be obtained by etching the second passivation layer 140 using an etching process. The third window position 142 can expose the current collector layer 100 located at the bottom of the second passivation layer 140, so that the lower electrode plate 200 of the capacitor can be processed on the current collector layer 100, that is, the lower electrode plate 200 of the capacitor is connected to the current collector layer 100. It should be noted that both the lower electrode 200 and the base metal 111 are made of metal. Compared with the bonding force of the current collector layer 100, the bonding force between the metal material and the second passivation layer 140 is relatively weak. Therefore, by setting the third window position 142, the lower electrode 200 and the current collector layer 100 are directly connected, which helps to improve the connection reliability of the lower electrode 200.

[0030] Example 4 Please refer to Figure 3 and Figure 5Based on the structure of Embodiment 2, the lower electrode plate 200 of the capacitor is disposed on the second passivation layer 140. The second passivation layer 140 can serve as an isolation between the lower electrode plate 200 of the capacitor and the current collector layer 100. Moreover, compared with Embodiment 3, this embodiment does not require the third opening position 142 to be opened on the second passivation layer 140 during processing, which can save processing steps.

[0031] Example 5 Please continue to refer to Figure 3 and Figure 5 Based on the structure of Embodiments 2, 3, or 4, the base step 110 has an inclined sidewall 112, and a second passivation layer 140 covers the inclined sidewall 112. Please refer to... Figure 5 The base step 110 has a trapezoidal cross-sectional shape, with the upper side of the trapezoid shorter than the lower side. The connection between the upper and lower sides of the trapezoid is a side, and the side and lower side form an angle of less than 90°. In other words, the inclined sidewall 112 of the base step 110 forms an angle of less than 90° with its bottom. The second passivation layer 140 covers the inclined sidewall 112, providing full coverage of the base step 110 and thus isolating and protecting it.

[0032] Example 6 Please refer to Figure 5 and Figure 6 Based on the structure of Embodiment 5, the first end of the base metal 111 forms an ohmic contact with the base step 110, and the second end of the base metal 111 extends along the inclined sidewall 112 to the isolation region 102. The first end of the base metal 111 forms an ohmic contact with the base step 110 to realize electrical signal connection, while the second end of the base metal 111 extends to the isolation region 102. Since the surface of the base step 110 is covered with a second passivation layer 140, the second passivation layer 140 can play an isolation role, and the base metal 111 can extend along the sidewall of the base step 110, thereby reducing the area occupied by the base metal 111 on the base step 110, so that the area of ​​the base step 110 can be made smaller.

[0033] Example 7 Please refer to Figure 6Based on the structure of Embodiment 6, an isolation gap 201 is provided between the second end of the base metal 111 and the lower electrode plate 200 of the capacitor. For example, during the processing, the first window position 131, the second window position, and the third window position 142 are etched on the second passivation layer 140 using an etching process. Then, based on a metal deposition process, the base metal 111 is deposited at the positions corresponding to the first window position 131 and the second window position 141, as well as on the inclined sidewall 112 of the base step 110. During the deposition process of the base metal 111, the lower electrode plate 200 of the capacitor is simultaneously deposited at the third window position 142. In this way, an isolation gap 201 can be processed between the second end of the base metal 111 and the lower electrode plate 200 of the capacitor. This allows for the simultaneous processing of the base metal 111 and the lower electrode plate 200 of the capacitor, and the base metal 111 and the lower electrode plate 200 of the capacitor use the same alloy material and are located in the same metal layer. It should be understood that during the deposition process, metal can be deposited at the desired location by applying a mask and making windows at different positions on the mask. For example, during processing, a base metal 111 and a lower capacitor plate 200 are fabricated based on a deposition process, wherein the base metal 111 and the lower capacitor plate 200 are integrally connected, and then an isolation gap 201 is etched between the base metal 111 and the lower capacitor plate 200 based on an etching process.

[0034] Example 8 Please refer to Figure 1 and Figure 2 Based on the structure of any one of embodiments 1 to 7, a recess 103 is provided on the current collector layer 100 and adjacent to the base step 110. A current collector metal 104 is disposed within the recess 103, forming an ohmic contact between the current collector metal 104 and the current collector layer 100. During processing, the recess 103 is etched into the current collector layer 100 using an etching process, and then metal is deposited within the recess 103 using a metal deposition process to form the current collector metal 104. In this way, electrical signals of the current collector layer 100 can be transmitted through the current collector metal 104.

[0035] Please refer to Figure 3 , Figure 4 and Figure 5 In the case where a second passivation layer 140 is processed, the second passivation layer 140 is etched based on an etching process to process corresponding window positions (such as the first window position 131, the second window position 141 and the third window position 142) and expose the current collector layer 100 at the fourth window position 143. Then, the base metal 111 and the lower electrode plate 200 of the capacitor are processed based on a metal deposition process. Next, the current collector layer 100 is etched at the fourth window position 143 to process a recess 103. Finally, metal is deposited in the recess 103 based on a metal deposition process to form the current collector metal 104.

[0036] Example 9 Please refer to Figure 3 , Figure 7 , Figure 8 and Figure 9 Based on the structure of any of embodiments 2 to 7, a recess 103 is provided on the current collector layer 100 and adjacent to the base step 110. A current collector metal 104 is disposed in the recess 103. A second passivation layer 140 also covers the current collector metal 104 and the recess 103, and the second passivation layer 140 can isolate and protect the current collector metal 104 and the recess 103. During the processing, the recess 103 is etched on the current collector layer 100 based on an etching process, and metal is deposited in the recess 103 based on a metal deposition process to form the current collector metal 104. Then, the second passivation layer 140 is deposited, and the second passivation layer 140 is then windowed, and the base metal 111 and the lower electrode plate 200 of the capacitor are deposited.

[0037] Based on the radio frequency integrated circuit structure of the above embodiments, a transistor active device including a base step 110, an emitter step 120, a base metal 111, an emitter metal 121 and a collector metal 104, and a capacitor lower plate 200 of a capacitor passive element can be integrated. On the basis of the capacitor lower plate 200, structures such as a capacitor dielectric layer and a capacitor upper plate can be processed to form a complete capacitor passive element.

[0038] The embodiments of the present utility model have been described in detail above with reference to the accompanying drawings. However, the present utility model is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present utility model.

Claims

1. A radio frequency integrated circuit structure, characterized in that, include: The collector layer (100) is provided with an active region (101) and an isolation region (102). The active region (101) is provided with a base step (110) and an emitter step (120). The emitter step (120) is disposed on the base step (110). Emitter metal (121) is disposed on the emitter step (120) and forms an ohmic contact with the emitter step (120); A first passivation layer (130) covers the base step (110), the emitter step (120) and the emitter metal (121), and a first window position (131) is provided on the first passivation layer (130). The base metal (111) is disposed at the first window position (131) and forms an ohmic contact with the base step (110); The lower electrode plate (200) of the capacitor is disposed on the same metal layer as the base metal (111). The lower electrode plate (200) is located in the isolation region (102) and connected to the current collector layer (100).

2. The radio frequency integrated circuit structure according to claim 1, characterized in that, The radio frequency integrated circuit structure further includes a second passivation layer (140), which covers the surfaces of the active region (101) and the isolation region (102). The second passivation layer (140) is provided with a second window position (141) adapted to the first window position (131). The base metal (111) is disposed at the first window position (131) and the second window position (141) and forms an ohmic contact with the base step (110).

3. The radio frequency integrated circuit structure according to claim 2, characterized in that, The second passivation layer (140) is provided with a third window position (142), and the lower electrode plate (200) of the capacitor is disposed in the third window position (142) and connected to the current collector layer (100).

4. The radio frequency integrated circuit structure according to claim 2, characterized in that, The lower electrode plate (200) of the capacitor is disposed on the second passivation layer (140).

5. The radio frequency integrated circuit structure according to claim 2, 3 or 4, characterized in that, The base step (110) has an inclined sidewall (112), and the second passivation layer (140) covers the inclined sidewall (112).

6. The radio frequency integrated circuit structure according to claim 5, characterized in that, The first end of the base metal (111) forms an ohmic contact with the base step (110), and the second end of the base metal (111) extends along the inclined sidewall (112) to the isolation region (102).

7. The radio frequency integrated circuit structure according to claim 6, characterized in that, There is an isolation gap (201) between the second end of the base metal (111) and the lower electrode plate (200) of the capacitor.

8. The radio frequency integrated circuit structure according to any one of claims 1 to 4, 6 or 7, characterized in that, A recess (103) is provided on the current collector layer (100) and on the adjacent side of the base step (110), and a current collector metal (104) is provided in the recess (103).

9. The radio frequency integrated circuit structure according to any one of claims 2 to 4, 6 or 7, characterized in that, A recess (103) is provided on the current collector layer (100) and adjacent to the base step (110). A current collector metal (104) is provided in the recess (103). The second passivation layer (140) also covers the current collector metal (104) and the recess (103).

10. A heterojunction bipolar transistor, characterized in that, Includes the radio frequency integrated circuit structure as described in any one of claims 1 to 9.

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