Integrated circuit device

Abstract

Various embodiments of the present inventive subject matter relate to an integrated circuit (IC) device having a substrate including a P-well region and a dielectric structure. The dielectric structure is located at a surface of the substrate, extends downward into the substrate, and is located at a lateral perimeter of the P-well region. The IC device also includes a dielectric layer located above the P-well region and laterally extending above the dielectric structure. The IC device also includes an N+ gate structure located above the dielectric layer and at least one P+ region located above the P-well region and the dielectric structure of the substrate.

Description

Technical Field

[0001] This utility model relates to an integrated circuit device. Background Technology

[0002] Ultra-low power complementary metal-oxide-semiconductor (CMOS) reference voltage circuits are becoming increasingly important in the implementation of various types of integrated circuit (IC) devices, including, but not limited to, display drivers, digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). A corresponding focus is on providing highly accurate reference voltages in a cost-effective manner across a range of process technologies. Utility Model Content

[0003] This invention provides an integrated circuit device. The integrated circuit device includes a substrate and a dielectric structure. The substrate includes a P-well region, and the dielectric structure is located on the surface of the substrate, extending downward into the substrate and at the lateral perimeter of the P-well region. The integrated circuit device also includes a dielectric layer located above the P-well region and laterally extending above the dielectric structure. The integrated circuit device further includes an N+ gate structure located above the dielectric layer and including at least one P+ region, which is located above the P-well region of the substrate and the dielectric structure.

[0004] Another aspect of this utility model provides an integrated circuit device. The integrated circuit device includes a reference voltage circuit. The reference voltage circuit includes a flip-gate assembly (FGD) and a normal gate assembly (NGD). The flip-gate assembly includes a first P-well region in a substrate, a first N+ source-drain region and a second N+ source-drain region in the first P-well region, and a P+ gate structure. The P+ gate structure is located above the first P-well region and, in a plan view of the integrated circuit device, between the first N+ source-drain region and the second N+ source-drain region. The P+ gate structure includes a first N+ region aligned side-by-side with the first N+ source-drain region in the plan view and a second N+ region aligned side-by-side with the second N+ source-drain region in the plan view. The normal gate assembly includes a second P-well region in a substrate, a third N+ source-drain region and a fourth N+ source-drain region in the second P-well region, and an N+ gate structure. The N+ gate structure is located above the second P-well region and, in the plan view, lies between the third N+ source-drain region and the fourth N+ source-drain region. The N+ gate structure includes at least one P+ region extending between the third N+ source-drain region and the fourth N+ source-drain region in the plan view, wherein the N+ gate structure is electrically connected to the P+ gate structure.

[0005] Another aspect of this invention provides a method for forming an integrated circuit device. The method includes providing a substrate including a P-well region. The method further includes forming a trench on the upper surface of the P-well region. The method further includes forming a dielectric structure in the trench. The method further includes forming a dielectric layer over the P-well region and the dielectric structure. The method further includes forming an N+ gate structure over the dielectric layer. The method further includes forming at least one P+ region in the N+ gate structure, the at least one P+ region being located over the P-well region and the dielectric structure.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 Schematic diagrams are shown of some embodiments of a CMOS-only reference voltage circuit according to the present invention.

[0008] Figure 2 The diagram shows cross-sectional views of some embodiments of a shallow trench isolation (STI) structure with a "recessed" feature according to the present invention, as shown in a normal gate assembly (NGD) of a CMOS reference voltage circuit, which may adversely affect the accuracy of the CMOS reference voltage circuit.

[0009] Figure 3 The graph shows the current-voltage (IV) curves of the NGD under different bias voltages according to the present invention, which can exhibit the "hump" effect caused by the dip feature, which adversely affects the accuracy of the CMOS reference voltage.

[0010] Figure 4A and Figure 4B The layout diagram and cross-sectional view of the NGD including the gate inversion doped region according to the present invention are shown respectively.

[0011] Figure 5 An exemplary current flow in an NGD affected by a gate inversion doped region according to the present invention is shown.

[0012] Figure 6 The diagram shows an IV curve illustrating an exemplary gamma value, which can be used to quantify the effect of the hump effect of NGD on the critical voltage.

[0013] Figure 7 The graph shows the IV curves and related gamma values ​​of NGD with and without the implementation of the gate inversion doped region according to the present invention.

[0014] Figure 8A graph showing an exemplary temperature coefficient comparison with reference voltage performance for NGD with and without a gate inversion doped region according to the present invention.

[0015] Figures 9A to 9F Cross-sectional views are shown of several embodiments of NGD and corresponding FGD (Flip Gate Diode) implementing the gate inversion doped region according to the present invention at various manufacturing stages.

[0016] Figure 9G This invention illustrates the content of the present invention. Figure 9F Different sectional views of FGD.

[0017] Figure 9H This invention illustrates the content and... Figure 9G The relevant floor plan of FGD 104.

[0018] Figure 10 This invention illustrates a system comprising, according to the present invention, including, Figures 9A to 9F Methods of some embodiments of NGD for gate inversion doped regions. Detailed Implementation

[0019] This utility model provides numerous different embodiments or examples for implementing various features of this utility model. Specific examples of components and arrangements are described below to simplify the utility model. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various instances of this utility model. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0021] Figure 1Schematic diagrams of some embodiments of a CMOS-only reference voltage circuit 100 according to the present invention are shown. As shown, the reference voltage circuit 100 may include a normal gate transistor device (NGD) 102 and a flipped gate transistor device (FGD) 104, their gate terminals being connected together and connected to the drain terminal of the FGD 104. Furthermore, at a first voltage terminal (e.g., drain voltage V...), DD A first current source I1 can be located between the source terminal of NGD 102 and the drain terminal of FGD 104. A second current source I2 can connect the source terminal of NGD 102 to a second voltage terminal (e.g., ground reference or source voltage V). SS Embodiments of current sources I1 and I2 may include one or more transistors and / or other components, but these sources will not be discussed in more detail herein. In some embodiments, a plurality (e.g., N1) of FGD 104 may be coupled together in parallel, and a plurality (e.g., N2) of NGD 102 may be coupled together in parallel, wherein the parallel components may be coupled together at one or more of their gate, source, and drain terminals.

[0022] In some embodiments, NGD 102 may be a standard or “regular” nMOS transistor assembly, which may include a p-doped (P+) substrate, an n-doped (N+) drain region and an N+ source region in the substrate, and an N+ polysilicon gate structure located above the substrate. Therefore, in the regular gate assembly NGD 102, the doping (e.g., implantation or diffusion) of the gate structure (N+) is opposite to the doping of the substrate (P+). FGD 104 may be an nMOS transistor assembly, which also includes a P+ substrate and an N+ drain region and an N+ source region in the substrate. However, FGD 104 also includes a “flipped” gate structure, which may include a P+ polysilicon gate having one or more inverted doped (N+) regions (e.g., at the lateral edges of the gate structure). Therefore, as used herein, the substrate of FGD 104 has the same or similar doping (P+) as the gate structure, and is therefore “flipped” compared to NGD 102. Moreover, as used in this paper, the source / drain region can refer to the source or drain individually or collectively, depending on the context.

[0023] In some embodiments, the reference voltage circuit 100 may utilize the polysilicon work function difference between one or more NGD 102 and FGD 104 to establish a reference voltage V. ref Furthermore, in some embodiments, the reference voltage V refThe current density I1 / N1 of one or more FGD 104s and the current density I2 / N2 of one or more NGD 102s can be determined. Furthermore, since the NGD 102 and FGD 104 operate within the subthreshold range of the reference voltage circuit 100, the subthreshold current ratio and associated standard deviation of the NGD 102 and FGD 104 may affect the reference voltage V. ref Accuracy. In some embodiments, the reference voltage V generated by the reference voltage circuit 100 ref It can be specified as follows:

[0024]

[0025] V t,FGD It is the critical voltage of FGD 104, V t,NGD V is the critical voltage of NGD 102, n is the ideality factor (e.g., the quality factor or emission coefficient in the Shockley ideal diode equation), and V T It is thermal voltage (e.g., also from the Shockley ideal diode equation).

[0026] When operating NGD 102 and FGD 104 in the subcritical region, a phenomenon known as the "corner effect" can affect the performance (e.g., accuracy, precision, and / or thermal stability) of the reference voltage circuit 100. Generally, the corner effect is an enhancement of leakage current at the edge of the active region isolated by a shallow trench isolation (STI) structure in a CMOS transistor. In some cases, the corner effect may be affected by the presence of a "divot" characteristic typically associated with STI structures.

[0027] Figure 2 Cross-sectional views of some embodiments of a dielectric (STI) structure 204 having such a recessed feature 210 according to the present invention are shown, as in NGD 102, which may adversely affect the performance of the reference voltage circuit 100. Figure 2 As shown, the dielectric structure 204 can be formed laterally toward the P-well region 206 of the substrate, on which the gate structure 202 and the dielectric layer (e.g., gate oxide structure) 208 can be formed. In 90-nanometer (nm) technology and other low-cost processes, it may be difficult to control the presence, shape, size, and / or depth of the recessed feature 210. As a result, due to the greater control exerted by the gate structure 202 in the vicinity of the recessed feature 210, shape variations of the recessed feature 210 may cause changes in the critical voltage V of the NGD 102. t Corresponding changes (e.g., reduction) may lead to the development of the "hump" effect.

[0028] Figure 3 The diagram shows the current-voltage (IV) curves 300 of the NGD 102, which exhibits a hump effect 302 under different bias voltages Vb according to the present invention. The hump effect 302 is characterized by a lower drain current I... d Critical voltage V at the point t Reduce. For example... Figure 3 As shown, the hump effect 302 can change with the reverse bias (e.g., V). b =X b ,like Figure 3 As shown, in some embodiments, X b The presence or increase of the voltage (within the range of 0.5 volts (V) to 5.0 V) can make it more pronounced or enhanced. Critical voltage V t The decrease may cause the reference voltage V provided by the reference voltage circuit 100 to be reduced. ref The accuracy and repeatability decrease. Additionally, such as... Figure 3 As shown, in some embodiments, the voltage X1 can range from 0.5V to 5.0V, and the current Y1 can range from 1 nanoamp (nA) to 1 milliamp (mA), wherein the critical voltage V t Displayed on a linear scale, and drain current I d Represented on a logarithmic scale.

[0029] To address these issues, this invention provides embodiments of integrated circuit (IC) devices including NGD transistor components (e.g., NGD 102), which include gate inversion-doped regions that can be disposed above the gate oxide or other dielectric layer and at the edge of the STI structure (e.g., in the P-well region). As used herein, an "inversion" doped (e.g., implanted) region can be a region that is doped opposite to the surrounding region in its particular material or structure. In some embodiments, as described in more detail below, the gate inversion-doped region can reduce the channel current in the subcritical region, thereby reducing the effect of the STI structure recess feature 210 and the associated hump effect 302, thereby improving the performance of the reference voltage circuit 100. Furthermore, in some embodiments, as described more fully below, the addition of the gate inversion-doped region may not require any additional process steps related to minimal changes in the circuit layout associated with the creation of the reference voltage circuit 100.

[0030] In the various embodiments discussed below, although the inversion region is referred to as the implantation region, other doping methods (e.g., diffusion) can be used to generate the inversion region, as well as other N+ and P+ regions mentioned below.

[0031] Figure 4A and Figure 4BLayout view 400A and cross-sectional view 400B of an NGD 102 including a gate inversion-doped (e.g., implanted) region (e.g., P+ region) 410 according to the present invention are shown respectively. More specifically, Figure 4B The position of the sectional view 400B is through Figure 4A The dashed lines shown are used to indicate this. For example... Figure 4B As shown, in some embodiments, the NGD 102 may include a substrate, wherein a deep N-well region 408 is located beneath a P-well region 206, which may be laterally surrounded by the N-well region 402. In some embodiments, the P-well region 206 may provide a semiconductor channel through which current can flow between the N+ source region (or the first N+ source-drain region) 404 and the N+ drain region (or the second N+ source-drain region) 406, such as... Figure 4A and Figure 4B As shown. In some embodiments, the substrate may include silicon (Si) or another semiconductor material.

[0032] In some embodiments, a dielectric structure (e.g., a shallow trench isolation (STI) structure) 204 may be formed in the substrate at the P-well region 206. More specifically, in some embodiments, the dielectric structure 204 may be formed at the surface of the substrate and extend at least partially downward into the substrate. Furthermore, in some embodiments, the dielectric structure 204 may be located at the lateral perimeter of the P-well region 206 (e.g., along the N-well region 402), such as... Figure 4B As shown. Furthermore, the dielectric structure 204 may be partially or entirely disposed along the lateral perimeter of the P-well region 206. In some embodiments, the dielectric structure 204 may comprise silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)), or another oxide or dielectric material (e.g., silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, etc.).

[0033] In some embodiments, the dielectric layer (e.g., gate oxide, such as silicon oxide (SiO2)) x(For example, silicon dioxide (SiO2)) or another oxide or dielectric material, as described above) 208 can be disposed above the P-well region 206 and at least a portion of the dielectric structure 204 (e.g., on top of the P-well region 206 and at least a portion of the dielectric structure 204). In some embodiments, the side edges of the dielectric layer 208 can be located above the dielectric structure 204. Furthermore, an N+ (n-doped) gate structure 202 can be disposed above the dielectric layer 208 (e.g., on top of the dielectric layer 208). In some embodiments, such as Figure 4B As shown, the lateral extent of the N+ gate structure 202 can be substantially matched with the lateral extent of the dielectric layer 208.

[0034] In some embodiments, at least one P+ (p-doped) region 410 may be disposed within the N+ gate structure 202 as an inversion doped region, as described above. Figure 4A and Figure 4B As shown, two P+ regions 410 may exist, each P+ region 410 being disposed above the dielectric structure 204 and the P-well region 206. In some embodiments, one side of the P+ region 410 may exist above the dielectric structure 204, while the opposite side of the P+ region 410 may exist above the P-well region 206, but not above the dielectric structure 204. Furthermore, in some embodiments, each P+ region 410 may extend along a corresponding laterally-facing side of the dielectric structure 204 perpendicular to the first N+ source-drain region 404 and the second N+ source-drain region 406 and between the first N+ source-drain region 404 and the second N+ source-drain region 406. More specifically, the first P+ region 410 may extend over the middle portion of the first side edge of the dielectric structure 204 perpendicular to the first and second ends of the dielectric layer 208, and the second P+ region 410 may extend over the middle portion of the second side edge of the dielectric structure 204 opposite to the first side edge. Furthermore, in some embodiments, the length of the middle portion of the first and second side edges of the dielectric structure 204 may be at least 75% of the lengths of the corresponding first and second side edges. However, in other embodiments, other percentages of the length of the middle portion relative to the first and second side edges of the dielectric structure 204 may be used (e.g., 50%, 55%, 60%, 65%, or greater than 75%). Furthermore, as... Figure 4B As shown, the first and second side edges of the dielectric structure 204 can face each other through the central portion of the P-well region 206. Furthermore, in some embodiments, each P+ region 410 can be completely laterally surrounded by the N+ gate structure 202. Additionally, in some embodiments, each P+ region 410 can extend from the top surface to the bottom surface of the N+ gate structure 202. Moreover, in some embodiments, such as... Figure 4BAs shown, each P+ region 410 can be narrower than the dielectric structure 204 in a plan view or layout diagram.

[0035] Although Figure 4A and Figure 4B The diagram shows that each P+ region 410 has a specific depth, width, and length relative to other structures of NGD 102, but other relative dimensions for each P+ region 410 are also possible in other embodiments.

[0036] Figure 5 Layout Figure 500A illustrates an exemplary current flow in an NGD 102 affected by a gate inversion doped region (e.g., P+ region 410) according to the present invention. As indicated, most of the current can flow between the first N+ source-drain region 404 and the second N+ source-drain region 406 via a channel in the P-well region 206 beneath the N+ gate structure 202. Therefore, the amount of leakage current that might pass through the recessed feature 210 at the edge of the dielectric structure 204 beneath the N+ gate structure 202 can be reduced or minimized by the presence of the P+ region 410, which can be used to suppress any such leakage current through the relevant portion of the dielectric structure 204. In some embodiments, the P+ region 410 can alter the polysilicon work function of the N+ gate structure 202 at its location. This altered work function can cause a critical voltage V at these locations. t Increase, thereby reducing the critical voltage V in the P+ region 410. t The critical voltage V along the dielectric structure 204 near other locations close to the first N+ source-drain region 404 and the second N+ source-drain region 406 t The difference between them leads to a reduced hump effect 302 and a lower associated leakage current.

[0037] Therefore, in some embodiments, when used in the NGD 102 of the reference voltage circuit 100, using one or more P+ regions 410 can generate a more accurate and stable reference voltage V. ref As discussed below, this accuracy and stability may be related to the "gamma" value associated with NGD 102. Generally, the gamma value is used to quantify the gate-source voltage V. gs The critical voltage V represented in the figure t How is it affected by the source-substrate reverse bias voltage V? b The impact. More specifically, for our purposes, Figure 6 Figure 600 shows an IV curve illustrating an exemplary gamma value, which can be used to quantify the hump effect 302 of NGD 102 on the critical voltage V. t The impact.

[0038] As described above, the hump effect 302 caused by the dip feature 210 may affect the corresponding drain current I. d Critical voltage V at the point t OR gate-source voltage V gs . Figure 6 Two IV curves are shown: the first curve shows the IV curve under bias V. b When = 0, the corresponding gate-source voltage V gs Various drain currents I at the location d The second curve shows that at a certain non-zero bias voltage V b When =x, the corresponding gate-source voltage V gs Drain current I at the location d Given these two curves, two gamma values ​​are defined: gamma 1 601 and gamma 2 602, which can provide the reference voltage V of the resulting reference voltage circuit 100 with respect to the hump effect 302. ref Some insights into the impact of accuracy and precision.

[0039] Gamma (γ) can be for two different bias voltages (e.g., zero bias V). b =0 (or V) b0 ) and non-zero bias (e.g., V b Within the range of -5V to -0.5V, at a specific drain current I d Gate-source voltage V at the location gs The difference between them. Mathematically, gamma can be defined as follows:

[0040]

[0041] In the gamma equation, 2φ f This refers to the surface potential or contact potential. Assuming a surface potential of 0.65, in some embodiments, the gamma can be as follows:

[0042]

[0043] In addition, such as Figure 6 As shown, Gamma 1601 is based on the drain current I d = Gamma value at A (e.g., in some embodiments, in the range of 10-500 nanoamps (nA)), and gamma 2 602 is the drain current I d = Gamma value at B (e.g., in some embodiments, in the range of 0.5-5 nA). In some embodiments, gamma 1 601 is the gate-source voltage V affected by the hump effect 302. gs Within the range, while Gamma 2 602 is the gate-source voltage V affected by the hump effect 302. gs Outside of that range. For example, with drain current I... d=C (e.g., in some embodiments, in the range of 0.05-0.5nA) can be approximately the same as gamma 2 602. Therefore, by comparing the difference between gamma 1 601 and gamma 2 602 of two different NGD 102 (e.g., one with P+ region 410 used as a gate inversion region and the other without), a judgment can be made regarding the relative effectiveness of P+ region 410.

[0044] Figure 7 This illustration shows implementations of the present invention with and without gate inversion doping or implantation regions (e.g., P+ region 410, as shown). Figure 4A and Figure 4B Figure 700 shows the IV curve and related gamma values ​​of the NGD 102 (as shown). The drain current of the NGD 102, including the P+ region 410, is expressed as I. d The drain current of NGD 102, excluding the P+ region 410, is expressed as I. d Therefore, in Figure 7 In the visual review, due to the significant hump effect 302 applied at a non-zero bias voltage, the IV curve I associated with NGD102 excluding the P+ region 410 was significantly different. d (V b =0)701 and IV curve I d (V b =x)702 causes gamma 1 (I d ) significantly greater than gamma 2 (I d ), as mentioned above Figure 3 As mentioned. Conversely, IV curve I associated with NGD 102, including the P+ region 410. d '(V b =0)703 (For example, basically overlapping I) d (V b =0)701)andI d '(V b =x)704 caused gamma 1 (I d ') is only slightly larger than gamma 2 (I d '), thus showing a significant improvement in the hump effect 302. Additionally, as Figure 7 As shown, in some embodiments, the voltage X2 can range from 0.5V to 5.0V, and the current Y2 can range from 1 nanoamp (nA) to 1 milliamp (mA), wherein the gate-source voltage V gs Shown on a linear scale, and the drain current I d Represented on a logarithmic scale.

[0045] In view of the reduced hump effect 302, a more accurate and precise reference voltage V can be generated by a reference voltage circuit 100 including an NGD 102 with a P+ region 410. ref .to this end, Figure 8 The exemplary temperature coefficient T of the NGD 102 with and without the gate inversion doped region (e.g., P+ region 410) shown in accordance with the present invention is illustrated. c Figure 800 shows the performance compared to the reference voltage. More specifically, Figure 8 It is shown at some reference temperatures T ref (For example, the reference voltage V at 25 degrees Celsius (°C) or some other temperature) ref Several measurement points and corresponding temperature coefficients T c (For example, expressed in parts per million per degree Celsius (ppm / °C), representing the reference voltage V) ref At reference temperature T ref The rate of change. Qualitatively, white test points unrelated to the use of inversion-doped regions are generally farther from the zero temperature coefficient T than shaded test points associated with the use of inversion-doped regions. c , indicating the reference voltage V ref The variability is greater relative to temperature. Furthermore, the white test points are more dispersed in both the vertical and horizontal directions compared to the shaded test points, indicating that without using an inversion-doped region (e.g., P+ region 410) in the NGD 102 of the reference voltage circuit 100, the reference voltage V... ref and temperature coefficient T c The variability is greater.

[0046] Given Figure 800, the measurement point distribution of NGD 102 with and without the implementation of the gate inversion doped region (e.g., P+ region 410) thus represents the median temperature coefficient T. c Smaller (e.g., close to zero), and reference temperature T ref The reference voltage V ref and the reference voltage V at that temperature ref Temperature coefficient T c Both have relatively small standard deviations. Therefore, using an inversion-doped region is expected to increase the reference voltage V provided by the reference voltage circuit 100. ref The accuracy and precision.

[0047] Additionally, while the use of an NGD 102 with an inversion-doped region (e.g., P+ region 410) is discussed herein with respect to a reference voltage circuit 100, in other embodiments such an NGD 102 may be employed outside the environment of the reference voltage circuit 100 to provide advantages related to reducing current leakage caused by the recessed features of the shallow trench isolation structure.

[0048] Figures 9A to 9F Cross-sectional views are shown of some embodiments of an IC device including an NGD 102 and a corresponding FGD 104, which incorporate gate inversion doped regions (e.g., P+ regions 410) at multiple manufacturing stages, according to the present invention. Although Figures 9A to 9F The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of actions within each series can be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0049] For example, Figure 9A A substrate 901 is shown providing doped (e.g., implanted or diffused) regions, including but not limited to deep N-well regions 408 on which P-well regions 206 are formed. (See diagram for reference.) Figures 9B to 9F As described, the left-handed P-well region 206 may form part of the FGD 104, while the right-handed P-well region 206 may form part of the NGD 102, as described above. Additionally, the substrate 901 may also include one or more N-well regions 402 that separate the respective P-well regions 206 from each other. In some embodiments, the respective regions of the substrate 901 may be formed by multiple implantation operations performed on relevant portions of the substrate 901. For example, in some embodiments, a deep N-well region 408 may be formed using implantation via the lower surface of the substrate 901, and the P-well regions 206 and N-well regions 402 may be formed using implantation via the upper surface of the substrate 901. In some embodiments, the substrate 901 may include silicon (Si) and / or other semiconductor materials.

[0050] Figure 9B A trench 902 is shown formed (e.g., photolithography and associated etching) in the upper surface of the P-well region 206 of substrate 901. In some embodiments, one or more trenches 902 may be formed within each P-well region 206 (e.g., adjacent to the N-well region 402). Furthermore, in some embodiments, each trench 902 may extend partially into its corresponding P-well region 206 (e.g., less than or equal to half). Additionally, as... Figure 4A and Figure 4B As shown, each trench 902 can be located on the lateral periphery of the upper surface of the corresponding P-trap region 206.

[0051] Figure 9C This illustrates the formation (e.g., deposition) of dielectric materials (e.g., silicon oxide (SiO2)). x Materials such as silicon dioxide (SiO2), or another oxide or dielectric material, can be used to create one or more dielectric structures (e.g., shallow trench isolation (STI) structures) 204. Therefore, the dielectric structure 204 can employ... Figure 9BThe trench 902 extends partially into the corresponding P-well region 206. Additionally, in some embodiments, each dielectric structure 204 may be located at the lateral periphery of the upper surface of the corresponding P-well region 206. Furthermore, in some embodiments, after depositing the dielectric material and after forming the dielectric structure 204, the upper surfaces of the P-well region 206, N-well region 402, and dielectric structure 204 may be planarized (e.g., using chemical mechanical planarization (CMP)).

[0052] Figure 9D This illustrates the formation (e.g., deposition) of a dielectric layer 208 on the upper surface (e.g., on top) of the P-well region 206, the N-well region 402, and the dielectric structure 204. In some embodiments, a single dielectric layer 208 may be formed on multiple P-well regions 206, such as... Figure 9D As shown below, the dielectric layer 208 may form the gate oxide (e.g., silicon oxide (SiO2)) for the gate structure of each transistor device associated with each P-well region 206. x (e.g., silicon dioxide (SiO2), or another oxide or dielectric material).

[0053] Figure 9E This illustrates the formation (e.g., deposition) of a conductive layer (e.g., polysilicon or another metal and / or conductive material) on a dielectric layer 208, followed by the formation (e.g., doping, such as by implantation or diffusion) of various P+ and N+ regions within the conductive layer to produce, for example, an N+ gate structure 202 (e.g., for NGD 102) and a P+ gate structure 910 (e.g., for FGD 104), as well as a P+ region 410 (e.g., for NGD 102) and an N+ region 912 (e.g., for FGD 104). As described above, the P+ region 410 can be used as an inversion doped or implanted region, and the N+ region 912 can be used to provide a self-aligned n-doped source-drain region for the FGD 104. Figure 9E (Not explicitly shown). In some embodiments, the n-type dopant used for the N+ gate structure 202 and the N+ region 912 may include arsenic (As), phosphorus (P), or another n-type dopant material. Furthermore, in some embodiments, the p-type dopant used for the P+ gate structure 910 and the P+ region 410 may include boron (B), boron trifluoride (BF3), or another p-type dopant material.

[0054] In some embodiments, assuming both p-type and n-type regions are used in both NGD 102 and FGD 104, the injection of P+ region 410 can be performed simultaneously with other P+ regions (e.g., the P+ gate structure 910 of FGD 104, or the P+ source-drain region of a pMOS transistor assembly not shown or discussed herein). Therefore, in some embodiments, P+ region 410 can be generated without adding any additional IC process steps.

[0055] Figure 9F This diagram illustrates the formation (e.g., photolithography and associated etching) of various trenches 914 (e.g., the region above the N-well region 402) to form the gate and associated dielectric (e.g., gate oxide) structures of NGD 102 and FGD 104. In some embodiments, the P+ gate structure 910 and N+ gate structure 202 are electrically connected together for use in a reference voltage circuit 100. In some embodiments, additional structures (e.g., additional dielectric layers, conductive (e.g., metal) vias, conductive (e.g., metal) layers, etc.) Figure 9F The formation of (not shown in the image) can occur after the formation of ditch 914.

[0056] Figure 9G Different cross-sectional views of FGD 104 according to the present invention are shown, such as Figure 9H As indicated by the dashed arrow. Furthermore, Figure 9H A plan view of FGD 104 is shown, indicating... Figure 9G The cross-section of the P+ gate structure 910 is shown. As illustrated, the N+ region 912 can be disposed along each upper edge of the P+ gate structure 910. In some embodiments, the N+ region 912 can be formed simultaneously with the first N+ source-drain region 404 and the second N+ source-drain region 406 (e.g., to facilitate the self-aligned formation of the first N+ source-drain region 404 and the second N+ source-drain region 406 of the FGD 104, as mentioned above). Furthermore, in some embodiments, such as... Figure 9G and Figure 9H As shown, the N+ region 912 can extend along the entire P+ gate structure 910, the first N+ source-drain region 404, and / or the second N+ source-drain region 406.

[0057] Figure 10 This invention illustrates a method 1000 for forming an IC device including an NGD 102 according to some embodiments of the present invention, wherein the NGD 102 includes... Figures 9A to 9FThe gate inversion doped (e.g., implanted) region (e.g., for reference voltage circuit 100). Although this and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that the scope of this invention is not limited to the shown order or actions. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0058] At action 1002, for example, a substrate (e.g., substrate 901) including a P-well region (e.g., P-well region 206) may be provided. Figure 9A Cross-sectional views are shown corresponding to some embodiments of action 1002.

[0059] At action 1004, at least one trench may be formed in the upper surface of the P-trap region (e.g., Figure 9B (Ditch 902). Figure 9B Cross-sectional views corresponding to some embodiments of action 1004 are shown.

[0060] At action 1006, a dielectric structure can be formed in the trench (e.g., Figure 9C The dielectric structure 204). As described above, in some embodiments, after the dielectric structure is formed, the dielectric structure and the P-well region can be planarized (e.g., by CMP). Figure 9C Cross-sectional views corresponding to some embodiments of action 1006 are shown.

[0061] At action 1008, a dielectric layer can be formed over the P-well region and the dielectric structure (e.g., Figure 9D (Dielectric layer 208). Figure 9D Cross-sectional views are shown for some embodiments corresponding to action 1008.

[0062] At operation 1010, an N+ gate structure can be formed over the dielectric layer (e.g., Figure 9E The N+ gate structure 202). Furthermore, at operation 1012, at least one P+ region can be formed in the N+ gate structure (e.g., Figure 9E The P+ region 410), wherein at least one P+ region may be located above the P-well region and the dielectric structure. Figure 9E Cross-sectional views corresponding to some embodiments of actions 1010 and 1012 are shown. In some embodiments, the formation of the dielectric layer, the N+ gate structure, and at least one P+ region may also involve selective removal of material, such as... Figure 9FAs shown, individual NGD 102s including inversion doped regions are formed, as described in detail above.

[0063] Some embodiments relate to an integrated circuit (IC) device. The device includes: a substrate including a P-well region and a dielectric structure, the dielectric structure being located at a surface of the substrate, extending downward into the substrate, and at a lateral perimeter of the P-well region; a dielectric layer located above the P-well region and laterally extending above the dielectric structure; and an N+ gate structure located above the dielectric layer and including at least one P+ region above the P-well region of the substrate and the dielectric structure.

[0064] In some embodiments, the N+ gate structure comprises an N+ polysilicon structure. In some embodiments, the dielectric layer comprises silicon oxide (SiO2). x The substrate comprises at least one of silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), or undoped silicate glass (USG). In some embodiments, the dielectric structure is disposed integrally along the lateral perimeter of the P-well region. In some embodiments, the substrate further comprises: a first N+ source-drain region located near a first end of the dielectric layer, and a second N+ source-drain region located near a second end of the dielectric layer opposite to the first end. In some embodiments, at least one P+ region comprises: a first P+ region extending above a middle portion of a first side edge of the dielectric structure, the first side edge being perpendicular to the first end and the second end of the dielectric layer; and a second P+ region extending above a middle portion of a second side edge of the dielectric structure, the second side edge being opposite to the first side edge. In some embodiments, the middle portion of the first side edge of the dielectric structure includes at least 75% of the length of the first side edge; and the middle portion of the second side edge of the dielectric structure includes at least 75% of the length of the second side edge. In some embodiments, the first side edge of the dielectric structure faces the central portion of the P-well region of the substrate; and the second side edge of the dielectric structure faces the first side edge of the dielectric structure. In some embodiments, at least one P+ region is completely laterally surrounded by the N+ gate structure. In some embodiments, at least one P+ region extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

[0065] Some embodiments relate to another IC device. The device includes a reference voltage circuit comprising a flip-gate assembly (FGD) and a normal gate assembly (NGD). The FGD includes a first P-well region in a substrate; a first N+ source-drain region and a second N+ source-drain region located within the first P-well region; and a P+ gate structure located above the first P-well region and between the first N+ source-drain region and the second N+ source-drain region in a plan view of the IC device. The P+ gate structure includes a first N+ region aligned side-by-side with the first N+ source-drain region in a plan view and a second N+ region aligned side-by-side with the second N+ source-drain region in a plan view. The NGD includes a second P-well region located in a substrate; a third N+ source-drain region and a fourth N+ source-drain region located in the second P-well region; and an N+ gate structure located above the second P-well region and between the third N+ source-drain region and the fourth N+ source-drain region in a plan view, the N+ gate structure including at least one P+ region extending between the third N+ source-drain region and the fourth N+ source-drain region in a plan view, wherein the N+ gate structure is electrically connected to the P+ gate structure.

[0066] In some embodiments, the reference voltage circuit further includes: a first current source coupling a first voltage terminal to the drain terminal of the FGD; and a second current source coupling the source terminal of the NGD to the second voltage terminal, wherein the source terminal provides a reference voltage. In some embodiments, at least one P+ region is located above a second P-well region disposed in the substrate and a dielectric structure, the dielectric structure being disposed on the surface of the substrate, extending downward into the substrate, and located at the lateral perimeter of the P+ well region. In some embodiments, the NGD further includes: a dielectric layer located between the second P-well region and the N+ gate structure; wherein a third N+ source-drain region is located near a first end of the dielectric layer; wherein a fourth N+ source-drain region is located near a second end of the dielectric layer opposite to the first end; and wherein at least one P+ region includes: a first P+ region extending above a middle portion of a first side edge of the dielectric structure, the first side edge being perpendicular to the first and second ends of the dielectric layer; and a second P+ region extending above a middle portion of a second side edge of the dielectric structure, the second side edge being opposite to the first side edge. In some embodiments, the first side edge of the dielectric structure faces the central portion of the second P-well region of the substrate; and the second side edge of the dielectric structure faces the first side edge of the dielectric structure. In some embodiments, at least one P+ region is completely laterally surrounded by the N+ gate structure and extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

[0067] Some embodiments relate to a method. The method includes: providing a substrate including a P-well region; forming a trench in the top surface of the P-well region; forming a dielectric structure in the trench; forming a dielectric layer over the P-well region and the dielectric structure; forming an N+ gate structure over the dielectric layer; and implanting at least one P+ region in the N+ gate structure, the at least one P+ region being located over the P-well region and the dielectric structure.

[0068] In some embodiments, the method further includes: implanting a first N+ source-drain region in a substrate near a first end of the dielectric layer; and implanting a second N+ source-drain region in a substrate near a second end of the dielectric layer opposite to the first end, wherein implanting at least one P+ region includes: implanting the first P+ region to extend over a middle portion of a first side edge of the dielectric structure between the first and second ends of the dielectric layer; and implanting the second P+ region to extend over a middle portion of a second side edge of the dielectric structure opposite to the first side edge. In some embodiments, the method further includes implanting a P+ region of a gate structure separate from the N+ gate structure while implanting at least one P+ region in the N+ gate structure. In some embodiments, each of the first P+ region and the second P+ region is completely laterally surrounded by the N+ gate structure and extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

[0069] It should be understood that in this written description and the appended claims, the terms "first," "second," "third," etc., are merely general identifiers used for convenience in describing and distinguishing different components of a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the components, and are not intended to describe different components in the illustrated embodiments and / or corresponding components in embodiments not shown. For example, a "first dielectric layer" described in conjunction with one figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in embodiments not shown.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. An integrated circuit device, characterized in that, include: The invention includes a substrate and a dielectric structure comprising a P-well region, wherein the dielectric structure is located on the surface of the substrate, extends downward into the substrate, and is located at the lateral perimeter of the P-well region; A dielectric layer is located above the P-well region and extends laterally above the dielectric structure; as well as An N+ gate structure is located above the dielectric layer and includes the P-well region located on the substrate and at least one P+ region above the dielectric structure.

2. The integrated circuit device according to claim 1, characterized in that, The dielectric structure is integrally disposed along the lateral perimeter of the P-well region.

3. The integrated circuit device according to claim 1, characterized in that, The substrate further includes: The first N+ source-drain region is located near the first end of the dielectric layer; and The second N+ source-drain region is located near the second end of the dielectric layer opposite to the first end.

4. The integrated circuit device according to claim 3, characterized in that, The at least one P+ region includes: A first P+ region extends above the middle portion of a first side edge of the dielectric structure, the first side edge being perpendicular to the first end and the second end of the dielectric layer; and The second P+ region extends above the middle portion of the second side edge of the dielectric structure, the second side edge being opposite to the first side edge.

5. The integrated circuit device according to claim 1, characterized in that, The at least one P+ region is completely surrounded laterally by the N+ gate structure.

6. The integrated circuit device according to claim 1, characterized in that, The at least one P+ region extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

7. An integrated circuit device, characterized in that, include: Reference voltage circuit, including: A flip-gate assembly, including: The first P-well region is located in the substrate; The first N+ source-drain region and the second N+ source-drain region are located within the first P-well region; and A P+ gate structure is located above the first P-well region and, in the plan view of the integrated circuit device, between the first N+ source-drain region and the second N+ source-drain region. The P+ gate structure includes a first N+ region aligned side-by-side with the first N+ source-drain region in the plan view and a second N+ region aligned side-by-side with the second N+ source-drain region in the plan view. Regular gate components include: The second P-well region is located in the substrate; The third N+ source-drain region and the fourth N+ source-drain region are located in the second P-well region; and An N+ gate structure is located above the second P-well region and between the third N+ source-drain region and the fourth N+ source-drain region in the plan view. The N+ gate structure includes at least one P+ region extending between the third N+ source-drain region and the fourth N+ source-drain region in the plan view, wherein the N+ gate structure is electrically connected to the P+ gate structure.

8. The integrated circuit device according to claim 7, characterized in that, The reference voltage circuit also includes: A first current source couples a first voltage terminal to the drain terminal of the flip-gate assembly; and A second current source couples the source terminal of the normal gate assembly to a second voltage terminal, wherein the source terminal provides a reference voltage.

9. The integrated circuit device according to claim 7, characterized in that, The at least one P+ region is located above the second P-well region and the dielectric structure disposed in the substrate. The dielectric structure is disposed on the surface of the substrate, extends downward into the substrate, and is located at the lateral perimeter of the P+ well region.

10. The integrated circuit device according to claim 9, characterized in that, The regular gate assembly also includes: A dielectric layer is located between the second P-well region and the N+ gate structure; The third N+ source-drain region is located near the first end of the dielectric layer; The fourth N+ source-drain region is located near the second end of the dielectric layer opposite to the first end; and The at least one P+ region includes: A first P+ region extends above the middle portion of a first side edge of the dielectric structure, the first side edge being perpendicular to the first end and the second end of the dielectric layer; and The second P+ region extends above the middle portion of the second side edge of the dielectric structure, the second side edge being opposite to the first side edge.

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