Electrostatic protection device
Patent Information
- Application Number
- CN202522309204.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-10-13
- Estimated Expiration
- 2035-10-30
AI Technical Summary
[0003]在传统设计中，芯片的高压引脚会经常使用低压GGNMOS（接地NMOS管）和低压GDPMOS（栅极到漏极PMOS管）堆叠的结构作为ESD防护结构，此种结构可以通过调整堆叠的数量来调节触发电压等参数，但是大量的堆叠会使得面积偏大，单位面积的ESD防护能力会比较低
[0035]本申请提供的静电防护器件，在器件衬底中设置了高压阱区，并将包含有串联连接的P沟道场效应晶体管结构和N沟道场效应晶体管结构的泄放单元（即低压GGNMOS和低压GDPMOS的堆叠结构）设置在该高压阱区中，即将低压GGNMOS和低压GDPMOS的堆叠结构做成了iso结构，当器件触发后，除器件本身的寄生三极管所形成的电流泄放路径（即由寄生PNP和寄生NPN串联所形成的ESD电流泄放路径）外，本申请还能够在器件中额外形成PNPN型的SCR路径作为器件触发后的电流泄放路径，因此相较于传统方案中仅具有单一的ESD电流泄放路径的器件而言，本申请中的静电防护器件的电流泄放能力更强，同样是采用堆叠的结构，但本申请能够在确保触发电压不变的情况下，利用更小的面积来实现相同的静电防护能力，有效的提高了器件单位面积的静电防护能力，且结构简单，与现有工艺的兼容性强，制备成本较低。
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Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuits, specifically to an electrostatic discharge (ESD) protection device. Background Technology
[0002] ESD (Electrostatic Discharge) refers to the phenomenon of charge transfer and energy release caused by objects with different electrostatic potentials approaching or coming into direct contact. It commonly occurs during the production, assembly, testing, storage, and handling of integrated circuits. When the accumulated electrostatic charge on the human body, instruments, equipment, or components is large, it can generate transient currents of tens of amperes and voltage surges of kilovolts, damaging electronic components or systems. Therefore, the industry commonly integrates ESD protection devices at chip ports.
[0003] In traditional designs, high-voltage pins of chips often use a stacked structure of low-voltage GGNMOS (grounded NMOS transistor) and low-voltage GDPMOS (gate-to-drain PMOS transistor) as an ESD protection structure. This structure can adjust parameters such as trigger voltage by adjusting the number of stacks. However, a large number of stacks will result in a large area and a relatively low ESD protection capability per unit area.
[0004] Therefore, improving the ESD protection capability per unit area of stacked structures has become particularly important. Utility Model Content
[0005] In view of the above-mentioned technical problems, the purpose of this application is to provide an electrostatic discharge (ESD) protection device in which a stacked structure including low-voltage GGNMOS and low-voltage GDPMOS is disposed in a high-voltage well region, thereby forming an additional parasitic SCR path in the ESD protection device for ESD protection, effectively improving the ESD protection capability per unit area of the device while ensuring that the trigger voltage remains unchanged.
[0006] According to a first aspect of this application, an electrostatic discharge protection device is provided, characterized in that it comprises:
[0007] Substrate;
[0008] High-voltage well region located on the substrate;
[0009] The discharge unit located within the high-voltage trap region includes a P-channel field-effect transistor structure and an N-channel field-effect transistor structure connected in series between the anode and cathode of the electrostatic protection device.
[0010] Optionally, the high-voltage trap region is also connected to the anode of the electrostatic protection device.
[0011] Optionally, the doping type of the high-voltage trap region is N-type ion doping.
[0012] Optionally, the number of discharge units located in the high-voltage trap area is M, and the M discharge units are connected in series between the anode and cathode of the electrostatic protection device, where M is a positive integer greater than or equal to 1.
[0013] Optionally, the number of high-voltage well regions located on the substrate is K, and each high-voltage well region is provided with a discharge unit, where K is a positive integer greater than or equal to 1.
[0014] Optionally, the discharge unit further includes:
[0015] At least one P-channel field-effect transistor structure is connected in series between the P-channel field-effect transistor structure and the N-channel field-effect transistor structure.
[0016] Optionally, the P-channel field-effect transistor structure includes:
[0017] N-type well region;
[0018] The first gate structure located on the upper surface of the N-type well region;
[0019] The first N+ injection region, the first P+ injection region, and the second P+ injection region are located within the N-type well region, with the first P+ injection region and the second P+ injection region located on both sides of the first gate structure.
[0020] The first N+ injection region, the first gate structure, and the first P+ injection region are connected together to serve as the first current transmission terminal of the P-channel field-effect transistor structure, and the second P+ injection region serves as the second current transmission terminal of the P-channel field-effect transistor structure; the first current transmission terminal is the current input terminal, and the second current transmission terminal is the current output terminal.
[0021] Optionally, the first N+ injection region and the first P+ injection region are isolated via a first isolation structure.
[0022] Optionally, the N-channel field-effect transistor structure includes:
[0023] P-type well region;
[0024] The second gate structure is located on the P-type well region;
[0025] The second N+ injection region, the third N+ injection region, and the third P+ injection region are located within the P-type well region, with the second N+ injection region and the third N+ injection region located on both sides of the second gate structure;
[0026] The second N+ injection region serves as the first current transmission terminal of the N-channel field-effect transistor structure, and the third N+ injection region, the second gate structure, and the third P+ injection region serve as the second current transmission terminal of the N-channel field-effect transistor structure; the first current transmission terminal is the current input terminal, and the second current transmission terminal is the current output terminal.
[0027] Optionally, the third N+ injection region and the third P+ injection region are isolated via a second isolation structure.
[0028] Optionally, the well regions of the P-channel field-effect transistor structure and the N-channel field-effect transistor structure are spaced apart by a certain distance or are adjacent to each other.
[0029] Optionally, the electrostatic discharge protection device further includes:
[0030] The third isolation structure isolates the two ends of two adjacent field-effect transistor structures that are connected to each other.
[0031] Optionally, the first isolation structure includes one of a field oxygen isolation structure and a shallow trench isolation structure.
[0032] Optionally, the second isolation structure includes one of a field oxygen isolation structure and a shallow trench isolation structure.
[0033] Optionally, the third isolation structure includes one of a field oxygen isolation structure and a shallow trench isolation structure.
[0034] The beneficial effects of this application include at least the following:
[0035] The electrostatic discharge (ESD) protection device provided in this application has a high-voltage well region in the device substrate, and a discharge unit (i.e., a stacked structure of low-voltage GGNMOS and low-voltage GDPMOS) containing a series-connected P-channel field-effect transistor structure and an N-channel field-effect transistor structure is placed in the high-voltage well region. That is, the stacked structure of low-voltage GGNMOS and low-voltage GDPMOS is made into an iso structure. When the device is triggered, in addition to the current discharge path formed by the parasitic transistor of the device itself (i.e., the ESD current discharge path formed by the series connection of parasitic PNP and parasitic NPN), this application can also form an additional PNPN type SCR path in the device as the current discharge path after the device is triggered. Therefore, compared with the device with only a single ESD current discharge path in the traditional solution, the ESD protection device in this application has a stronger current discharge capability. Although it also adopts a stacked structure, this application can achieve the same ESD protection capability with a smaller area while ensuring that the trigger voltage remains unchanged. It effectively improves the ESD protection capability per unit area of the device, and the structure is simple, highly compatible with existing processes, and has a low manufacturing cost.
[0036] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description
[0037] Figure 1 A cross-sectional view of an electrostatic discharge protection device provided according to a first embodiment of this application is shown;
[0038] Figure 2 Show Figure 1 Equivalent circuit diagram of electrostatic discharge protection devices;
[0039] Figure 3 A cross-sectional view of an electrostatic discharge protection device according to a second embodiment of this application is shown;
[0040] Figure 4 Show Figure 3 Equivalent circuit diagram of electrostatic discharge protection devices. Detailed Implementation
[0041] The preferred embodiments of this disclosure are described in detail below with reference to the accompanying drawings, but this disclosure is not limited to these embodiments. This disclosure covers any alternatives, modifications, equivalent methods, and solutions made within the spirit and scope of this disclosure.
[0042] In order to provide the public with a thorough understanding of this disclosure, specific details are described in detail in the following preferred embodiments of this disclosure, but those skilled in the art can fully understand this disclosure without these details.
[0043] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.
[0044] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0045] In the description of this application, words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. The term "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.
[0046] When describing the structure of a device in this disclosure, when referring to a layer or region as being "above" or "over" another layer or region, it may mean being directly above another layer or region, or including other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.
[0047] It should be understood that when a component or layer is referred to as "on," "connected to," or "coupled to" other components or layers, it may be directly on, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion.
[0048] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the application.
[0049] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.
[0050] Combination Figure 1 and Figure 2 As shown, the electrostatic discharge protection device 100 provided in this application embodiment includes: a substrate 110, a high-voltage trap region 120 located on the substrate 110, and a discharge unit located in the high-voltage trap region 120. The discharge unit includes a P-channel field-effect transistor structure 130 and an N-channel field-effect transistor structure 140 connected in series between the anode and cathode of the electrostatic discharge protection device 100.
[0051] Substrate 110 is a P-type substrate.
[0052] The high-voltage well region 120 is doped with N-type ions and is connected to the anode of the electrostatic discharge protection device 100.
[0053] The P-channel field-effect transistor structure 130 includes: an N-type well region 131, a first gate structure 135 located on the upper surface of the N-type well region 131, and a first N+ injection region 132, a first P+ injection region 133, and a second P+ injection region 134 located within the N-type well region 131. The first P+ injection region 133 and the second P+ injection region 134 are located on both sides of the first gate structure 135.
[0054] In some embodiments, the first N+ injection region 132 and the first P+ injection region 133 are isolated via a first isolation structure 136. In other embodiments, the first N+ injection region 132 and the first P+ injection region 133 are disposed adjacent to each other.
[0055] The N-channel field-effect transistor structure 140 includes: a P-type well region 141, a second gate structure 145 located on the P-type well region 141, and a second N+ injection region 142, a third N+ injection region 143 and a third P+ injection region 144 located within the P-type well region 141, wherein the second N+ injection region 142 and the third N+ injection region 143 are located on both sides of the second gate structure 145.
[0056] In some embodiments, the third N+ injection region 143 and the third P+ injection region 144 are isolated via a second isolation structure 146. In other embodiments, the third N+ injection region 143 and the third P+ injection region 144 are disposed adjacent to each other.
[0057] Optionally, the first isolation structure 136 and the second isolation structure 146 include one of a field oxygen isolation structure and a shallow trench isolation structure.
[0058] In the P-channel field-effect transistor structure 130, the first N+ injection region 132, the first gate structure 135, and the first P+ injection region 133 are connected together (electrically; the specific fabrication process can adopt existing structures) as the first current transmission terminal (current input terminal) of the P-channel field-effect transistor structure 130, and the second P+ injection region 134 serves as the second current transmission terminal (current output terminal) of the P-channel field-effect transistor structure 130. Similarly, in the N-channel field-effect transistor structure 140, the second N+ injection region 142 serves as the first current transmission terminal (current input terminal) of the N-channel field-effect transistor structure 140, and the third N+ injection region 143, the second gate structure 145, and the third P+ injection region 144 are connected together as the second current transmission terminal (current output terminal) of the N-channel field-effect transistor structure 140. Figure 1 and Figure 2 The first current transmission terminal of the P-channel field-effect transistor structure 130 is connected to the anode of the electrostatic discharge protection device 100, the second current transmission terminal of the P-channel field-effect transistor structure 130 is connected to the first current transmission terminal of the N-channel field-effect transistor structure 140, and the second current transmission terminal of the N-channel field-effect transistor structure 140 is connected to the cathode of the electrostatic discharge protection device 100. At this time, the P-channel field-effect transistor structure 130 is equivalent to a GDPMOS structure, and the N-channel field-effect transistor structure 140 is equivalent to a GGNMOS structure.
[0059] In this embodiment, the electrostatic discharge protection device 100 further includes a third isolation structure, through which the two ends of two adjacent field-effect transistor structures connected to each other are isolated. For example, Figure 1 In the P-channel field-effect transistor structure 130, the current output terminal (i.e., the second P+ injection region 134) and the current input terminal (i.e., the second N+ injection region 142) of the N-channel field-effect transistor structure 140 are isolated by the third isolation structure 150.
[0060] Preferably, the N-type well region 131 in the P-channel field-effect transistor structure 130 and the P-type well region 141 in the N-channel field-effect transistor structure 140 are spaced apart by a certain distance. In this case, the N-type well region 131 in the P-channel field-effect transistor structure 130 and the P-type well region 141 in the N-channel field-effect transistor structure 140 are separated by a high-voltage well region 120. Figure 1This enables the device to have good voltage withstand capability and process applicability. Of course, in other embodiments, the N-type well region 131 in the P-channel field-effect transistor structure 130 and the P-type well region 141 in the N-channel field-effect transistor structure 140 can also be arranged adjacently (not shown).
[0061] Optionally, the third isolation structure 150 includes one of a field oxygen isolation structure and a shallow trench isolation structure.
[0062] Combination Figure 1 and Figure 2 In this embodiment, it is equivalent to setting a stacked series structure of P-channel field-effect transistor structure 130 and N-channel field-effect transistor structure 140 in the electrostatic discharge protection device 100, and the P-channel field-effect transistor structure 130 is located on the high side of the N-channel field-effect transistor structure 140. That is, the GDPMOS structure equivalent to the P-channel field-effect transistor structure 130 and the GGNMOS structure equivalent to the N-channel field-effect transistor structure 140 have a "P on top, N on bottom" positional relationship in the electrostatic discharge protection device 100. Therefore, the trigger voltage of the electrostatic discharge protection device 100 is still the sum of the breakdown voltages of the P-channel field-effect transistor structure 130 and the N-channel field-effect transistor structure 140, that is, ensuring that the trigger voltage of the device remains unchanged.
[0063] Meanwhile, since both the P-channel field-effect transistor structure 130 and the N-channel field-effect transistor structure 140 are located within the N-type high-voltage well region 120, an iso structure (i.e., the P-type well region 141 is separated from the substrate 110) can be formed in the electrostatic discharge protection device 100 based on the N-type high-voltage well region 120 and the N-channel field-effect transistor structure 140. Furthermore, based on the shared use of the N-type high-voltage well region 120 (i.e., the tub) by the P-channel field-effect transistor structure 130 and the N-channel field-effect transistor structure 140, when the device is triggered, in addition to the electrostatic discharge protection device 100… In addition to forming a current discharge path between the anode and cathode based on the parasitic transistor of the device itself (e.g., an ESD current discharge path formed by the series connection of parasitic PNP and parasitic NPN in the device), a parasitic PNPN type SCR path based on "first P+ injection region 133 → N-type well region 131 → N-type high voltage well region 120 → P-type well region 141 → third N+ injection region 143" can also be formed between the anode and cathode of the electrostatic protection device 100. This SCR path is turned on and performs ESD current discharge after the electrostatic protection device 100 is triggered. It is understood that, since this application adds an additional ESD current discharge path in the electrostatic discharge device 100, the ESD current discharge capability of the electrostatic discharge device 100 disclosed in this application is stronger than that of traditional devices with only a single ESD current discharge path (i.e., an ESD current discharge path formed by parasitic PNP and parasitic NPN connected in series). When achieving the same size ESD current discharge, the device size of the electrostatic discharge device disclosed in this application is smaller, effectively improving the ESD protection capability per unit area of the device.
[0064] Figure 1 The diagram illustrates an example in which an electrostatic discharge (ESD) protection device 100 includes a high-voltage trap region 120, within which a discharge unit is provided, and which contains a set of P-channel field-effect transistor structures 130 and N-channel field-effect transistor structures 140 stacked in series. It can then be understood that... Figure 1 In this context, the trigger voltage of the electrostatic discharge (ESD) protection device 100 is equal to the sum of the breakdown voltages of the P-channel field-effect transistor structure 130 and the N-channel field-effect transistor structure 140. However, in... Figure 1 Based on the scheme shown, the scheme of this application can be further modified as follows to increase the trigger voltage of the electrostatic discharge protection device:
[0065] In some embodiments, at least one additional P-channel field-effect transistor structure may be provided in the discharge unit, which is connected in series between the P-channel field-effect transistor structure and the N-channel field-effect transistor structure.
[0066] In some embodiments, the number of discharge units located in the high-voltage trap region 120 can be set to M, and the M discharge units are connected in series between the anode and cathode of the electrostatic protection device 100, where M is a positive integer greater than or equal to 1.
[0067] In some embodiments, the number of high-voltage well regions on the substrate is K, and each high-voltage well region is provided with a discharge unit, where K is a positive integer greater than or equal to 1. Figure 3 and Figure 4 The diagram shows the cross-sectional structure and equivalent circuit diagram of the electrostatic discharge (ESD) protection device when K equals 2. Figure 3 and Figure 4 The electrostatic discharge (ESD) protection device 200 shown includes a substrate 210, a first high-voltage well region 221 and a second high-voltage well region 222 located on the substrate 210. The first high-voltage well region 221 has a discharge unit composed of a P-channel field-effect transistor structure 230 and an N-channel field-effect transistor structure 240. The second high-voltage well region 222 has a discharge unit composed of a P-channel field-effect transistor structure 250 and an N-channel field-effect transistor structure 260. The P-channel field-effect transistor structure 230, the N-channel field-effect transistor structure 240, the P-channel field-effect transistor structure 250 and the N-channel field-effect transistor structure 260 are connected in series between the anode and the cathode of the ESD protection device 200. Meanwhile, the first high-voltage well region 221 (i.e., tub1) shared by the P-channel field-effect transistor structure 230 and the N-channel field-effect transistor structure 240 is connected to the anode of the electrostatic discharge protection device 200, and the second high-voltage well region 222 (i.e., tub2) shared by the P-channel field-effect transistor structure 250 and the N-channel field-effect transistor structure 260 is connected to the anode (i.e., source) of the P-channel field-effect transistor structure 250. The device structure when K is greater than 2 can be deduced by analogy.
[0068] Of course, any combination of the above embodiments is also possible.
[0069] In summary, the electrostatic discharge (ESD) protection device provided in this application has a high-voltage well region in the device substrate, and a discharge unit (i.e., a stacked structure of low-voltage GGNMOS and low-voltage GDPMOS) containing a series-connected P-channel field-effect transistor structure and an N-channel field-effect transistor structure is placed in this high-voltage well region. That is, the stacked structure of low-voltage GGNMOS and low-voltage GDPMOS is made into an iso structure. When the device is triggered, in addition to the current discharge path formed by the parasitic transistor of the device itself (i.e., the ESD current discharge path formed by the series connection of parasitic PNP and parasitic NPN), this application can also form an additional PNPN type SCR path in the device as the current discharge path after the device is triggered. Therefore, compared with the device with only a single ESD current discharge path in the traditional solution, the ESD protection device in this application has a stronger current discharge capability. Although it also adopts a stacked structure, this application can achieve the same ESD protection capability with a smaller area while ensuring that the trigger voltage remains unchanged, effectively improving the ESD protection capability per unit area of the device. Moreover, the structure is simple, has strong compatibility with existing processes, and has a low manufacturing cost.
[0070] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. An electrostatic discharge protection device, characterized in that, include: Substrate; High-voltage well region located on the substrate; The discharge unit located within the high-voltage trap region includes a P-channel field-effect transistor structure and an N-channel field-effect transistor structure connected in series between the anode and cathode of the electrostatic protection device.
2. The electrostatic discharge protection device according to claim 1, wherein, The high-voltage trap region is also connected to the anode of the electrostatic protection device.
3. The electrostatic discharge protection device according to claim 1, wherein, The high-pressure well region is doped with N-type ions.
4. The electrostatic discharge protection device according to claim 1, wherein, The number of discharge units located in the high-voltage trap area is M. These M discharge units are connected in series between the anode and cathode of the electrostatic protection device, where M is a positive integer greater than or equal to 1.
5. The electrostatic discharge protection device according to claim 1, wherein, The number of high-voltage well regions located on the substrate is K, and each high-voltage well region is provided with a discharge unit, where K is a positive integer greater than or equal to 1.
6. The electrostatic discharge protection device according to any one of claims 1-5, wherein, The venting unit also includes: At least one P-channel field-effect transistor structure is connected in series between the P-channel field-effect transistor structure and the N-channel field-effect transistor structure.
7. The electrostatic discharge protection device according to claim 1, wherein, The P-channel field-effect transistor structure includes: N-type well region; The first gate structure located on the upper surface of the N-type well region; The first N+ injection region, the first P+ injection region, and the second P+ injection region are located within the N-type well region, with the first P+ injection region and the second P+ injection region located on both sides of the first gate structure. The first N+ injection region, the first gate structure, and the first P+ injection region are connected together to serve as the first current transmission terminal of the P-channel field-effect transistor structure, and the second P+ injection region serves as the second current transmission terminal of the P-channel field-effect transistor structure; the first current transmission terminal is the current input terminal, and the second current transmission terminal is the current output terminal.
8. The electrostatic discharge protection device according to claim 7, wherein, The first N+ injection region and the first P+ injection region are isolated by a first isolation structure.
9. The electrostatic discharge protection device according to claim 1, wherein, The N-channel field-effect transistor structure includes: P-type well region; The second gate structure is located on the P-type well region; The second N+ injection region, the third N+ injection region, and the third P+ injection region are located within the P-type well region, with the second N+ injection region and the third N+ injection region located on both sides of the second gate structure; The second N+ injection region serves as the first current transmission terminal of the N-channel field-effect transistor structure. The third N+ injection region, the second gate structure, and the third P+ injection region are connected together to serve as the second current transmission terminal of the N-channel field-effect transistor structure. The first current transmission terminal is the current input terminal, and the second current transmission terminal is the current output terminal.
10. The electrostatic discharge protection device according to claim 9, wherein, The third N+ injection region and the third P+ injection region are isolated via a second isolation structure.
11. The electrostatic discharge protection device according to claim 1, wherein, The well regions of the P-channel field-effect transistor structure and the N-channel field-effect transistor structure are spaced apart by a certain distance or are adjacent to each other.
12. The electrostatic discharge protection device according to claim 11, wherein, The electrostatic protection device also includes: The third isolation structure isolates the two ends of two adjacent field-effect transistor structures that are connected to each other.