A photovoltaic cell and photovoltaic module

Abstract

The utility model relates to crystalline silicon solar cell technical field discloses a photovoltaic cell and photovoltaic module. The photovoltaic cell includes silicon wafer and the local area doped silicon quantum dot structure of being equipped with at the back of silicon wafer and being spaced apart from each other distribution, and the local area doped silicon quantum dot structure is only arranged in the non-interval area of the back surface nonmetallization area of silicon wafer, each local area doped silicon quantum dot structure includes insulating tunneling area and the doped silicon quantum dot area of being equipped with at insulating tunneling area back surface, and the doped silicon quantum dot area includes m-1 doped silicon quantum dot layer and m-1 insulating layer, and m is the integer of 3-10, and doped silicon quantum dot layer and insulating layer are alternately arranged in proper order, and the interval distribution has a plurality of doped silicon quantum dots in doped silicon quantum dot layer. The photovoltaic cell can effectively avoid the risk of the increase of series resistance, the poor contact, the difficulty of carrier to cross the insulating material to form effective carrier and so on caused by the multilayer silicon quantum dot structure of prior art, and further promotes the light absorption capacity and double side rate of cell back surface.

Description

Technical Field

[0001] This utility model relates to the field of crystalline silicon solar cell technology, specifically to a photovoltaic cell and a photovoltaic module. Background Technology

[0002] With the increasing popularity of bifacial photovoltaic (PV) modules (i.e., PV modules that can receive sunlight and generate electricity on both the front and back), the bifaciality (the ratio of the power generation capacity of the back cell to that of the front cell) is gradually gaining attention. Currently, most solar modules (i.e., PV modules) are bifacial, meaning both the front and back are translucent. The back of the module can receive reflected light from the ground to generate electricity. Generally, the reflectivity of the light input on the back of the module varies depending on the installation angle and the environment; for example, it's about 20% on grass, about 45% on concrete, and about 90% on snow. Considering the shading caused by the installation angle, the light input on the back is generally considered to be 10% of that on the front.

[0003] Bifaciality is a measure of the ratio of power generation capacity of the front and back sides of a solar cell: Bifaciality = (Back side photoelectric conversion efficiency / Front side photoelectric conversion efficiency) × 100%. The bifaciality of a typical TOPCon (tunneling oxide passivated contact) cell is approximately 83% (the bifaciality of photovoltaic modules can reach 73%). To improve the bifaciality of photovoltaic cells (or modules), taking TOPCon cells as an example, common methods include: reducing the thickness of the back poly layer (i.e., the polycrystalline silicon layer), increasing the back doping concentration, and optimizing the design of the back anti-reflection passivation layer. The purpose of these methods is to reduce light consumption. However, this approach only achieves "reduction" and not "increase" the light source. This is because the bandgap of monocrystalline silicon (commonly used as the silicon substrate material for photovoltaic cells) is fixed at room temperature, Eg = 1.12 eV, meaning the spectral absorption range of monocrystalline silicon is fixed. Therefore, using only monocrystalline silicon as the light-absorbing material clearly cannot achieve "increase" the light source.

[0004] Quantum dots (QDs) are objects with dimensions all below 100 nm in all three dimensions, resembling tiny dots. The movement of electrons within them is restricted in all directions, resulting in a particularly significant quantum confinement effect. This effect causes the band gap to increase as the quantum dot size decreases, allowing quantum dot materials to absorb a broad spectrum of sunlight. Even smaller quantum dot sizes are located in strongly confined regions, readily forming excitons and generating exciton absorption bands; therefore, the absorption coefficient increases with decreasing particle size. The blue shift of the exciton's lowest energy also expands the light absorption range. Therefore, introducing silicon quantum dots (Si QDs) into all-silicon solar cells expands the light absorption range and increases the absorption coefficient, enabling the solar cell to absorb a wider spectrum of sunlight, effectively "opening up" the light spectrum.

[0005] For example, CN117878178A discloses a crystalline silicon heterojunction solar cell structure and its fabrication method, which prepares a multilayer silicon quantum dot structure on the front surface (i.e., the front side) of the heterojunction cell to broaden the light absorption range of the cell and thus improve the cell efficiency.

[0006] It should be noted that the tiny size of QDs means they cannot exist independently and must be embedded in other materials. Common embedding materials include SiO2, SiC, and SiNx. However, these materials are all insulating, and directly covering the battery surface with them presents the following problems:

[0007] 1) Increasing the series resistance of the battery is currently addressed by using metal electrode paste to burn through the battery's insulating layer during screen printing and sintering to form a contact. 2) This method further increases the difficulty of sintering and the risk of poor contact. 3) In addition, the photons captured by QDs, forming excitons and charge carriers, need to pass through the insulating layer surrounding their surface to form effective charge carriers. However, in the battery of CN117878178A, it is difficult for the charge carriers formed by the silicon quantum dots capturing photons in the multilayer silicon quantum dot structure to pass through the entire insulating layer on the front side (such as the first amorphous silicon carbide layer and the second amorphous silicon carbide layer), making it difficult to form effective charge carriers, which in turn adversely affects the battery's light absorption capacity and bifaciality. Therefore, the QDs battery prepared by CN117878178A still has significant problems, and directly preparing silicon quantum dots on the front side of the battery carries a high risk. Utility Model Content

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a photovoltaic cell and a photovoltaic module.

[0009] Based on this, the present invention discloses a photovoltaic cell, comprising: a silicon wafer and a plurality of locally doped silicon quantum dot structures disposed on the back side of the silicon wafer at intervals; the back side of the silicon wafer is divided into a back metallized region and a back non-metallized region, and the back non-metallized region has a plurality of spaced regions that are separated from each other; the locally doped silicon quantum dot structures are disposed in the non-spaced regions of the back non-metallized region.

[0010] Each of the localized doped silicon quantum dot structures includes an insulating tunneling region and a doped silicon quantum dot region disposed on the back side of the insulating tunneling region; the doped silicon quantum dot region includes m-1 doped silicon quantum dot layers and m-1 insulating layers, where m is an integer from 3 to 10; the doped silicon quantum dot layers and the insulating layers are alternately arranged in sequence, such that the doped silicon quantum dot layers are disposed on the back side of the insulating tunneling region; a plurality of doped silicon quantum dots are distributed at intervals within the doped silicon quantum dot layers.

[0011] Preferably, the doping type of the locally doped silicon quantum dot structure is n-type, and the doped silicon quantum dots are n-type silicon quantum dots.

[0012] More preferably, the area of ​​the interval region is 15×15nm to 30×30nm, and the distance between the center points of two adjacent interval regions is 20-50nm.

[0013] More preferably, the thickness of the insulating tunneling region is 1-5 nm, and the material of the insulating tunneling region is silicon oxide or silicon carbide.

[0014] More preferably, the thickness of a single doped silicon quantum dot layer is 5-10 nm;

[0015] The doped silicon quantum dot layer is a silicon oxide layer with doped silicon quantum dots formed by annealing a doped silicon-rich oxide layer, or the doped silicon quantum dot layer is a polycrystalline silicon layer with doped silicon quantum dots formed by annealing a doped amorphous silicon layer.

[0016] More preferably, the insulating layer is a silicon oxide layer or a silicon carbide layer.

[0017] Preferably, a photovoltaic cell further includes an emitter, a front passivation antireflection layer, and a front metal electrode located in the front grid line contact area, which are sequentially disposed on the front side of the silicon wafer; the lower end of the front metal electrode passes through the front passivation antireflection layer and makes ohmic contact with the emitter.

[0018] Preferably, a photovoltaic cell further includes a tunneling oxide layer, a doped polycrystalline silicon layer, a back passivation antireflection layer, and a back metal electrode located in the back gate contact area, which are sequentially disposed on the back side of the silicon wafer; the upper end of the back metal electrode passes through the back passivation antireflection layer and makes ohmic contact with the doped polycrystalline silicon layer.

[0019] The tunneling oxide layer is located on the back side of the locally doped silicon quantum dot structure and on the back side of the bare silicon wafer.

[0020] More preferably, the silicon wafer is an n-type silicon wafer; the front surface of the silicon wafer has a pyramid-shaped textured surface; and the back surface of the silicon wafer is a flat, polished surface.

[0021] This utility model also discloses a photovoltaic module, which includes a photovoltaic cell as described above.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects:

[0023] The photovoltaic cell of this invention (1) has a multilayer composite structure in its doped silicon quantum dot region (including m-1 doped silicon quantum dot layers and m-1 insulating layers, with the insulating layer and the doped silicon quantum dot layers alternately disposed on the back side of the insulating tunneling region). This results in more doped silicon quantum dots being located at the edge of the insulating layer, which increases the tunneling success rate of the carriers formed by the doped silicon quantum dots capturing photons, thereby forming more effective carriers and helping to improve the back side light absorption capacity and bifaciality of the cell; (2) it is combined with the arrangement of several locally doped silicon quantum dot structures that are spaced apart on the back side of the silicon wafer, and these locally doped silicon quantum dot structures are only disposed in the non-spaced region of the non-metallized region on the back side. This can effectively avoid the risk of increased series resistance of the cell caused by the presence of insulating materials (such as insulating layers) covering the doped silicon quantum dots in the metallized region on the back side, and can also enable the carriers formed by the doped silicon quantum dots (such as n-Si QDs) to increase the pathway in the three-dimensional direction to form effective carriers.

[0024] Therefore, this photovoltaic cell can effectively avoid the risks brought about by the multilayer silicon quantum dot structure of the existing CN117878178A, such as increased series resistance, poor contact, and difficulty for charge carriers to pass through the insulating material to form effective charge carriers. It can further improve the light absorption capacity and bifaciality of the back of the cell, thereby improving the power of the photovoltaic module. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the cross-sectional structure of the silicon oxide / n-SRO composite layer formed by magnetron sputtering in step one of this invention.

[0026] Figure 2 This is a schematic diagram of the cross-sectional structure of the n-SiQDs composite layer formed after annealing in step one of this utility model.

[0027] Figure 3 This is a bottom view of the laser-opened area of ​​the silicon wafer after step two of the present invention.

[0028] Figure 4 This is a schematic diagram of the cross-sectional structure of the photovoltaic cell obtained in step three of this utility model.

[0029] Figure 5 The graph shows the back-side short-circuit current (Isc) data of photovoltaic cells in Examples 1-2 and Comparative Examples 1-3.

[0030] Figure 6 The graph shows the bifaciality data of photovoltaic cells in Examples 1-2 and Comparative Examples 1-3.

[0031] Explanation of reference numerals: 1. Silicon oxide / n-SRO composite layer; 11. Silicon oxide layer; 12. n-SRO layer; 2. n-Si QDs composite layer; 21. Insulating layer; 22. n-Si QDs layer; 3. n-type silicon quantum dot;

[0032] Main grid line area 4; Fine grid line area 5; Gap area 6;

[0033] 7. Silicon wafer; 8. p-type emitter; 9. Alumina layer; 10. Front silicon nitride layer; 11. Front metal electrode; 12. Localized n-Si QDs structure; 121. Insulating tunneling region; 122. n-Si QDs region; 13. Tunneling oxide layer; 14. n-type poly layer; 15. Back silicon nitride layer; 16. Back metal electrode. Detailed Implementation

[0034] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] This utility model discloses a method for improving the bifaciality of photovoltaic cells, comprising the following steps:

[0036] S1. Prepare a silicon quantum dot composite layer on the back side of the pre-treated silicon wafer; wherein the back side of the silicon wafer is divided into a back metallized region and a back non-metallized region, and the back non-metallized region has several spacer regions that are separated from each other.

[0037] S2. Perform localized film opening on the back side of the silicon wafer to remove the doped silicon quantum dot composite layer in the back gate contact area;

[0038] S3. Perform a dot matrix opening process on the back side of the silicon wafer to remove the doped silicon quantum dot composite layer in the spacer region of the dot matrix, thereby obtaining a number of locally doped silicon quantum dot structures that are spaced apart from each other.

[0039] This invention discloses a method for improving the bifaciality of photovoltaic cells, taking TOPCon cells as an example, which specifically includes the following steps:

[0040] Step 1: First, the silicon wafer 7 is subjected to double-sided texturing, boron diffusion on the front side, removal of the oxide layer on the back side, and polishing on the back side to prepare the n-Si QDs composite layer 2 (i.e., n-type doped silicon quantum dot composite layer).

[0041] The process involves double-sided texturing, which creates a pyramidal textured surface on both the front and back sides of the silicon wafer 7. Front-side boron diffusion forms a p-type emitter 8 (e.g., a p+ emitter) on the front side of the silicon wafer 7. After removing the back oxide layer, back-side polishing creates a smooth, flat polished surface on the back of the silicon wafer 7. Double-sided texturing, front-side boron diffusion, back oxide layer removal, and back-side polishing are standard procedures in existing TOPCon cell fabrication and will not be elaborated upon here.

[0042] The n-Si QDs composite layer 2 can be prepared using the following two methods:

[0043] Option 1: The n-Si QDs composite layer 2 is prepared by magnetron sputtering, specifically including the following preparation steps:

[0044] Step 11: First, magnetron sputter a quartz target to deposit a 1-5 nm thick SiO2 layer (silicon oxide layer 11) on the back side of silicon wafer 7.

[0045] Step 12: Then, magnetron sputtering of silicon target and quartz target and introducing phosphine to deposit a 5-10 nm thick n-type doped silicon-rich oxide layer (referred to as n-type silicon-rich oxide layer, i.e. n-SRO layer 12) on the back side of silicon oxide layer 11.

[0046] Step 13: Repeat the magnetron sputtering deposition process of steps 11 and 12 above to obtain silicon oxide / n-SRO composite layer 1 (silicon oxide / n-type silicon-rich oxide composite layer). See also Figure 1 The sum of the number of silicon oxide layers 11 and n-SRO layers 12 in the silicon oxide / n-SRO composite layer 1 is an odd number of layers (5-19 layers in total); thus, the top and bottom layers of the silicon oxide / n-SRO composite layer 1 (or n-Si QDs composite layer 2) are both silicon oxide layers 11 (which are insulating layers 21).

[0047] Step 14: Anneal the silicon oxide / n-SRO composite layer 1 to form the n-Si QDs composite layer 2 (e.g., Figure 2 (As shown).

[0048] Option 2: The n-Si QDs composite layer 2 is prepared by PECVD (plasma-enhanced chemical vapor deposition), specifically including the following preparation steps:

[0049] Step 21: First, using silane and methane as raw materials, prepare an intrinsic silicon carbide layer (SiC layer) with a thickness of 1-5 nm on the back side of silicon wafer 7.

[0050] Step 22: Using phosphine and silane as raw materials, prepare a 5-10 nm thick n-type doped amorphous silicon layer (such as an n-type doped hydrogenated amorphous silicon layer, i.e., an n-Si:H layer) on the back side of the intrinsic silicon carbide layer.

[0051] Step 23: Repeat the PECVD deposition process of steps 21 and 22 above to obtain a SiC / n-Si:H composite layer. The sum of the number of SiC layers and n-Si:H layers in the SiC / n-Si:H composite layer is an odd number of layers (5-19 layers in total); thus, the top and bottom layers of the SiC / n-Si:H composite layer (or n-Si QDs composite layer 2) are both SiC layers (which are insulating layers 21).

[0052] Step 24: Anneal the SiC / n-Si:H composite layer at 900-800℃ for 45-60 minutes to form the n-Si QDs composite layer 2 (e.g., Figure 2 (As shown).

[0053] The n-Si QDs composite layer 2 in this invention is formed by depositing silicon oxide / n-SRO composite layer 1 (or SiC / n-Si:H composite layer) together and then annealing it, resulting in a multilayer structure. For example... Figure 2 As shown, the n-Si QDs composite layer 2 includes m insulating layers 21 (the insulating layers 21 are silicon oxide layers 11 or intrinsic silicon carbide layers) and m-1 n-Si QDs layers 22 (the n-Si QDs layers 22 are n-SRO layers 12 or n-Si:H layers formed by annealing), where m is an integer from 3 to 10; and the insulating layers 21 and n-Si QDs layers 22 (n-type silicon quantum dot layers) are sequentially and alternately deposited on the back side of the silicon wafer 7. Thus, the uppermost and lowermost layers of the n-Si QDs composite layer 2 are both insulating layers 21. A number of n-Si QDs (n-type silicon quantum dots 3) are distributed at intervals within the n-Si QDs layers 22. Therefore, the outer surfaces of the n-type silicon quantum dots 3 are all encapsulated by the insulating layers 21 (or insulating materials, such as silicon oxide or intrinsic silicon carbide).

[0054] Taking the preparation of the n-Si QDs composite layer 2 using Scheme 1 as an example, in the prepared n-SRO layer 12, silicon and phosphorus elements are dispersed in silicon oxide. During high-temperature annealing, silicon and phosphorus elements will "condense" into individual dots, namely n-type silicon quantum dots 3 (n-SiQDs). At this time, the n-Si QDs are encapsulated in an insulating material (such as SiO2). Therefore, the majority of the n-Si QDs composite layer 2 is an insulating material (such as SiO2 or SiC). The n-SiQDs exist in the n-Si QDs composite layer 2 in a dotted form. The proportion of n-SiQDs in the n-Si QDs composite layer 2 is not large. The n-Si QDs are essentially embedded in the n-Si QDs composite layer 2. Therefore, the n-Si QDs in the n-Si QDs composite layer 2 are surrounded by an insulating material (such as SiO2 or SiC).

[0055] Compared to the silicon quantum dots in the existing technology CN117878178A, the n-Si QDs composite layer 2 of the photovoltaic cell in this invention is phosphorus-doped (i.e., n-type doped), mainly because:

[0056] This invention aims to improve the bifaciality of photovoltaic cells, primarily by enhancing the back-side photoelectric conversion efficiency (referred to as back-side efficiency). This is achieved by using an n-Si QDs composite layer 2 as a light-absorbing layer to increase back-side light absorption. Currently, crystalline silicon photovoltaic cells are mainly n-type cells. The silicon substrate (i.e., silicon wafer 7) used in these cells is itself a silicon wafer 7 doped with a certain proportion of phosphorus (i.e., an n-type silicon wafer), which inherently exhibits a certain degree of negative charge (n, negative). The n-type poly layer 14 (n-type polycrystalline silicon layer, such as an n++ poly layer) is itself a parasitic light-absorbing layer; the absorbed light cannot be used to generate electricity. Based on this, in order to further improve the power generation capacity and bifaciality of the back side of the photovoltaic cell, this invention prepares an n-Si QDs composite layer 2 (n-type doped silicon quantum dot composite layer) between the silicon substrate (silicon wafer 7) and the n++poly layer on the back side of the photovoltaic cell. This creates a doping concentration gradient of n→n+→n++ between the bulk region (silicon substrate) - n-Si QDs composite layer 2 - n++poly layer, enabling the back side of the photovoltaic cell to efficiently absorb light, generate electricity, and guide the electricity out of the photovoltaic cell, thereby better improving the power generation capacity of the back side of the photovoltaic cell and further improving the bifaciality.

[0057] It should be noted that the n-SiQDs composite layer 2 prepared in step one covers the entire back side of the silicon wafer 7.

[0058] Step 2: Perform laser localized delamination on the back gate contact area (corresponding to the back metallization area) of silicon wafer 7 to remove the n-Si QDs composite layer 2 in the back gate contact area, while retaining the n-Si QDs composite layer 2 in the back non-gate contact area (corresponding to the back non-metallization area); then, perform laser dot matrix delamination on the back non-gate contact area of ​​silicon wafer 7 to remove localized n-Si QDs composite layer 2 in the back non-gate contact area (e.g., Figure 3-4 As shown), several local n-Si QDs structures 12 (local n-type doped silicon quantum dot structures, or simply local n-type silicon quantum dot structures) can be obtained by distributing them at intervals.

[0059] See Figure 4 Each localized n-Si QDs structure 12 includes an insulating tunneling region 121 and an n-Si QDs region 122 (n-type silicon quantum dot region) disposed on the back side of the insulating tunneling region 121. See also Figure 2-4The n-Si QDs region 122 includes m-1 n-Si QDs layers 22 and m-1 insulating layers 21, where m is an integer from 3 to 10. The n-Si QDs layers 22 and the insulating layers 21 are alternately disposed on the back side of the insulating tunneling region 121, and the back side of the insulating tunneling region 121 directly contacts one n-Si QDs layer 22. A number of n-type silicon quantum dots 3 (n-SiQDs) are distributed at intervals within the n-SiQDs layer 22.

[0060] It should be noted that when the n-Si QDs composite layer 2 is prepared using the magnetron sputtering method of step one, the insulating tunneling region 121 is formed by the silicon oxide layer 11 first deposited on the back side of the silicon wafer 7 in step 11. However, when the n-Si QDs composite layer 2 is prepared using the PECVD method of step one, the insulating tunneling region 121 is formed by the silicon carbide layer first deposited on the back side of the silicon wafer 7 in step 21.

[0061] In practice, the metal electrode includes several spaced main grid lines and several spaced fine grid lines. The specific distribution of the main grid lines and fine grid lines refers to existing technology, so it will not be described in detail here. Taking the back of a photovoltaic cell as an example, the area where the main grid lines are located on the back (referred to as main grid line area 4) and the area where the fine grid lines are located on the back (referred to as fine grid line area 5) are the back grid line contact area (i.e., the back metallization area).

[0062] Among them, laser localized film opening treatment of the back grid line contact area is... Figure 3 The n-Si QDs composite layer 2 in the main gate line region 4 and the fine gate line region 5 is removed by laser-based delamination. The main purpose is to reduce the resistance increase caused by the insulating layer 21 in the n-Si QDs composite layer 2, allowing the back metal electrode 16 to achieve better ohmic contact with the subsequently fabricated n-type poly layer 14. Laser-based delamination is used to remove localized n-Si QDs composite layer 2 in the non-gate line contact areas on the back side, i.e., to remove... Figure 3-4 The n-Si QDs composite layer 2 in the gap region 6 (spacer region) is designed to increase the pathways of the charge carriers formed by the n-Si QDs in the three-dimensional direction, thereby forming effective charge carriers and further improving the dihedrality.

[0063] In practice, after laser localization to remove the n-Si QDs composite layer 2 in the back-side gate contact area, the outer surface of the n-SiQDs in the n-SiQDs composite layer 2 in the back-side non-gate contact area is still covered with an insulating material (SiC or SiO2). For photons captured by the n-SiQDs to form excitons and charge carriers, they still need to pass through the insulating material on the outer surface of the n-SiQDs (i.e., insulating layer 21 or insulating tunneling region 121) to form effective charge carriers. This is determined by the material properties of the quantum dots themselves; they must be encased in other materials, such as insulating materials, to exist stably.

[0064] The insulating material (insulating layer 21 or insulating tunneling region 121, made of SiC or SiO2) surrounding the n-Si QDs is not completely impenetrable. The "tunneling" in "tunneling layer" means that charge carriers have a certain probability of passing through the insulating layer 21. The probability of charge carriers formed by n-Si QDs passing through the insulating layer 21 (or insulating tunneling region 121) formed by the insulating material is related to factors such as the charge carrier concentration and the thickness of the insulating layer 21 (or insulating tunneling region 121). This invention solves the above problem through the following two methods to effectively increase the probability of charge carriers formed by n-Si QDs passing through the insulating layer 21 (or insulating tunneling region 121) to form effective charge carriers:

[0065] Firstly, the n-Si QDs enclosed by the insulating layer 21 are not spherical in shape, but rather are individual points embedded in the insulating layer 21, such as... Figure 2 As shown.

[0066] Therefore, this invention designs a multilayer composite structure (i.e., n-Si QDs composite layer 2), so that more n-Si QDs are located at the edge of the insulating layer 21, thereby increasing the probability of tunneling success for its charge carriers.

[0067] Secondly, step two improves the tunneling probability of carriers formed by n-Si QDs through the synergistic combination of laser localized film opening and laser lattice film opening processes.

[0068] like Figure 3-4 In the gap region 6 (spacer region), a portion of the n-Si QDs composite layer 2 located in the non-gate contact area on the back side is further removed in a dot matrix manner to obtain several local n-Si QDs structures 12 that are spaced apart from each other. This allows the charge carriers generated by the n-Si QDs (n-type silicon quantum dots 3) to move not only in two-dimensional directions (such as the up and down direction), but also in three-dimensional directions (such as the up and down and left and right directions), thereby greatly increasing the probability that the charge carriers generated by the n-Si QDs can successfully tunnel through the insulating tunneling region 121 or the insulating layer 21.

[0069] Step 3: The silicon wafer 7 processed in Step 2 is then polished and cleaned sequentially (to flatten the back laser-etched area and reduce laser damage), and a back tunneling oxide layer 13 (such as a tunneling silicon oxide layer 11) and an n-type poly layer 14 (such as an n++ poly layer) are prepared (the tunneling oxide layer 13 and the n-type poly layer 14 together form a TOPCon structure). BOE cleaning (buffered oxide etching cleaning) is performed, followed by the preparation of a front passivation antireflection layer (which includes an aluminum oxide layer 9 and a front silicon nitride layer 10 sequentially deposited on the front side of the p-type emitter 8) and a back passivation antireflection layer (which includes a back silicon nitride layer 15 deposited on the back side of the n-type poly layer 14). Finally, a screen printing sintering (i.e., metallization) process is completed to obtain a photovoltaic cell of this invention (such as...). Figure 4 As shown in the figure.

[0070] The polishing and cleaning, TOPCon structure preparation, BOE cleaning, preparation of front and back passivation and antireflection layers, and metallization are all based on the existing TOPCon battery preparation process, so they will not be described in detail.

[0071] In steps one through three above, wet processing and annealing can reduce damage and improve battery yield.

[0072] This utility model provides a photovoltaic cell, such as... Figure 3-4 As shown, it includes: a silicon wafer 7; the front side of the silicon wafer 7 is sequentially provided with a p-type emitter 8, a front passivation anti-reflection layer and a front metal electrode 11 located in the front metallization region (i.e. the front gate contact region); the lower end of the front metal electrode 11 passes through the front passivation anti-reflection layer and makes ohmic contact with the p-type emitter 8. The back side of the silicon wafer 7 is sequentially provided with a tunneling oxide layer 13, an n-type poly layer 14, a back passivation antireflection layer, and a back metal electrode 16 located in the back metallization region (i.e., the back gate contact region). The upper end of the back metal electrode 16 passes through the back passivation antireflection layer and makes ohmic contact with the n-type poly layer 14. Between the back side of the silicon wafer 7 and the tunneling oxide layer 13, there are also a number of locally distributed n-Si QDs structures 12. The locally distributed n-Si QDs structures 12 are located in the non-spaced region of the back non-metallization region. Each locally distributed n-Si QDs structure 12 includes an insulating tunneling region 121 and an n-Si QDs region 122 located on the back side of the insulating tunneling region 121. Several n-type silicon quantum dots 3, which are wrapped by the insulating layer 21 or the insulating tunneling region 121, are distributed at intervals in the n-Si QDs region 122.

[0073] The following provides a method for improving the bifaciality of photovoltaic cells according to this utility model, and specific embodiments of the photovoltaic cells: Embodiment 1

[0074] This embodiment provides a method for improving the bifaciality of photovoltaic cells. It utilizes the magnetron sputtering method of Scheme 1 to prepare an n-Si QDs composite layer 2, and then removes part of the n-Si QDs composite layer 2 through a laser localized film-opening process combined with a laser dot matrix film-opening process to obtain a localized n-Si QDs structure 12.

[0075] This embodiment provides a method for improving the bifaciality of photovoltaic cells. See [link to relevant documentation]. Figure 1-4 Specifically, it includes the following steps:

[0076] Step 1, Double-sided texturing: Using an n-type c-Si single crystal silicon wafer 7 with a resistivity of 1Ω·cm as the silicon substrate, KOH solution is used to perform double-sided texturing on the silicon wafer 7 to form a pyramid-shaped textured surface on the front and back surfaces of the silicon wafer 7, which mainly serves to trap light.

[0077] Step 2, front-side boron diffusion: Boron doping is performed on the front side of silicon wafer 7 using a thermal diffusion process, preferably using BBr3 as the boron doping source to prepare p-type emitter 8 (such as p+ emitter).

[0078] Step 3: Removal of the back oxide layer and back polishing: Using a chain-type single-sided HF treatment device, the volume ratio of HF (hydrofluoric acid) solution to DI Water (deionized water) in the machine is 1:10, and the mass fraction of the HF solution is 40%, to remove the back oxide layer. Then, the silicon wafer 7 is back polished in a tank-type polishing device using a 60°C alkaline solution for 200 seconds. The volume ratio of the polishing solution is DI Water:KOH (potassium hydroxide) solution:ADD (additive) = 120:1:1, and the mass fraction of the KOH solution is 45%, forming a smooth and flat polished surface on the back of the silicon wafer 7.

[0079] Step 4: PVD (Physical Vapor Deposition, preferably magnetron sputtering) method is used to prepare n-Si QDs composite layer 2 (n-type doped silicon quantum dot composite layer): A 2 nm thick SiO2 layer is formed by magnetron sputtering on a quartz target (the SiO2 layer is called silicon oxide layer 11 before annealing, and becomes insulating layer 21 or insulating tunneling region 121 after annealing); then, a silicon target and a quartz target are magnetron sputtered and phosphine is introduced to form a 5 nm thick n-type doped silicon-rich oxide layer (the n-type doped silicon-rich oxide layer is called n-SRO layer 12 before annealing, and becomes n-Si after annealing). QDs layer 22); repeat the above preparation steps of silicon oxide layer 11 and n-SRO layer 12 to obtain silicon oxide / n-SRO composite layer 1 (which includes 10 silicon oxide layers 11 and 9 n-SRO layers 12, and silicon oxide layers 11 and n-SRO layers 12 are alternately formed on the back side of silicon wafer 7, so the uppermost and lowermost layers of the silicon oxide / n-SRO composite layer 1 are both silicon oxide layers 11); then anneal at 1100℃ for 30 min, so that phosphorus and silicon elements in n-SRO layer 12 gradually precipitate and crystallize to form n-Si QDs (n-type silicon quantum dots 3), and n-SiQDs composite layer 2 can be obtained.

[0080] Step 5, Laser Localized Film Removal Process: A short-wavelength ultraviolet picosecond laser (wavelength 355nm) with an energy of 5.0W is used to perform laser localized film removal processing on the back gate line contact area. The laser frequency of the laser is preferably 1MHz. The n-Si QDs composite layer 2 in the back gate line contact area is removed to expose the back surface of the silicon wafer 7 in the back gate line contact area.

[0081] Step 6, Laser dot matrix opening process: A 248nm ultraviolet picosecond laser is used, with an energy of 5.0-5.5W (preferably 5W) and a laser frequency of 0.5×10⁻⁶. 6 -2.0×10 6 A laser with a frequency of 1 MHz is used to perform laser dot matrix opening processing on the non-gateline contact area on the back side of the silicon wafer 7, exposing the gap region 6 (one gap region 6 is a single dot matrix opening region in step 6). The opening area of ​​a single gap region 6 is 15×15nm, and the center-to-center distance between two adjacent gap regions 6 is 30nm. After processing in steps 5-6, several locally distributed n-Si QDs structures 12 are obtained.

[0082] Step 7, Polishing and Cleaning: Polishing and cleaning are carried out in a tank polishing equipment using an alkaline solution at 35°C for 100 seconds to smooth the laser-opened area on the back side and reduce laser damage. The volume ratio of the polishing liquid is DI Water:KOH solution:ADD = 150:1:1, and the mass fraction of KOH solution is 45%.

[0083] Step 8: Fabrication of the back-side TOPCon structure: First, a 1 nm thick silicon oxide layer 13 is prepared on the back side of the localized n-Si QDs structure 12 and the exposed silicon wafer 7. Then, a 100 nm thick phosphorus-doped amorphous silicon layer (ni-Si) is prepared on the back side of the tunneling oxide layer 13. The layers are then annealed at 850 °C for 2000 s to activate the doped atoms and transform the phosphorus-doped amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer (i.e., an n-type poly layer 14).

[0084] Step 9, BOE cleaning: Using a tank cleaning device, BOE cleaning solution with a volume ratio of DI Water:KOH solution (KOH solution mass fraction of 45%):H2O2 = 90:1:4 is used to remove surface organic impurities, and a mixed solution of HCl & HF is used to remove the oxide layers (such as oxide layers formed by boron doping and phosphorus doping) on ​​the front and back sides.

[0085] Step 10: Fabrication of front and back passivation antireflection layers: An 8 nm thick aluminum oxide layer 9 is fabricated on the front side of the p-type emitter 8 using ALD (Atomic Layer Deposition) as a passivation layer; then, a 70 nm thick front silicon nitride layer 10 is fabricated on the aluminum oxide layer 9 using PECVD as a passivation / antireflection layer; the aluminum oxide layer 9 and the front silicon nitride layer 10 together serve as the front passivation antireflection layer. A 90 nm thick back silicon nitride layer is fabricated on the back side of the n-type poly layer 14 using PECVD as the back passivation antireflection layer.

[0086] Step 11, Metallization: Using screen printing equipment, metal electrode paste is coated on both the front and back metallization areas (i.e., the front and back grid line contact areas) of the battery, and then sintered to obtain the front metal electrode 11 and the back metal electrode 16. The upper end of the back metal electrode 16 makes ohmic contact with the n-type poly layer 14, and the lower end of the front metal electrode 11 makes ohmic contact with the p-type emitter 8; in this way, the metal electrodes are bonded to silicon to form an alloy, which leads out the photogenerated carriers, completing the battery fabrication (battery structure as shown in Figure 11). Figure 4 (As shown).

[0087] Example 2

[0088] The method for improving the bifaciality of photovoltaic cells and the photovoltaic cell in this embodiment are both based on Embodiment 1, but the difference between them is as follows:

[0089] Step 4 is changed to use the PECVD (Plasma Enhanced Chemical Vapor Deposition) method of Scheme 2 to prepare the n-Si QDs composite layer: The silicon wafer processed in Step 3 is placed in a PECVD equipment with a system temperature of 260℃. A mixture of silane and methane is used as the reaction gas source, with a methane to silane flow rate ratio of 10:1, and the methane flow rate is 55 cm³ / h. 3 / s, silane flow rate is 5.5cm3 / s, a 5nm thick a-SiC:H layer is deposited on the back side of the silicon wafer (the a-SiC:H layer is called hydrogenated amorphous silicon carbide layer before annealing, and becomes an insulating layer or insulating tunneling region after annealing); then the methane flow is stopped, silane is continued to flow, and phosphine gas is introduced at a flow rate of 5cm. 3 / s, a 5nm thick n-Si:H layer is deposited on the back side of the a-SiC:H layer (before annealing, the n-Si:H layer is called an n-type doped hydrogenated amorphous silicon layer, and after annealing, it becomes an n-Si QDs layer); repeat the above preparation steps of the a-SiC:H layer and the n-Si:H layer to obtain an a-SiC:H / n-Si:H composite layer (which includes 3 a-SiC:H layers and 2 n-Si:H layers, and the a-SiC:H layer and the n-Si:H layer are alternately formed on the back side of the silicon wafer, so the top and bottom layers of the a-SiC:H / n-Si:H composite layer are both a-SiC:H layers); then anneal at 900℃ for 1h, so that the phosphorus and silicon elements in the n-Si:H layer gradually precipitate and crystallize to form n-Si QDs, and the n-Si QDs composite layer can be obtained.

[0090] Comparative Example 1

[0091] This comparative example describes a method for preparing a photovoltaic cell and a photovoltaic cell, both based on Example 1, but differing from Example 1 in that:

[0092] Steps 4 (preparation of n-Si QDs composite layer by magnetron sputtering), 5 (laser localized film opening treatment), and 6 (laser array film opening treatment) of Example 1 are omitted. That is, the photovoltaic cell in this comparative example is a photovoltaic cell without n-SiQDs (n-type silicon quantum dots) prepared using the existing TOPCon cell preparation process.

[0093] Comparative Example 2

[0094] This comparative example describes a method for improving the bifaciality of photovoltaic cells, and the photovoltaic cell used is based on Example 1. The difference between this method and Example 1 is that:

[0095] Step 6 (laser dot matrix opening process) of Example 1 has been omitted. Therefore, the photovoltaic cell of this comparative example only removes the n-SiQDs composite layer in the back grid contact area, while retaining the n-SiQDs composite layer in the back non-grid contact area.

[0096] Comparative Example 3

[0097] This comparative example describes a method for improving the bifaciality of photovoltaic cells, and the photovoltaic cell used is based on Example 2. The difference between this method and Example 2 is that:

[0098] Step 6 (laser dot matrix opening process) of Example 2 has been omitted. Therefore, the photovoltaic cell of this comparative example only removes the n-SiQDs composite layer in the back grid contact area, while retaining the n-SiQDs composite layer in the back non-grid contact area.

[0099] Performance testing

[0100] The back-side short-circuit current (Isc) and bifaciality of the photovoltaic cells in Examples 1-2 and Comparative Examples 1-3 were tested, and the test results are as follows: Figure 5 and Figure 6 As shown.

[0101] Since I = Q / t (i.e., current = amount of electricity passing through per unit time), the light absorption capacity of each photovoltaic cell can be compared by detecting the magnitude of the short-circuit current Isc on the back of each photovoltaic cell.

[0102] Combination Figure 5-6 It can be seen that, compared with Comparative Example 1 (without n-type silicon quantum dots), the photovoltaic cells of Examples 1-2 and Comparative Examples 2-3 all have n-type silicon quantum dots on the back. Therefore, the photovoltaic cells of Examples 1-2 and Comparative Examples 2-3 can bring a short-circuit current gain of 0.03-0.1A, that is, improve the light absorption capacity and bifaciality by 0.3-1% (for example, compared with Comparative Example 1, the bifaciality of the examples is improved by 0.94%).

[0103] Compared to Comparative Examples 2-3 (which did not undergo laser dot matrix opening processing and completely preserved the n-Si QDs composite layer in the non-gateline contact area on the back side), Examples 1-2, based on the laser local opening processing process, further combined the laser dot matrix opening processing process to obtain several local n-Si QDs structures that are spaced apart from each other. This allows the charge carriers formed by the n-Si QDs to have more pathways in the three-dimensional direction to form effective charge carriers, thus further improving the bifaciality (compared to Comparative Examples 2-3, the bifaciality of Examples 1-2 is improved by about 5%).

[0104] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0105] The technical solution provided by this utility model has been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A photovoltaic cell, characterized in that, include: A silicon wafer and a plurality of locally doped silicon quantum dot structures disposed on the back side of the silicon wafer at intervals; the back side of the silicon wafer is divided into a back metallized region and a back non-metallized region, and the back non-metallized region has a plurality of spaced regions that are separated from each other; the locally doped silicon quantum dot structures are disposed in the non-spaced regions of the back non-metallized region. Each of the localized doped silicon quantum dot structures includes an insulating tunneling region and a doped silicon quantum dot region disposed on the back side of the insulating tunneling region; the doped silicon quantum dot region includes m-1 doped silicon quantum dot layers and m-1 insulating layers, where m is an integer from 3 to 10; the doped silicon quantum dot layers and the insulating layers are alternately arranged in sequence, such that the doped silicon quantum dot layers are disposed on the back side of the insulating tunneling region; a plurality of doped silicon quantum dots are distributed at intervals within the doped silicon quantum dot layers.

2. A photovoltaic cell according to claim 1, characterized in that, The localized doped silicon quantum dot structure is of the n-type doping type, and the doped silicon quantum dots are n-type silicon quantum dots.

3. A photovoltaic cell according to claim 1 or 2, characterized in that, The area of ​​the interval region is 15×15nm to 30×30nm, and the distance between the center points of two adjacent interval regions is 20-50nm.

4. A photovoltaic cell according to claim 1 or 2, characterized in that, The thickness of the insulating tunneling region is 1-5 nm, and the material of the insulating tunneling region is silicon oxide or silicon carbide.

5. A photovoltaic cell according to claim 1 or 2, characterized in that, The thickness of a single doped silicon quantum dot layer is 5-10 nm; The doped silicon quantum dot layer is a silicon oxide layer with doped silicon quantum dots formed by annealing a doped silicon-rich oxide layer, or the doped silicon quantum dot layer is a polycrystalline silicon layer with doped silicon quantum dots formed by annealing a doped amorphous silicon layer.

6. A photovoltaic cell according to claim 1 or 2, characterized in that, The insulating layer is a silicon oxide layer or a silicon carbide layer.

7. A photovoltaic cell according to claim 1, characterized in that, It also includes an emitter, a front passivation antireflection layer, and a front metal electrode located in the front gate contact area, which are sequentially disposed on the front side of the silicon wafer; the lower end of the front metal electrode passes through the front passivation antireflection layer and makes ohmic contact with the emitter.

8. A photovoltaic cell according to claim 1, characterized in that, It also includes a tunneling oxide layer, a doped polysilicon layer, a back passivation antireflection layer and a back metal electrode located in the back gate contact area, which are sequentially disposed on the back side of the silicon wafer; the upper end of the back metal electrode passes through the back passivation antireflection layer and makes ohmic contact with the doped polysilicon layer. The tunneling oxide layer is located on the back side of the locally doped silicon quantum dot structure and on the back side of the bare silicon wafer.

9. A photovoltaic cell according to claim 1 or 2, characterized in that, The silicon wafer is an n-type silicon wafer; the front surface of the silicon wafer has a pyramid-shaped textured surface; the back surface of the silicon wafer is a flat, polished surface.

10. A photovoltaic module, characterized in that, It includes a photovoltaic cell as described in any one of claims 1-9.

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