A high resolution temperature measurement system for a freezing point osmometer

Abstract

The application discloses a high-resolution temperature measurement system for a freezing point osmometer, comprising an analog-to-digital conversion core unit, wherein a power management unit, a signal conditioning and differential level sensor interface unit and a communication unit are connected to the analog-to-digital conversion core unit. The application has the following advantages: through the collaborative optimization design of the power supply, the signal chain and the core ADC, various noise sources are effectively suppressed, and the performance of the high-precision ADC is maximized, so that the sub-millidegree (0.01 m°C) resolution measurement of the sample temperature is realized, and a solid guarantee is provided for the accurate determination of the freezing point.

Description

Technical Field

[0001] This utility model relates to a temperature measurement circuit, specifically, to a temperature measurement system, belonging to the field of electronic technology. Background Technology

[0002] Freezing-point osmoremetry is an indispensable piece of equipment in clinical testing and life science research. Its working principle is to calculate the osmotic concentration by accurately measuring the freezing point depression of a solution during cooling. The accuracy of freezing-point osmoremetry is highly dependent on its ability to monitor temperature changes in real time and at high resolution. Near the freezing point, the temperature change of the solution is extremely small and slow; any tiny measurement error will be amplified, leading to significant deviations in the final osmotic pressure result.

[0003] Traditional temperature measurement schemes typically employ simple thermistor voltage divider circuits paired with ordinary ADCs, whose resolution and stability are insufficient for measuring freezing point osmotic pressure. Existing schemes generally suffer from the following problems: 1. Power supply noise interference: High-frequency noise generated by digital circuits can couple into the analog measurement path, causing reading drift and instability.

[0004] 2. Reference voltage drift: Temperature drift and long-term drift of the reference source will introduce systematic errors.

[0005] 3. Insufficient signal conditioning: Lacks effective filtering and protection circuits, making it susceptible to external electromagnetic interference.

[0006] 4. Sensor measurement bottleneck: Using a single wire to measure resistance value is prone to introducing ground network interference, and the resolution is difficult to improve when the signal is weak. Utility Model Content

[0007] The technical problem to be solved by this utility model is to provide a high-resolution temperature measurement system for a freezing point osmotic pressure analyzer, which addresses the above-mentioned shortcomings. Through the coordinated optimization design of the power supply, signal chain and core ADC, various noise sources are effectively suppressed and the performance of the high-precision ADC is maximized, thereby achieving sub-millisecond (0.01m°C) resolution measurement of sample temperature, providing a solid guarantee for accurate freezing point determination.

[0008] To solve the above technical problems, the present invention adopts the following technical solution: A high-resolution temperature measurement system for a freezing point osmotic pressure analyzer includes an analog-to-digital conversion core unit, which is connected to a power management unit, a signal conditioning and differential sensor interface unit, and a communication unit. The analog-to-digital conversion core unit includes a chip U4, model AD7124-8BCPZ. One end of a capacitor C20 is connected to pin 1 of the chip U4, and the other end of the capacitor C20 is grounded. One end of a capacitor C21 is connected to pin 24 of the chip U4, and the other end of the capacitor C21 is connected to AGND.

[0009] Furthermore, the power management unit includes a power input filter network, which includes parallel ferrite beads L1 and L2. One end of ferrite bead L1 is connected to one end of capacitor C2, one end of capacitor C1, and one end of resistor R12, and is connected to the VIN input power supply. The other ends of capacitor C2 and capacitor C1 are connected to PGND. One end of ferrite bead L1 and the other end of resistor R12 are connected to one end of capacitor C3 and one end of capacitor C4, and output a +12V power supply. The other ends of capacitor C3 and capacitor C4 are grounded.

[0010] Furthermore, the power management unit also includes a first-level voltage regulator module, which includes a chip U2, model LP2985A-50DBVR. Pins 1 and 3 of chip U2 are connected to a +12V power supply. Pin 4 of chip U2 is connected to one end of capacitor C16, and the other end of capacitor C16 is grounded. Pin 5 of chip U2 is connected to one end of resistor R6 and connected to a +5V power supply. The other end of resistor R6 is connected to one end of capacitor C17, one end of capacitor C18, and one end of capacitor C19 and connected to a +5V power supply. The other ends of capacitors C17, C18, and C19 are grounded.

[0011] Furthermore, the power management unit also includes a secondary voltage regulator module. The secondary voltage regulator module includes chips U1 and U3, which are ADP150AUJZ-3.3-R7. Pins 1 and 3 of chip U1 are connected to one end of capacitor C22 and connected to a +5V power supply. The other end of capacitor C22 is grounded. Pin 5 of chip U1 is connected to one end of capacitor C5 and one end of capacitor C6 and is connected to pin 2 of chip U4. The other ends of capacitor C5 and capacitor C6 are grounded.

[0012] Furthermore, pins 1 and 3 of the chip U3 are connected to a +5V power supply. Pin 5 of the chip U3 is connected to one end of capacitor C13, one end of capacitor C14, and one end of capacitor C15, and is connected to the AVDD power supply. The other end of capacitor C13 is connected to ground, and the other ends of capacitor C14 and capacitor C15 are connected to AGND.

[0013] Furthermore, the signal conditioning and differential sensor interface unit includes an interface CN1, which is used to connect an external high-precision NTC sensor. Pin 1 of the interface CN1 is connected to one end of resistor R2 and one end of resistor R4. The other end of resistor R4 is grounded. The other end of resistor R2 is connected to one end of capacitor C9 and one end of capacitor C8, and is also connected to pin 19 of chip U4. The other end of capacitor C9 is grounded.

[0014] Furthermore, pin 2 of interface CN1 is connected to one end of resistor R1, one end of capacitor C23, and pin 22 of chip U4. The other end of capacitor C23 is grounded. The other end of resistor R1 is connected to one end of capacitor C7 and the other end of capacitor C8, and is connected to pin 18 of chip U4. The other end of capacitor C7 is grounded.

[0015] Furthermore, the communication unit includes a connector that brings out the communication bus of the chip U4 through a standardized connector for easy interface with the host system. The connector is connected to the chip U4, pin 2 of the connector is connected to the VIN power supply, and pin 1 of the connector is connected to PGND.

[0016] The present invention adopts the above technical solution and has the following technical effects compared with the prior art: This invention provides unprecedented temperature measurement performance for freezing point osmolarity analyzers. Through synergistic optimization of the power supply, signal chain, and core ADC, various noise sources are effectively suppressed, maximizing the performance of the high-precision ADC. This achieves sub-millisecond resolution measurement of sample temperature, providing a solid guarantee for accurate freezing point determination. The resolution reaches the 0.01 m°C level, with excellent long-term stability and superior anti-interference capabilities. This enables the instrument to accurately capture the temperature inflection point near the freezing point, thereby elevating the accuracy and repeatability of osmolarity measurements to a new level, meeting the stringent requirements of high-end clinical diagnostics and scientific research experiments. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0018] Figure 1 This is a circuit diagram of the core analog-to-digital converter unit in this utility model; Figure 2 This is a circuit diagram of the power supply inlet filter network in this utility model; Figure 3 This is the circuit diagram of the first-stage voltage regulator module in this utility model; Figure 4 This is the circuit diagram of the two-stage voltage regulator module in this utility model; Figure 5 This is a circuit diagram of the signal conditioning and differential sensor interface unit in this utility model. Detailed Implementation

[0019] Example 1: A high-resolution temperature measurement system for a freezing point osmotic pressure analyzer, comprising an analog-to-digital conversion core unit, which is connected to a power management unit, a signal conditioning and differential sensor interface unit, and a communication unit.

[0020] like Figure 1 As shown, the analog-to-digital conversion core unit includes a chip U4, model AD7124-8BCPZ. One end of a capacitor C20 is connected to pin 1 of the chip U4, and the other end of the capacitor C20 is grounded. One end of a capacitor C21 is connected to pin 24 of the chip U4, and the other end of the capacitor C21 is connected to AGND.

[0021] The analog-to-digital converter (ADC) core unit is the "brain" of the entire system, responsible for converting the conditioned analog signal into high-precision digital data. Chip U4 employs a highly integrated, high-resolution, and extremely low-noise Σ-Δ ADC. This chip integrates a programmable gain amplifier (PGA), a precision reference source, an excitation source, and various digital filters, making it an ideal choice for achieving high-precision measurements. Chip U4's internal high-precision, low-temperature-drift reference voltage source provides temperature compensation based on the chip's internal temperature. It receives temperature signals from the signal conditioning unit and communicates with the main controller (such as an embedded processor) via a standard SPI bus, receiving configuration commands and uploading measurement data.

[0022] like Figures 2 to 4 As shown, the power management unit includes a power input filter network, a first-stage voltage regulator module, and a second-stage voltage regulator module. The power input filter network includes parallel ferrite beads L1 and L2. One end of ferrite bead L1 is connected to one end of capacitor C2, one end of capacitor C1, and one end of resistor R12, and is connected to the VIN input power supply. The other ends of capacitor C2 and capacitor C1 are connected to PGND. One end of ferrite bead L1 and the other end of resistor R12 are connected to one end of capacitor C3 and one end of capacitor C4, and output a +12V power supply. The other ends of capacitor C3 and capacitor C4 are grounded.

[0023] The system consists of parallel ferrite beads L1 and L2, along with parallel damping resistors R11 and R12. Ferrite beads L1 and L2 utilize their high impedance at high frequencies to effectively filter out high-frequency noise that may be introduced from external power supplies or other modules within the board. The parallel resistors R11 and R12 provide a backup path in extreme cases, ensuring the robustness of the power system.

[0024] The primary voltage regulator module includes chip U2, model LP2985A-50DBVR. Pins 1 and 3 of chip U2 are connected to a +12V power supply. Pin 4 of chip U2 is connected to one end of capacitor C16, and the other end of capacitor C16 is grounded. Pin 5 of chip U2 is connected to one end of resistor R6 and connected to a +5V power supply. The other end of resistor R6 is connected to one end of capacitors C17, C18, and C19 and connected to a +5V power supply. The other ends of capacitors C17, C18, and C19 are grounded.

[0025] The initially regulated voltage is reduced to the first-stage operating voltage to provide basic power for subsequent circuits. An ultra-low noise, low-dropout linear regulator U2 is selected. Its input terminals are equipped with input filter capacitors C3, C4, and C16, and output filter capacitors C17, C18, and C19. C17 is a large-capacity tantalum capacitor, while C3, C4, C16, C18, and C19 are multi-stage ceramic capacitors, collectively used to absorb transient currents and filter wideband noise. An inrush resistor R6 is also provided at the output terminal to ensure voltage stability during sudden load changes.

[0026] The secondary voltage regulator module includes chips U1 and U3, which are ADP150AUJZ-3.3-R7. Pins 1 and 3 of chip U1 are connected to one end of capacitor C22 and connected to a +5V power supply. The other end of capacitor C22 is grounded. Pin 5 of chip U1 is connected to one end of capacitor C5 and one end of capacitor C6 and is connected to pin 2 of chip U4. The other ends of capacitor C5 and capacitor C6 are grounded.

[0027] Pins 1 and 3 of the chip U3 are connected to a +5V power supply. Pin 5 of the chip U3 is connected to one end of capacitor C13, one end of capacitor C14, and one end of capacitor C15, and is connected to the AVDD power supply. The other end of capacitor C13 is connected to ground, and the other ends of capacitor C14 and capacitor C15 are connected to AGND.

[0028] The second-stage operating voltage is generated from the first-stage regulated power supply and divided into two independent outputs: one (generated by U1) is used to power the digital logic circuit (IOVDD), and the other (generated by U3) is used to power the analog core circuit (AVDD).

[0029] High-performance, ultra-low-noise linear regulators U1 and U3 are employed to ensure extremely low output voltage ripple. The two power supplies operate independently, effectively preventing noise crosstalk from digital circuit switching operations to sensitive analog measurement circuits. Each regulator's input and output terminals are equipped with high-frequency decoupling capacitors (such as C5, C6, C14, and C15).

[0030] like Figure 5As shown, the signal conditioning and differential sensor interface unit includes interface CN1, which is used to connect a high-precision NTC sensor. Pin 1 of interface CN1 is connected to one end of resistor R2 and one end of resistor R4. The other end of resistor R4 is grounded. The other end of resistor R2 is connected to one end of capacitor C9 and one end of capacitor C8, and is connected to pin 19 of chip U4. The other end of capacitor C9 is grounded. Pin 2 of interface CN1 is connected to one end of resistor R1, one end of capacitor C23, and pin 22 of chip U4. The other end of capacitor C23 is grounded. The other end of resistor R1 is connected to one end of capacitor C7 and the other end of capacitor C8, and is connected to pin 18 of chip U4. The other end of capacitor C7 is grounded.

[0031] It connects to a dedicated high-precision NTC thermistor probe located within the sample chamber via dedicated interface pins NTC+ and NTC-. The precision constant voltage source built into the U4 chip is used as the excitation source. Compared to traditional solutions, the built-in constant voltage source excitation can generate a voltage reference under the same conditions as the sensor, greatly simplifying the mathematical model of the nonlinear region near the freezing point and improving the linearity and accuracy of the measurement.

[0032] Resistor R4 is connected in series with the NTC sensor, forming a precise voltage divider network. The NTC sensor exhibits extremely high stability throughout its entire operating temperature range, thus ensuring absolute measurement accuracy. An RC low-pass filter, consisting of high-resistance current-limiting resistors R1 and R2 and multiple parallel filter capacitors C7, C8, and C9, is placed before the ADC input pin of chip U4. This effectively attenuates high-frequency noise and limits the input current, providing protection. This multi-stage filtering design ensures maximum signal integrity even in slow-signal scenarios such as freezing point measurements.

[0033] The communication unit includes a connector that brings out the communication bus of the chip U4 through a standardized connector for easy interface with the host system. The connector is connected to the chip U4, pin 2 of the connector is connected to the VIN power supply, and pin 1 of the connector is connected to PGND.

[0034] Key design considerations for high-resolution temperature measurement systems: 1. Dual power supply design: Independent analog (AVDD) and digital (IOVDD) power supplies are implemented through U1 and U3, which fundamentally eliminates the pollution of precision analog measurements by digital noise.

[0035] 2. Ferrite bead source filtering: Ferrite beads L1 and L2 are added at the power input to shield high-frequency interference at the system level, providing a "clean" starting point for the entire measurement link.

[0036] 3. Internal high-precision reference: The constant voltage reference built into the chip U4 is used and stabilized by filtering through C20, C21, and C23, so that the reference source temperature is correlated with the ADC temperature, avoiding system errors caused by chip temperature drift.

[0037] 4. Multi-stage RC filtering: Multi-stage filtering is set at both the signal input terminal (R1, R2, C7, C8, C9) and the power supply terminal (capacitors at the input and output terminals of each regulator) to build a "three-dimensional" anti-interference barrier, ensuring stable readings even in complex electromagnetic environments.

[0038] 5. Differential input architecture: Adopting AIN12 / AIN13 differential input mode, it effectively suppresses common-mode noise and improves the measurement signal-to-noise ratio under weak signals near the freezing point.

[0039] The description of this utility model is given for illustrative and descriptive purposes only, and is not intended to be exhaustive or to limit the utility model to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of the utility model, and to enable those skilled in the art to understand the utility model and design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A high-resolution temperature measurement system for a freezing point osmotic pressure analyzer, characterized in that: It includes an analog-to-digital conversion core unit, which is connected to a power management unit, a signal conditioning and differential sensor interface unit, and a communication unit; The analog-to-digital conversion core unit includes a chip U4, model AD7124-8BCPZ. One end of a capacitor C20 is connected to pin 1 of the chip U4, and the other end of the capacitor C20 is grounded. One end of a capacitor C21 is connected to pin 24 of the chip U4, and the other end of the capacitor C21 is connected to AGND.

2. The high-resolution temperature measurement system for a freezing point osmotic pressure analyzer as described in claim 1, characterized in that: The power management unit includes a power inlet filter network, which includes parallel ferrite beads L1 and L2. One end of ferrite bead L1 is connected to one end of capacitor C2, one end of capacitor C1, and one end of resistor R12, and is connected to the VIN input power supply. The other ends of capacitor C2 and capacitor C1 are connected to PGND. One end of ferrite bead L1 and the other end of resistor R12 are connected to one end of capacitor C3 and capacitor C4, and output a +12V power supply. The other ends of capacitor C3 and capacitor C4 are grounded.

3. The high-resolution temperature measurement system for a freezing point osmotic pressure analyzer as described in claim 1, characterized in that: The power management unit also includes a first-level voltage regulator module, which includes a chip U2, model LP2985A-50DBVR. Pins 1 and 3 of chip U2 are connected to a +12V power supply. Pin 4 of chip U2 is connected to one end of capacitor C16, and the other end of capacitor C16 is grounded. Pin 5 of chip U2 is connected to one end of resistor R6 and connected to a +5V power supply. The other end of resistor R6 is connected to one end of capacitor C17, one end of capacitor C18, and one end of capacitor C19 and connected to a +5V power supply. The other ends of capacitors C17, C18, and C19 are grounded.

4. The high-resolution temperature measurement system for a freezing point osmotic pressure analyzer as described in claim 1, characterized in that: The power management unit also includes a secondary voltage regulator module. The secondary voltage regulator module includes chips U1 and U3, which are ADP150AUJZ-3.3-R7. Pins 1 and 3 of chip U1 are connected to one end of capacitor C22 and connected to a +5V power supply. The other end of capacitor C22 is grounded. Pin 5 of chip U1 is connected to one end of capacitor C5 and one end of capacitor C6 and is connected to pin 2 of chip U4. The other ends of capacitor C5 and capacitor C6 are grounded.

5. The high-resolution temperature measurement system for a freezing point osmotic pressure analyzer as described in claim 4, characterized in that: Pins 1 and 3 of the chip U3 are connected to a +5V power supply. Pin 5 of the chip U3 is connected to one end of capacitor C13, one end of capacitor C14, and one end of capacitor C15, and is connected to the AVDD power supply. The other end of capacitor C13 is connected to ground, and the other ends of capacitor C14 and capacitor C15 are connected to AGND.

6. The high-resolution temperature measurement system for a freezing point osmotic pressure analyzer as described in claim 1, characterized in that: The signal conditioning and differential sensor interface unit includes interface CN1, which is used to connect a high-precision NTC sensor. Pin 1 of interface CN1 is connected to one end of resistor R2 and one end of resistor R4. The other end of resistor R4 is grounded. The other end of resistor R2 is connected to one end of capacitor C9 and one end of capacitor C8, and is connected to pin 19 of chip U4. The other end of capacitor C9 is grounded.

7. The high-resolution temperature measurement system for a freezing point osmotic pressure analyzer as described in claim 6, characterized in that: Pin 2 of interface CN1 is connected to one end of resistor R1, one end of capacitor C23, and pin 22 of chip U4. The other end of capacitor C23 is grounded. The other end of resistor R1 is connected to one end of capacitor C7 and the other end of capacitor C8, and is connected to pin 18 of chip U4. The other end of capacitor C7 is grounded.

8. The high-resolution temperature measurement system for a freezing point osmotic pressure analyzer as described in claim 1, characterized in that: The communication unit includes a connector that brings out the communication bus of chip U4 through a standardized connector to facilitate interface with the host system. Chip U4 is connected to the connector.

Images