Chip test socket probe anomaly detection circuit and system

Abstract

The application discloses a chip test seat probe abnormality detection circuit and system, relates to the technical field of chip testing, and comprises a test circuit board and a detection circuit board. A chip test seat for mounting a chip to be tested is arranged on the test circuit board, a plurality of probes are embedded in the chip test seat, the chip to be tested comprises a plurality of chip signal pins and an electrostatic discharge protection unit connected to each chip signal pin in correspondence, and the first ends of the plurality of probes are connected to the plurality of chip signal pins in one-to-one correspondence. The second ends of the plurality of probes are connected to the detection circuit board respectively, and the detection circuit board detects the voltage between the first end of each probe and the electrostatic discharge protection unit to detect abnormal probes in the chip test seat. The application can quickly and accurately locate abnormal probes of the chip test seat.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip test socket probe anomaly detection circuit and system. Background Technology

[0002] Before a chip product is launched on the market, it needs to be packaged and then subjected to functional testing (FT) and system-level testing (SLT) to verify that there are no problems before it can be launched.

[0003] Both FT and SLT tests require the use of IC sockets. The main function of IC sockets is to connect and conduct, and they are used for functional verification of integrated circuit applications. They are static connectors between printed circuit boards (PCBs) and chips (ICs), making chip replacement and testing more convenient without having to repeatedly solder and remove the chip.

[0004] Chip test sockets embed probes to connect chips to printed circuit boards. The number of probes on a chip test socket is determined by the number of signal pins on the chip under test. During use, probe malfunctions can prevent the chip from being tested correctly. This is especially problematic when the chip test socket is used to test chips with a large number of signal pins, as there is often no timely and effective way to quickly locate the damaged probe, impacting chip testing yield and efficiency, and increasing testing costs.

[0005] How to quickly locate abnormal probes in chip test sockets and improve the efficiency of chip testing is a technical problem that needs to be solved. Utility Model Content

[0006] The purpose of this application is to provide a chip test socket probe anomaly detection circuit and system to solve the problem of the inability to quickly locate abnormal probes in chip test sockets.

[0007] To solve the above-mentioned technical problems, this specification is implemented as follows: In the first aspect, a chip test socket probe anomaly detection circuit is provided, including a test circuit board and a detection circuit board; The test circuit board is provided with a chip test socket for mounting the chip under test. Multiple probes are embedded inside the chip test socket. The chip under test includes multiple chip signal pins and electrostatic discharge protection units connected to each chip signal pin. The first ends of the multiple probes are connected to the multiple chip signal pins one by one. The detection circuit board is connected to the second end of the plurality of probes respectively. The detection circuit board detects the voltage between the first end of each probe and the electrostatic discharge protection unit in order to detect abnormal probes in the chip test socket.

[0008] Optionally, the detection circuit board includes a current source and a voltage sampling unit; A current source is connected to the second end of the target probe to output a constant current to the target probe; A voltage sampling unit is connected to the second end of the target probe to detect the voltage between the first end of the target probe and the electrostatic discharge protection unit of the corresponding connected target chip signal pin.

[0009] Optionally, the detection circuit board further includes an overvoltage protection unit, the first end of which is connected to the second end of the target probe, and the second end of which is grounded.

[0010] Optionally, the overvoltage protection unit includes a current-limiting resistor and a Zener diode; The first end of the current-limiting resistor is connected to the second end of the target probe, and the second end of the current-limiting resistor is connected to the Zener diode; The first terminal of the Zener diode is connected to the second terminal of the current-limiting resistor, and the second terminal of the Zener diode is grounded.

[0011] Optionally, the electrostatic discharge protection unit includes a first diode and a second diode, wherein the positive terminal of the first diode is connected to the negative terminal of the second diode, the negative terminal of the first diode is connected to the power supply voltage, and the positive terminal of the second diode is grounded; The first end of the target chip signal pin is connected to the second end of the target probe, and the second end of the target chip signal pin is connected to the positive terminal of the first diode.

[0012] Optionally, the test circuit board includes a chip power supply unit, a chip test unit circuit switching unit, and a control unit. The control unit is connected to the chip power supply unit and outputs an enable signal to the chip power supply unit to control the chip power supply unit to output power voltage or not output power voltage. The control unit is also connected to the circuit switching unit and outputs a control signal to the circuit switching unit to control the circuit switching unit to be turned on or off. The circuit switching unit is disposed between the chip power supply unit and the target chip power supply pin corresponding to the target chip signal pin, and the chip testing unit is connected between the chip power supply unit and the target chip signal pin; The circuit switching unit switches the connection between the chip power supply unit and the power supply pin of the target chip, the power supply pin of the target chip is connected to the power supply voltage, and the chip testing unit outputs a test signal to the signal pin of the target chip; The circuit switching unit switches the chip power supply unit to disconnect from the target chip power supply pin, and the target chip power supply pin is grounded.

[0013] Optionally, the circuit switching unit includes a switching relay and a MOSFET; The first terminal of the MOSFET is connected to the switching relay, and the second terminal of the MOSFET is connected to the control unit to receive the control signal from the control unit; The first terminal of the switching relay is connected to the first terminal of the MOS transistor, the second terminal of the switching relay is connected to the power supply pin of the target chip, the third terminal of the switching relay is connected to the power supply unit of the chip, and the fourth terminal of the switching relay is grounded.

[0014] Optionally, the switching relay includes a switching module and a relay coil; The switch module includes a common contact, a normally open contact, and a normally closed contact. The common contact is connected to the power supply pin of the target chip, the normally open contact is grounded, and the normally closed contact is connected to the chip power supply unit. The relay coil includes a first coil pin and a second coil pin. The first coil pin is connected to the relay power supply unit, and the second coil pin is connected to the first end of the MOS transistor.

[0015] Optionally, the circuit switching unit further includes a freewheeling diode, which is disposed between the first terminal of the MOS transistor and the relay power supply unit.

[0016] In a second aspect, a chip test socket probe anomaly detection system is provided, including a host computer; and a chip test socket probe anomaly detection circuit as described in the first aspect above. The host computer is connected to the test circuit board through a preset communication interface and outputs a chip test socket detection command to the test circuit board to establish the connection between the second ends of the multiple probes of the chip test socket and the test circuit board.

[0017] In this embodiment, the chip test socket probe anomaly detection circuit includes a test circuit board and a detection circuit board. The test circuit board has a chip test socket for mounting the chip under test (DUT). Multiple probes are embedded inside the chip test socket. The DUT includes multiple chip signal pins and electrostatic discharge (ESD) protection units corresponding to each chip signal pin. The first ends of the multiple probes are connected one-to-one to the multiple chip signal pins. The detection circuit board is connected to the second ends of each of the multiple probes. The detection circuit board detects the voltage between the first end of each probe and the ESD protection unit to detect abnormal probes in the chip test socket. Therefore, the voltage between the probe and the ESD protection unit (the voltage of the chip signal pins) can be detected, and based on whether the detected voltage is abnormal, the abnormal probe among the multiple probes of the chip test socket can be quickly and accurately located, thereby improving chip testing yield and efficiency and reducing chip testing costs. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a block diagram of the chip test socket probe anomaly detection circuit according to an embodiment of this application.

[0019] Figure 2 This is a block diagram of the structure of the detection circuit board according to an embodiment of this application.

[0020] Figure 3 This is a circuit diagram of a detection circuit board according to a specific embodiment of this application.

[0021] Figure 4 This is a structural block diagram of the chip test socket probe anomaly detection system according to an embodiment of this application.

[0022] Figure 5 This is a circuit diagram of a test circuit board according to a specific embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the chip test socket probe anomaly detection process according to an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The drawing numbers in this application are only used to distinguish the various steps in the solution and are not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0025] As chip development accelerates and functionality becomes increasingly complex, chip testing demands higher reliability and shorter testing times to bring products to market quickly. After chip packaging, functional testing (FT) and system-level testing (SLT) are performed to verify the chip's integrity before it can be released to the market.

[0026] FT testing primarily verifies the electrical characteristics of a chip, identifying defective chips and verifying packaging yield and the manufacturing process of the packaging plant. SLT testing mainly tests whether the specific modules of the chip function correctly.

[0027] Both FT and SLT testing require IC sockets, which are critical components in the semiconductor manufacturing process. The primary function of an IC socket is to provide electrical conductivity, used for functional verification of integrated circuit applications. It acts as a static connector between the printed circuit board (PCB) and the IC, making chip replacement and testing more convenient. This eliminates the need for repeated soldering and removal of the chip, reducing damage between the chip and the PCB and achieving faster and more efficient testing.

[0028] A chip test socket contains a number of probes used to connect the chip to the printed circuit board (PCB). The number of probes is determined by the number of signal pins on the chip under test, typically several hundred. During use, the probes often lose elasticity or fail to spring back up after being pressed, leading to abnormal contact between the chip and the PCB and affecting functional testing. Probe malfunctions can prevent the chip from being tested properly. When using a chip test socket to test chips with a large number of signal pins, if one or more probes become damaged during testing, there is usually no quick and effective way to locate the damaged probe.

[0029] Chip testing demands short testing times and high speeds. If probe damage occurs during testing, it leads to the failure of both FT and SLT verification tests, consequently impacting chip testing yield and efficiency, and increasing testing costs. Therefore, quickly locating abnormal probes in chip test sockets and improving chip testing efficiency are key technical problems that need to be solved.

[0030] To address the problems existing in the prior art, this application provides a solution for a chip test socket probe anomaly detection circuit and system, including a test circuit board and a detection circuit board. The test circuit board is equipped with a chip test socket for mounting a chip under test (DUT). Multiple probes are embedded within the chip test socket. The DUT includes multiple chip signal pins and electrostatic discharge (ESD) protection units corresponding to each chip signal pin. The first ends of the multiple probes are connected one-to-one with the multiple chip signal pins. The detection circuit board is connected to the second ends of each of the multiple probes. The detection circuit board detects the voltage between the first end of each probe and the ESD protection unit to detect abnormal probes in the chip test socket. Therefore, the voltage between the probe and the ESD protection unit (the voltage of the chip signal pins) can be detected, and based on whether the detected voltage is abnormal, the abnormal probe among the multiple probes of the chip test socket can be quickly and accurately located, thereby improving chip testing yield and efficiency and reducing chip testing costs.

[0031] In one embodiment of this application, a chip test socket probe anomaly detection circuit is proposed, such as... Figure 1 As shown, it includes a test circuit board 100 and a detection circuit board 200; The test circuit board 100 is provided with a chip test socket 400 for mounting the chip under test. The chip test socket 400 has multiple probes 320 embedded inside. The chip under test includes multiple chip signal pins 422 and electrostatic discharge protection units 440 connected to each chip signal pin 422. The first ends of the multiple probes 320 are connected to the multiple chip signal pins 422 one by one. The detection circuit board 200 is connected to the second ends of the multiple probes 322 respectively. The detection circuit board 200 detects the voltage between the first end of each probe 320 and the electrostatic discharge protection unit 440 to detect abnormal probes in the chip test socket 400.

[0032] The test circuit board 100 is used to perform normal tests on the chip after chip packaging is completed, including FT test and SLT test. The test circuit board 100 may be a printed circuit board, providing electrical connections for various electronic components mounted on the test circuit board 100.

[0033] The chip test socket 400 generally consists of a base and a cover. A plurality of probes 320 are embedded inside the base, and the number of the probes 320 is determined by the number of chip signal pins of the chip to be tested, which is equal to the number of the chip signal pins to be tested of the chip. First ends of the plurality of probes 320 are connected to the plurality of chip signal pins of the chip to be tested in a one-to-one correspondence, and pads on the test circuit board 100 are further connected to the chip to be tested through the probes 320. The chip to be tested is placed above the base of the chip test socket 400, and the cover is used to fix the position of the chip to be tested. The probes 320 are generally of a straight up-and-down structure, and the inside of each probe 320 has elasticity, which provides contact force support for the contact of the chip to be tested, reduces contact impedance, and increases the stability of the contact surface in contact with the probe.

[0034] The chip to be tested includes a plurality of chip signal pins 422, and each chip signal pin 422 has a corresponding chip function. When testing the chip, it is necessary to test each of the chip signal pins 422 respectively, so as to test whether the function of the corresponding chip signal pin 422 is qualified.

[0035] To prevent the large voltage generated by instantaneous static electricity from damaging the internal circuit of the chip to be tested, each chip signal pin 422 of the chip to be tested is correspondingly connected with an electrostatic discharge protection unit 440, that is, each chip signal pin 422 is correspondingly connected with one electrostatic discharge protection unit 440, which aims to prevent electrostatic discharge from causing damage to the chip to be tested, and avoid a large amount of current flowing into the interior of the chip to be tested when static electricity is generated, resulting in chip damage. After the chip to be tested is connected to a corresponding power supply voltage or a constant current, each chip signal pin 422 and the correspondingly connected electrostatic discharge protection unit 440 form a current path.

[0036] in conjunction with Figure 1 , one end of one probe 320 is connected to the test circuit board 100, the other end of the probe 320 is connected to one chip signal pin 422, and at the same time, the chip signal pin 422 is connected to one electrostatic discharge protection unit 440. The test circuit board 100 outputs a test signal to the chip signal pin 422 connected to the other end of the probe 320 through the connected probe 320, so as to perform a corresponding test on the chip signal pin 422. Moreover, during the test process of the chip signal pin 422, the electrostatic discharge protection unit 440 forms a current path with the chip signal pin 422 to perform electrostatic discharge protection on the chip signal pin 422.

[0037] The detection circuit board 200 is configured to detect abnormal probes among the plurality of probes 320 correspondingly connected to the plurality of chip signal pins 422 of the chip to be tested on the chip test socket 400, that is, the probes 320 with abnormal conditions such as deteriorated elasticity due to increased use times or failure to bounce up after being pressed. The detection circuit board 200 is connected to the second ends of the plurality of probes 320 respectively, that is, each probe 320 is correspondingly connected to one detection circuit board 200.

[0038] Continue to refer to Figure 1 One end of a probe 320 is also connected to a detection circuit board 200. The detection circuit board 200 can form a current path with the chip signal pin 422 and the electrostatic discharge protection unit 440 connected to the chip signal pin 422, and is used to detect the voltage between the probe 320 and the electrostatic discharge protection unit 440, that is, to detect the voltage of the chip signal pin 422. Therefore, based on the detected voltage of the chip signal pin 422, it can be determined whether the probe 320 is abnormal.

[0039] Normally, the voltage of probe 320 is within the normal voltage range under normal circumstances. If it exceeds the normal voltage range, probe 320 can be judged as an abnormal probe.

[0040] In this embodiment, for each probe 320 of the chip test socket 400, a detection circuit board is connected to the end away from the connection between the probe 320 and the chip signal pin 422, and is used to detect the voltage of the corresponding chip signal pin 422. Each probe 320 can be distinguished by a number, and the correlation between each detection circuit board 200 and the connected probe 320 is pre-recorded.

[0041] Therefore, based on the detection voltage of the chip signal pin 422, it is possible to determine whether each probe is abnormal. Based on the abnormal probe number, the location of the abnormal probe among multiple probes 320 can be quickly and accurately located. By quickly locating abnormal probes in the chip test socket, chip testing yield and efficiency can be improved, and chip testing costs can be reduced.

[0042] In one specific embodiment of this application, such as Figure 2 As shown, the detection circuit board 200 includes a current source 240 and a voltage sampling unit 220; the current source 240 is connected to the second end of the target probe 320 to output a constant current to the target probe 320; the voltage sampling unit 220 is connected to the second end of the target probe 320 to detect the voltage between the first end of the target probe 320 and the electrostatic discharge protection unit 440 of the corresponding connected target chip signal pin 422.

[0043] Combination Figure 3 As can be seen from a circuit example of a detection circuit board 200, the current source 240 is connected to the probe 320 and is used to output a constant current i when detecting an abnormal probe. The constant current i flows through the probe 320, the chip signal pin 422 and the electrostatic discharge protection unit 440, forming a current path and generating a corresponding voltage at both ends of each component.

[0044] The voltage sampling unit 220 is connected to the probe 320 to detect the voltage at the corresponding connection end of the probe 320. The voltage drop of the probe 320 is also fixed when the constant current i is fixed. Therefore, by detecting the voltage at the corresponding connection end of the probe 320, the voltage between the probe 320 and the end connected to the electrostatic discharge protection unit 440, that is, the voltage on the chip signal pin 422, can be detected.

[0045] In one embodiment, the voltage sampling unit 220 is, for example, an analog-to-digital converter (ADC) that acquires the analog voltage value at the corresponding connection terminal of the probe 320 and obtains the corresponding digital voltage value through analog-to-digital conversion.

[0046] Optionally, combined Figure 2 and Figure 3 The detection circuit board 200 also includes an overvoltage protection unit 260, the first end of which is connected to the second end of the target probe 320, and the second end of which is grounded.

[0047] The overvoltage protection unit 260 performs voltage clamping, ensuring that the voltage on the probe 320 does not exceed a preset voltage threshold, such as the voltage of the voltage sampling unit 220, and also protects the chip signal pin 422 from overvoltage damage.

[0048] Combination Figure 1 The probe 320 also serves as a module connecting the test circuit board 100 and the detection circuit board 200. In addition to performing chip testing, the test circuit board 100 can also lead out the signal pins 422 of each chip to be tested to the chip test point area 460 (e.g., ...). Figure 4 As shown in the figure, it is convenient to connect to the detection circuit board 200 via probe 320.

[0049] In one specific embodiment, such as Figure 3 As shown, the overvoltage protection unit 260 includes a current-limiting resistor R1 and a Zener diode D31; the first end of the current-limiting resistor R1 is connected to the second end of the target probe 320, and the second end of the current-limiting resistor R1 is connected to the Zener diode D31; the first end of the Zener diode D31 is connected to the second end of the current-limiting resistor R1, and the second end of the Zener diode D31 is grounded.

[0050] The current-limiting resistor R1 and the Zener diode D31 work together to provide a stable voltage, which is used to realize the voltage clamping function of the chip signal pin 422.

[0051] When a contact abnormality occurs at the probe 320 connected to the target chip signal pin 422, the impedance R between the probe 320 and the pad connected to the test circuit board 100 increases, or there is a possibility of an open circuit. At this time, the voltage Vf detected by the voltage sampling unit 220 is Vf = i*R. The larger R is, the larger Vf is. If the Vf value exceeds the preset voltage threshold, such as the detection range of the voltage sampling unit 220, it may damage the voltage sampling unit 220. By adding an overvoltage protection unit 260 composed of a current-limiting resistor R1 and a Zener diode D31 to the detection circuit board 200 for voltage regulation, the voltage value on the detection circuit board can be ensured to be within the detection range of the overvoltage protection unit 260. The stable voltage value is determined by the voltage sampling unit 220 and the chip under test, ensuring that the stable voltage will not damage the voltage sampling unit 220 and the chip signal pin 422.

[0052] As shown above, the electrostatic discharge protection unit 440 is used to prevent electrostatic discharge from damaging the chip under test and to avoid a large amount of current flowing into the chip under test when the voltage is too high, which would cause chip damage.

[0053] Combination Figure 3 Optionally, in one specific embodiment of this application, the electrostatic discharge protection unit 440 includes a first diode D11 and a second diode D21. The positive terminal of the first diode D11 is connected to the negative terminal of the second diode D21. The negative terminal of the first diode D11 is connected to a power supply voltage, and the positive terminal of the second diode D21 is grounded. The first end of the target chip signal pin 422 is connected to the second end of the target probe 320, and the second end of the target chip signal pin 422 is connected to the positive terminal of the first diode D11.

[0054] The first diode D11 and the second diode D21 constitute the electrostatic discharge protection unit 440, which is a diode inside the chip used for electrostatic discharge protection. Based on the unidirectional conduction characteristics of the first diode D11 and the second diode D21 in the electrostatic discharge protection unit 440, when detecting abnormal probes in the chip test socket, a constant current i is applied to the signal pin 422 of the target chip, and the presence of contact abnormalities in the corresponding probes in the chip test socket is determined according to the on-state voltage drop range.

[0055] In actual testing, the chip power supply pin 432 is first connected to ground (GND). The current source 240 outputs a positive constant current i. If the corresponding probe 320 makes normal contact, the constant current i flows through the probe 320 to the chip signal pin 422, and then through the first diode D11 to ground. At this time, the voltage sampling unit 220 detects the voltage value as the conduction voltage of the first diode D11, i.e., voltage Vf. The value of the conduction voltage will vary between 0.3-0.8V due to differences in manufacturing process.

[0056] If the probe 320 makes an abnormal contact, the impedance R between the probe 320 and the pads of the test circuit board 100 will increase or there will be an open circuit. The voltage Vf detected by the voltage sampling unit 220 is i*R. At this time, the voltage Vf is greater than the maximum value of the conduction voltage range, for example, 0.8V.

[0057] Therefore, the function of the detection circuit board 200 is to provide a constant current i to each chip signal pin 422 and then detect the voltage Vf on each chip signal pin 422, which is the forward voltage of the first diode D11. If the voltage Vf is within the range of the forward voltage, for example, between 0.3-0.8V, the corresponding probe 320 is considered to have normal contact; if the voltage Vf is between the voltage value exceeding the forward voltage range and the stable voltage Vc, the corresponding probe 320 is considered to have abnormal contact.

[0058] For a chip under test with multiple chip signal pins 422, it is only necessary to connect a detection circuit board 200 to each chip signal pin 422 through probe 320.

[0059] like Figure 3 As shown, the detection circuit board 200 also includes a control unit 290, which is, for example, a microprocessor unit (MCU).

[0060] The control unit 290 connects to the host computer 500, enabling communication between the detection circuit board 200 and the host computer 500. Internally, it connects to the voltage sampling unit 220 to acquire the voltage of the chip signal pin 422 and determine whether there are any contact abnormalities or other problems with the corresponding probe 320 connected to the chip test socket. The voltage sampling unit 220 is controlled by the control unit 290 and acquires the voltage on the corresponding chip signal pin 422. The current source 240 is controlled by the chip signal pin 422 and outputs a constant current i when a probe abnormality is detected.

[0061] The control unit 290 is used to read the voltage value detected by the voltage sampling unit 220 and determine whether there is a contact abnormality problem of the probe 320 corresponding to the chip signal pin 422 based on the read voltage value.

[0062] The test circuit board 100 can be used together with the detection circuit board 200 for probe anomaly detection in the chip test socket where the chip under test is located. The test circuit board 100 can also be used alone for normal testing of the chip under test, and can switch between normal testing and probe anomaly detection as needed.

[0063] Optionally, such as Figure 4As shown, the test circuit board 100 includes a chip power supply unit 430, a chip testing unit 420, a circuit switching unit 120, and a control unit 190. The control unit 190 is connected to the chip power supply unit 430 and outputs an enable signal to the chip power supply unit 430 to control the chip power supply unit 430 to output power voltage or not output power voltage. The control unit 190 is also connected to the circuit switching unit 120 and outputs a control signal to the circuit switching unit 120 to control the circuit switching unit 120 to be turned on or off. The circuit switching unit 120 is disposed between the chip power supply unit 430 and the target chip power supply unit 430. Between the chip signal pin 422 and the target chip power supply pin 432, the chip test unit 420 is connected between the chip power supply unit 430 and the target chip signal pin 422; the circuit switching unit 120 switches the chip power supply unit 430 to connect to the target chip power supply pin 432, the target chip power supply pin 432 is connected to the power supply voltage, and the chip test unit 420 outputs a test signal to the target chip signal pin 422; the circuit switching unit 120 switches the chip power supply unit 430 to disconnect from the target chip power supply pin 432, and the target chip power supply pin 432 is grounded.

[0064] Normal testing of the chip under test (DUT) is performed independently by the test circuit board 100. When the chip test reaches a certain number of cycles, probe contact detection of the chip test socket is required. Alternatively, if an anomaly occurs during testing of the DUT and it needs to be investigated whether the anomaly is due to probe contact issues with the chip test socket, the system switches to probe anomaly detection of the chip test socket, and the detection circuit board 200 is connected to the test circuit board 100. During normal chip testing, the detection circuit board is not connected to the DUT.

[0065] Specifically, such as Figure 4 As shown, the test circuit board 100 includes a chip test socket 400 for the chip under test (DUT), a chip power supply unit 430, a chip test unit 420, a circuit switching unit 120, and a control unit 190. The chip power supply unit 430 is connected to the chip power pin 432 of the DUT via PCB traces, providing power voltage to the corresponding chip signal pin 422. Multiple chip power pins 432 of the DUT can also be routed to the chip test point area 460 via traces. The chip power supply unit 430 is also connected to the chip test unit 420, providing power voltage to the chip test unit 420.

[0066] The chip test unit 420 is connected between the chip power supply unit 430 and the corresponding chip signal pin 422. The chip test unit 420 is a peripheral module related to the testing of the chip under test, used for functional testing and / or system-level testing of the corresponding chip power supply pin 422. Multiple chip power supply pins 432 of the chip under test can also be led to the chip test point area 460 through traces. The test circuit board 200 is connected to the corresponding chip signal pin 422 in the chip test point area 460 through probes and PCB traces.

[0067] The control unit 190 is, for example, a microprocessor unit (MCU). The control unit 190 is connected to the chip power supply unit 430 and is used to control the chip power supply unit 430 to turn on and off, that is, to control the chip power supply unit 430 to output power voltage or not output power voltage.

[0068] When the control unit 190 controls the chip power supply unit 430 to output power voltage, the chip test unit 420 performs normal testing on the corresponding chip signal pin 422. When the control unit 190 controls the chip power supply unit 430 not to output power voltage, the detection circuit board 200 performs abnormal detection on the probe 320 connected to the chip signal pin 422 of the chip under test.

[0069] The circuit switching unit 120 is located between the chip power supply unit 430 and the chip power supply pin 432 corresponding to the chip signal pin 422. Correspondingly, the control unit 190 is also connected to the circuit switching unit 120 and outputs a control signal to the circuit switching unit 120 to control the circuit switching unit 120 to be turned on or off.

[0070] In one embodiment, when the control circuit switching unit 120 of the control unit 190 is not turned on, the chip testing unit 420 performs normal testing on the chip signal pin 422 of the chip under test. When the control circuit switching unit 120 of the control unit 190 is turned on, the detection circuit board 200 performs abnormal detection on the probe 320 connected to the chip signal pin 422 of the chip under test.

[0071] During normal testing of the chip signal pin 422 of the chip under test, the control circuit switching unit 120 switches the chip power supply unit 430 to the corresponding chip power supply pin 432. The chip power supply pin 432 is connected to the power supply voltage provided by the chip power supply unit 430, and the chip test unit 420 outputs a test signal to the chip signal pin 422.

[0072] When performing a probe abnormality test on the chip signal pin 422 of the chip under test, the control circuit switching unit 120 switches the chip power supply unit 430 to disconnect from the corresponding chip power supply pin 432. The chip power supply unit 430 stops providing power voltage, the chip power supply pin 432 is grounded, and the detection circuit board 200 outputs a constant current to the chip signal pin 422.

[0073] In this embodiment, one chip signal pin 422 corresponds to one chip power supply unit 430, one chip test unit 420, and one circuit switching unit 120. The chip power supply unit 430 is connected to an input voltage Vin to generate a corresponding power supply voltage.

[0074] Combination Figure 5 In one embodiment, for example, the chip under test 600 includes n chip signal pins 422, and each chip signal pin 422 is connected to a circuit structure including a chip power supply unit 430, a chip test unit 420 and a circuit switching unit 120.

[0075] like Figure 5 As shown, the chip power supply unit 430 includes, for example, n chip power supply units VCC1 to VCCn, and the chip power supply pins 432 include, for example, n chip power supply pins POWER1 to POWERn.

[0076] The chip power supply units VCC1 to VCCn are connected to the circuit switching unit 120 one by one, and the circuit switching unit 120 is connected to the chip power supply pins POWER1 to POWERn one by one.

[0077] A control unit 190 is connected to n chip power supply units to output corresponding enable signals EN1 to ENn; a control unit 190 is connected to n circuit switching units 120 to output corresponding control signals.

[0078] In one specific embodiment, the circuit switching unit 120 includes a switching relay and a MOSFET; the first terminal of the MOSFET is connected to the switching relay, and the second terminal of the MOSFET is connected to the control unit 190 to receive control signals from the control unit 190; the first terminal of the switching relay is connected to the first terminal of the MOSFET, the second terminal of the switching relay is connected to the power supply pin 432 of the target chip, the third terminal of the switching relay is connected to the chip power supply unit 430, and the fourth terminal of the switching relay is grounded.

[0079] Combination Figure 5 For example, n circuit switching units 120 correspond one-to-one with n switching relays K1 to Kn, and n MOS transistors (metal-oxide-semiconductor field-effect transistors) Q1 to Qn.

[0080] The control unit 190 controls each chip power supply unit to output power voltage or not output power voltage by sending enable signals to each chip power supply unit; and controls the connection or disconnection between each switching relay and the corresponding chip power supply unit by sending control signals to each MOSFET.

[0081] Specifically, in one embodiment, such as Figure 5 As shown, the switch relay includes a switch module and a relay coil; the switch module includes a common contact 3, a normally open contact 4, and a normally closed contact 5. The common contact 3 is connected to the power supply pin 432 of the target chip, the normally open contact 4 is grounded, and the normally closed contact 5 is connected to the chip power supply unit 430; the relay coil includes a first coil pin 1 and a second coil pin 2. The first coil pin 1 is connected to the relay power supply unit Vdd, and the second coil pin 2 is connected to the first end of the MOS transistor.

[0082] Combination Figure 5 For example, each switch relay includes a switch module and a relay coil. Taking switch relay K1 as an example, the switch module includes a common contact 3, a normally open contact 4, and a normally closed contact 5. The chip power supply pin 432 corresponding to the common contact 3 is connected, the normally open contact 4 is grounded, and the normally closed contact 5 is connected to the corresponding chip power supply unit 430.

[0083] One end of the relay coil is connected to the MOSFET, and the other end is connected to the relay power supply unit Vdd, which supplies power to the relay coil.

[0084] The MOSFET Q1 can be an NMOS transistor, a PMOS transistor, or other transistors with the same function.

[0085] Whether the chip power supply unit 430 on the test circuit board 100 provides power supply voltage is controlled by the control unit 190 through the output enable signal; whether the power supply provided on each chip signal pin 422 of the chip under test is the power supply voltage output by the chip power supply unit 430 or the constant voltage provided by the current source 240 is controlled by the circuit switching unit 120, which is controlled by the control unit 190 through the output relay control signal to the MOSFET Q1.

[0086] For example Figure 5 In the circuit switching unit 120, the control unit 190 can output relay control signals 1 to 2 to 3 to 4 to 5 corresponding to the MOS transistors Q1 to Qn in each circuit switching unit 120.

[0087] In one embodiment, the circuit switching unit 120 further includes a freewheeling diode D1, which is disposed between the first terminal of the MOS transistor Q1 and the relay power supply unit Vdd.

[0088] like Figure 5As shown, D1 to Dn are freewheeling diodes located across the power supply terminals of each relay. Their main function is to provide freewheeling protection when the control unit 190 controls the switching relays to close. Each NMOS transistor is used to turn the switching relays on or off, and the control unit 190 indirectly controls the switching relays through each NMOS transistor.

[0089] Specifically, the control unit 190 controls the on / off state of the corresponding chip power supply units VCC1 to VCCn respectively through the enable signals EN1 to ENn, thereby controlling the on / off state of the power supplied by the chip power supply units VCC1 to VCCn to each chip power supply pin of the chip under test, that is, controlling the on / off state of the power supplied to each chip signal pin 422.

[0090] When the chip under test 600 needs to be powered on for testing, the control unit 190 controls the relay control signals 1 to n to output a low level. At this time, the switching relays K1 to Kn maintain their default state, that is, the normally closed contact 5 remains connected to the corresponding chip power supply unit VCC1 to VCCn. Furthermore, the NMOS transistors Q1 to Qn are not turned on, and the switching relays K1 to Kn are not activated. At this time, the common contact 3 of the switching relays K1 to Kn is connected to the normally closed contact 5.

[0091] The control unit 190 controls the enable signals EN1 to ENn to output a high level. At this time, each chip power supply unit VCC1 to VCCn turns on the power supply and outputs the corresponding power supply voltage to the chip power supply pins POWER1 to POWERn of the chip under test 600, so that the chip under test 600 can realize the normal power-on test function.

[0092] When it is necessary to detect abnormalities of probe 320 on the chip test socket, the host computer 500 sends a chip test socket detection command to the test circuit board 100. After receiving the chip test socket command from the host computer 500, the control unit 190 controls the enable signals EN1 to ENn to output a low level. At this time, the power supply of each chip power supply unit VCC1 to VCCn is turned off. At the same time, the control unit 190 controls the relay control signal 1 to relay control signal n to output a high level, the NMOS transistors Q1 to Qn are turned on, and the switching relays K1 to Kn are turned on.

[0093] At this time, the common contact 3 of the switching relays K1 to Kn is connected to the normally closed contact 4, and the power supply pins POWER1 to POWERn of the chip under test 600 are grounded. Meanwhile, the signal pin 422 of the chip under test 600, in addition to connecting to the chip test unit 420, also connects to... Figure 4The probes 320 in the chip test point area 460 are connected to detect the connection between the test circuit board 200 and the test circuit board 100. At this time, the current source 240 of the test circuit board 200 supplies power to the corresponding chip signal pin 422, and the voltage of the chip signal pin 422 is used to detect whether the corresponding probe 320 is abnormal.

[0094] In this embodiment, the chip test socket probe anomaly detection circuit includes a test circuit board and a detection circuit board. The test circuit board has a chip test socket for mounting the chip under test (DUT). Multiple probes are embedded inside the chip test socket. The DUT includes multiple chip signal pins and electrostatic discharge (ESD) protection units corresponding to each chip signal pin. The first ends of the multiple probes are connected one-to-one to the multiple chip signal pins. The detection circuit board is connected to the second ends of each of the multiple probes. The detection circuit board detects the voltage between the first end of each probe and the ESD protection unit to detect abnormal probes in the chip test socket. Therefore, the voltage between the probe and the ESD protection unit (the voltage of the chip signal pins) can be detected, and based on whether the detected voltage is abnormal, the abnormal probe among the multiple probes of the chip test socket can be quickly and accurately located, thereby improving chip testing yield and efficiency and reducing chip testing costs.

[0095] Optionally, embodiments of this application also provide a chip test socket probe anomaly detection system, such as... Figure 4 and Figure 5 As shown, this includes the host computer 500; and as... Figures 1 to 5 The chip test socket probe anomaly detection circuit described in any one of the embodiments; The host computer 500 is connected to the test circuit board 100 through a preset communication interface, and outputs a chip test socket detection command to the test circuit board 100 to connect the second ends of the multiple probes of the chip test socket to the detection circuit board 200.

[0096] The host computer 500 is typically a personal computer (PC). It connects to the chip under test (DUT) 600 via a serial port or USB interface. The host computer 500 receives and displays the test verification results sent by the DUT 600, and records each test result of the DUT 600. The host computer 500 is also connected to the detection circuit board 200. When a probe malfunctions in the chip test socket, the host computer 500 can control the detection circuit board 200 to perform voltage detection on the connection status of the chip signal pin 422 of the chip test socket and upload the voltage detection result to the host computer 500.

[0097] The following is combined Figure 6 The working principle of the chip test socket probe anomaly detection system according to the embodiments of this application is described.

[0098] like Figure 6 As shown, it includes the following steps: Step 12: The Design under Test (DUT) test board (i.e., the test circuit board 100 of the chip under test 600) and the detection module (i.e., the detection circuit board 200) are connected to the host computer 500. Step 14: Determine whether the number of DUT tests is greater than or equal to the preset number n. If so, it means that the DUT has reached a certain number of tests n and the chip test socket (Socket) probe contact detection is required. Proceed to step 16; otherwise, end. Step 16: The host computer 500 sends a Socket probe contact anomaly detection command to the DUT test board; Step 18: The MCU (i.e. control unit 190) on the DUT test board receives the test command. After receiving the test command, the MCU controls the switch relay to ground the chip power supply pin. After the grounding is completed, the MCU uploads the execution result to the host computer. Step 20: The host computer 500 sends a Socket probe contact anomaly detection command to the MCU (i.e., control unit 290) of the detection module; Step 22: The DUT test board and the detection module are connected via probe 320. The DUT signal pins can be connected to the test points of the detection module via the probes. The probe numbers of the detection module correspond one-to-one with the DUT signal pin numbers. Step 24: The MCU on the detection module controls the current source 240 to output a constant current i to the DUT signal pin (i.e., chip signal pin 422), controls the voltage sampling unit 220 to detect the voltage of the DUT signal pin, and reads the voltage on the DUT signal pin from the voltage sampling unit 220; Step 26: The MCU on the detection module determines whether the voltage Vf value on each DUT signal pin is outside the conduction voltage range, for example, between 0.8V and the stable voltage Vc. If it is within the conduction voltage range, for example, between 0.3V and 0.8V, the connection between the socket probe and the PCB pad is considered normal. If the voltage Vf value is outside the conduction voltage range, for example, between 0.8V and the stable voltage Vc, the contact between the socket probe and the PCB pad is considered abnormal, and the socket probe corresponding to the current DUT signal pin needs to be replaced.

[0099] Step 28: The detection module feeds back the DUT signal pin when the voltage Vf exceeds the conduction voltage range, for example, greater than 0.8V, to the host computer 500. Step 30: The host computer 500 displays the detection results of the Socket contact abnormality and the number of the Socket probe that needs to be replaced, so as to locate the corresponding abnormal probe position.

[0100] It is understood that the chip test socket probe anomaly detection circuit in the chip test socket probe anomaly detection system provided in the embodiments of this specification can achieve... Figures 1 to 5 The various processes implemented in the embodiments will not be described again here to avoid repetition.

[0101] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip test socket probe anomaly detection circuit, characterized in that, Includes test circuit boards and inspection circuit boards; The test circuit board is provided with a chip test socket for mounting the chip under test. Multiple probes are embedded inside the chip test socket. The chip under test includes multiple chip signal pins and electrostatic discharge protection units connected to each chip signal pin. The first ends of the multiple probes are connected to the multiple chip signal pins one by one. The detection circuit board is connected to the second end of the plurality of probes respectively. The detection circuit board detects the voltage between the first end of each probe and the electrostatic discharge protection unit in order to detect abnormal probes in the chip test socket.

2. The circuit according to claim 1, characterized in that, The detection circuit board includes a current source and a voltage sampling unit; A current source is connected to the second end of the target probe to output a constant current to the target probe; A voltage sampling unit is connected to the second end of the target probe to detect the voltage between the first end of the target probe and the electrostatic discharge protection unit of the corresponding connected target chip signal pin.

3. The circuit according to claim 2, characterized in that, The detection circuit board also includes an overvoltage protection unit, the first end of which is connected to the second end of the target probe, and the second end of the overvoltage protection unit is grounded.

4. The circuit according to claim 3, characterized in that, The overvoltage protection unit includes a current-limiting resistor and a Zener diode; The first end of the current-limiting resistor is connected to the second end of the target probe, and the second end of the current-limiting resistor is connected to the Zener diode; The first terminal of the Zener diode is connected to the second terminal of the current-limiting resistor, and the second terminal of the Zener diode is grounded.

5. The circuit according to claim 2, characterized in that, The electrostatic discharge protection unit includes a first diode and a second diode. The positive terminal of the first diode is connected to the negative terminal of the second diode. The negative terminal of the first diode is connected to the power supply voltage, and the positive terminal of the second diode is grounded. The first end of the target chip signal pin is connected to the second end of the target probe, and the second end of the target chip signal pin is connected to the positive terminal of the first diode.

6. The circuit according to claim 5, characterized in that, The test circuit board includes a chip power supply unit, a chip test unit circuit switching unit, and a control unit. The control unit is connected to the chip power supply unit and outputs an enable signal to the chip power supply unit to control the chip power supply unit to output power voltage or not output power voltage. The control unit is also connected to the circuit switching unit and outputs a control signal to the circuit switching unit to control the circuit switching unit to be turned on or off. The circuit switching unit is disposed between the chip power supply unit and the target chip power supply pin corresponding to the target chip signal pin, and the chip testing unit is connected between the chip power supply unit and the target chip signal pin; The circuit switching unit switches the connection between the chip power supply unit and the power supply pin of the target chip, the power supply pin of the target chip is connected to the power supply voltage, and the chip testing unit outputs a test signal to the signal pin of the target chip; The circuit switching unit switches the chip power supply unit to disconnect from the target chip power supply pin, and the target chip power supply pin is grounded.

7. The circuit according to claim 6, characterized in that, The circuit switching unit includes a switching relay and a MOSFET; The first terminal of the MOSFET is connected to the switching relay, and the second terminal of the MOSFET is connected to the control unit to receive the control signal from the control unit; The first terminal of the switching relay is connected to the first terminal of the MOS transistor, the second terminal of the switching relay is connected to the power supply pin of the target chip, the third terminal of the switching relay is connected to the power supply unit of the chip, and the fourth terminal of the switching relay is grounded.

8. The circuit according to claim 7, characterized in that, The switch relay includes a switch module and a relay coil; The switch module includes a common contact, a normally open contact, and a normally closed contact. The common contact is connected to the power supply pin of the target chip, the normally open contact is grounded, and the normally closed contact is connected to the chip power supply unit. The relay coil includes a first coil pin and a second coil pin. The first coil pin is connected to the relay power supply unit, and the second coil pin is connected to the first end of the MOS transistor.

9. The circuit according to claim 8, characterized in that, The circuit switching unit also includes a freewheeling diode, which is disposed between the first terminal of the MOS transistor and the relay power supply unit.

10. A chip test socket probe anomaly detection system, characterized in that, Includes a host computer; and a chip test socket probe anomaly detection circuit as described in any one of claims 1 to 9; The host computer is connected to the test circuit board through a preset communication interface and outputs a chip test socket detection command to the test circuit board to establish the connection between the second ends of the multiple probes of the chip test socket and the test circuit board.

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