Superheterodyne radio frequency receiver

Abstract

The utility model relates to radio frequency technical field especially, and it is a kind of superheterodyne radio frequency receiver, superheterodyne radio frequency receiver includes: antenna, for receiving radio frequency signal;Amplification filter module, for amplifying and filtering processing to radio frequency signal, output amplification and filtering processing after radio frequency signal;Mixing module, for converting frequency processing to amplification and filtering processing after radio frequency signal, output intermediate frequency signal;Impedance conversion module, for impedance conversion to intermediate frequency signal, output impedance conversion after intermediate frequency signal;Analog-digital conversion module, including continuous time sigma-delta modulator, for analog-digital conversion to impedance conversion after intermediate frequency signal, output target digital signal.The superheterodyne radio frequency receiver of the utility model embodiment, without the LC filter of big volume, poor reliability in traditional anti-interference radio frequency receiver structure, and then also can not set up intermediate frequency amplifier, saves cost, reduces the volume, and saves power consumption.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency technology, and in particular to a superheterodyne radio frequency receiver. Background Technology

[0002] In existing satellite navigation anti-jamming RF receiver architectures, to ensure high system sensitivity and strong anti-jamming capability, superheterodyne structures still offer performance advantages over zero-IF structures. The characteristic of anti-jamming receivers is that they must simultaneously receive weak useful signals and interference signals with significantly higher power than the useful signals. Therefore, the link gain needs to be set relatively low to ensure that the ADC is not saturated by the interference signal. Generally, the overall link gain will not exceed 30dB, placing high demands on the noise performance and linearity of the link components.

[0003] like Figure 1 As shown, in the superheterodyne structure of related technologies, the antenna-received signal passes through a low-noise amplifier (LNA) with a gain of approximately 20dB and an RF filter module (LNA+RF) to filter out far-end out-of-band interference and image frequency interference before entering the intermediate frequency (IF-BLOCK) module. The high-linearity mixer in the IF-BLOCK module provides a gain of 2-3dB, converting the RF signal to an IF signal around 33MHz±10MHz. The remaining gain of approximately 8dB is provided by the IF-BLOCK amplifier and the attenuator (ATT) before the mixer. The output of the IF-BLOCK amplifier needs to be converted to a single-ended signal by a transformer (1:1 transformer) and then fed into an LC filter as an anti-aliasing filter for the ADC. After passing through the anti-aliasing filter, the signal serves as the input to the high-speed ADC. High-speed ADCs are generally pipeline structures with a sampling rate typically of 108MHz.

[0004] It is evident that the receiver in the relevant technical architecture has the following drawbacks:

[0005] First, in the relevant technical architecture, high-speed ADCs generally adopt pipeline ADCs (pipeline analog-to-digital converters). Since the sampling rate of pipeline ADCs is not high, the requirements for the anti-aliasing filter in front of the pipeline ADC are high, and the order of the LC filter has to be relatively high. The problem is that the LC filter has a complex structure, large size, difficult debugging, and poor reliability.

[0006] Secondly, LC filters require both input and output characteristic impedances of 50 ohms to achieve their frequency response, and the intermediate frequency amplifier driving a 50-ohm load consumes a significant amount of power. ADC sampling circuits are generally of the switched-capacitor structure, and also require the ADC front-end transformer and related circuitry to be matched to a relatively low 50-ohm impedance to ensure sufficient setup accuracy for the switched-capacitor sampling circuit.

[0007] Third, the full-scale power of a typical pipeline ADC is around 10dBm (2Vpp). Due to the 2-3dB attenuation of the LC anti-aliasing filter, the intermediate frequency (IF) amplifier needs to maintain extremely high linearity at an output power around 12dBm-13dBm. This necessitates a significant increase in the IF amplifier's power consumption to achieve such high performance. This also leads to a higher OIP3 (Output 3) rating for the IF amplifier. rd Intercept Point (outputting the 3rd order intersection point) becomes the main factor restricting the linearity of the entire link, limiting the potential for further improvement in link performance.

[0008] Therefore, it is necessary to propose a new technical solution to address the problems of large size and poor reliability of LC filters in the anti-interference RF receiver structure of related technologies, as well as the resulting high performance requirements and high power consumption of intermediate frequency amplifiers. Utility Model Content

[0009] In view of this, the present invention proposes a superheterodyne radio frequency receiver, the superheterodyne radio frequency receiver comprising:

[0010] Antenna, used to receive radio frequency signals;

[0011] An amplification and filtering module, connected to the antenna, is used to amplify and filter the radio frequency signal and output the amplified and filtered radio frequency signal.

[0012] The mixing module, connected to the amplification and filtering module, is used to perform frequency conversion processing on the amplified and filtered radio frequency signal and output an intermediate frequency signal.

[0013] An impedance transformation module, connected to the mixer module, is used to perform impedance transformation on the intermediate frequency signal and output the impedance-transformed intermediate frequency signal.

[0014] An analog-to-digital conversion module is connected to the impedance transformation module. The analog-to-digital conversion module includes a continuous-time Sigma-delta modulator, which is used to perform analog-to-digital conversion on the impedance-transformed intermediate frequency signal and output the target digital signal.

[0015] In one possible implementation, the amplification and filtering module includes:

[0016] A low-noise amplifier is used to amplify the radio frequency signal;

[0017] An RF filter, connected to the low-noise amplifier, is used to filter the amplified RF signal and output the amplified and filtered RF signal.

[0018] In one possible implementation, the superheterodyne RF receiver further includes an intermediate frequency (IF) amplification module, which is disposed between the impedance transformation module and the analog-to-digital conversion module.

[0019] The intermediate frequency (IF) amplification module includes an IF amplifier, a first bypass switch, and a second bypass switch.

[0020] The second terminal of the first bypass switch is connected to the second terminal of the second bypass switch.

[0021] The third terminal of the first bypass switch is connected to the input terminal of the intermediate frequency amplifier.

[0022] The third terminal of the second bypass switch is connected to the output terminal of the intermediate frequency amplifier.

[0023] The first terminal of the first bypass switch is the input terminal of the intermediate frequency amplifier module, and the first terminal of the second bypass switch is the output terminal of the intermediate frequency amplifier module.

[0024] In one possible implementation, the superheterodyne RF receiver further includes a controllable attenuator for adjusting the attenuation of the input signal.

[0025] The controllable attenuator can be located between the mixing module and the amplification and filtering module, between the mixing module and the impedance transformation module, or between the impedance transformation module and the analog-to-digital conversion module.

[0026] In one possible implementation, the impedance transformation module includes at least one passive flux-coupled transformer.

[0027] The impedance transformation ratio of the impedance transformation module is greater than 1.

[0028] In one possible implementation, both input terminals of the continuous-time Sigma-delta modulator are provided with input resistors, the resistance of which is greater than or equal to 100Ω.

[0029] In one possible implementation, the input resistor has a resistance of 200Ω.

[0030] In one possible implementation, the sampling rate of the continuous-time Sigma-delta modulator is 20 or 24 times the system clock of the analog-to-digital conversion module.

[0031] In one possible implementation, if the system clock is 108MHz, the sampling rate of the continuous-time Sigma-delta modulator is 24 times the system clock of the analog-to-digital converter; or if the system clock is 124MHz, the sampling rate of the continuous-time Sigma-delta modulator is 20 times the system clock of the analog-to-digital converter.

[0032] In one possible implementation, the analog-to-digital conversion module further includes a first decimation filter and a second decimation filter, wherein the first decimation filter has a decimation rate of 1 / 6 or 1 / 5, and the second decimation filter has a decimation rate of 1 / 4.

[0033] The superheterodyne RF receiver also includes a serial LVDS interface component, which is connected to the analog-to-digital converter module and is used to output the target digital signal.

[0034] The bit clock of the serial LVDS interface component is four times the system clock of the analog-to-digital conversion module.

[0035] The superheterodyne radio frequency receiver of this utility model includes an antenna, an amplification and filtering module, a mixing module, an impedance transformation module, and an analog-to-digital conversion module containing a continuous-time Sigma-delta modulator. It eliminates the need for the bulky and unreliable LC filter found in traditional anti-interference radio frequency receiver structures, and also eliminates the need for an intermediate frequency amplifier, thus saving costs, reducing size, and saving power consumption.

[0036] Other features and aspects of the present invention will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0037] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of the present invention together with the specification and serve to explain the principles of the present invention.

[0038] Figure 1 A schematic diagram of a superheterodyne radio frequency receiver based on related technologies is shown.

[0039] Figure 2 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0040] Figure 3 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0041] Figure 4 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0042] Figure 5 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0043] Figure 6 A schematic diagram of a continuous-time Sigma-delta modulator according to an embodiment of the present invention is shown. Detailed Implementation

[0044] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0045] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0046] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0047] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of this inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0048] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0049] Furthermore, to better illustrate this utility model, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this utility model can be implemented even without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail, in order to highlight the main points of this utility model.

[0050] In view of the defects of the superheterodyne receivers mentioned in the background art, this utility model proposes a superheterodyne radio frequency receiver, including an antenna, an amplification and filtering module, a mixing module, an impedance transformation module, and an analog-to-digital conversion module containing a continuous-time Sigma-delta modulator. This superheterodyne radio frequency receiver eliminates the need for the bulky and unreliable LC filter found in the anti-interference radio frequency receiver structures of related technologies, and also eliminates the need for an intermediate frequency amplifier, thus saving costs, reducing size, and saving power consumption.

[0051] Please see Figure 2 , Figure 2 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0052] like Figure 2 As shown, the superheterodyne radio frequency receiver includes:

[0053] Antenna E1 is used to receive radio frequency signals;

[0054] Amplification and filtering module 10 is connected to the antenna E1 and is used to amplify and filter the radio frequency signal and output the amplified and filtered radio frequency signal.

[0055] The mixer module 20 is connected to the amplification and filtering module 10 and is used to perform frequency conversion processing on the amplified and filtered radio frequency signal to output an intermediate frequency signal.

[0056] Impedance transformation module 30 is connected to the mixer module 20 and is used to perform impedance transformation on the intermediate frequency signal and output the impedance-transformed intermediate frequency signal.

[0057] The analog-to-digital conversion module 40 is connected to the impedance transformation module 30. The analog-to-digital conversion module 40 includes a continuous-time Sigma-Delta modulator (CTDM) for performing analog-to-digital conversion on the impedance-transformed intermediate frequency signal and outputting a target digital signal.

[0058] This utility model embodiment does not limit the specific implementation of the amplification and filtering module 10, the mixing module 20, the impedance transformation module 30, and the analog-to-digital conversion module 40. Those skilled in the art can adopt appropriate hardware circuit structures according to actual conditions and needs.

[0059] Please see Figure 3 , Figure 3 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0060] In one possible implementation, such as Figure 3As shown, the amplification and filtering module 10 includes:

[0061] A low-noise amplifier 110 (LNA) is used to amplify the radio frequency signal;

[0062] The RF filter 120 is connected to the low-noise amplifier 110 and is used to filter the amplified RF signal and output the amplified and filtered RF signal.

[0063] For example, antenna E1 receives radio frequency (RF) signals (e.g., 1268MHz ± 10MHz) in the space. A low-noise amplifier 110 amplifies the received RF signal while minimizing its own noise introduction to ensure a good signal-to-noise ratio (SNR). The amplified RF signal then passes through an RF filter 120, which filters out out-of-band interference signals (such as other unwanted radio stations or spurious radiation) within the RF band, improving the receiver's selectivity (interference immunity).

[0064] For example, such as Figure 3 As shown in the embodiment of this utility model, the mixing module 20 may include a mixer 210, which can realize frequency down-conversion and output an intermediate frequency signal. The superheterodyne RF receiver may include a first phase-locked loop (PLL1) providing a local oscillator frequency Flo (1235MHz). The mixer 210 outputs the difference frequency signal (i.e., an intermediate frequency signal of 33MHz ± 10MHz) between the two frequencies through nonlinear frequency conversion. This utility model embodiment does not limit the specific implementation of the mixer 210 and the first PLL1; those skilled in the art can implement them according to actual conditions and needs, referring to relevant technologies.

[0065] In one possible implementation, such as Figure 3 As shown, the superheterodyne RF receiver also includes a controllable attenuator (ATT, also known as an attenuator or automatic gain controller), which is used to adjust the attenuation of the input signal. This embodiment of the invention does not limit the specific location of the controllable attenuator ATT; those skilled in the art can set it according to actual conditions and needs. For example, the controllable attenuator ATT can be located between the mixer module 20 and the amplification and filtering module 10, between the mixer module 20 and the impedance transformation module 30, or between the impedance transformation module 30 and the analog-to-digital conversion module 40.

[0066] This embodiment of the invention, by setting a controllable attenuator (ATT), can dynamically adjust the attenuation amount according to the signal strength, preventing subsequent mixing and amplification circuits from "saturating and distorting" due to excessively strong signals, and ensuring that the signal amplitude always matches the dynamic range of subsequent modules. Of course, this embodiment of the invention does not limit the specific implementation of the controllable attenuator (ATT), and those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs.

[0067] For example, in one possible implementation, the impedance transformation module 30 may include at least one passive transformer (such as a passive flux-coupled transformer), wherein the impedance transformation ratio of the impedance transformation module is greater than 1 (for example, the impedance transformation ratio between the output side and the input side may be 1:2, 1:4, 1:8, etc.). This embodiment of the invention does not limit the specific number of transformers in the impedance transformation module 30; those skilled in the art can determine this number based on actual conditions and needs. By including at least one passive transformer in the impedance transformation module 30, this embodiment of the invention enables impedance transformation and provides voltage gain.

[0068] For example, such as Figure 3 As shown, the impedance transformation module 30 can contain one transformer, including transformer 310.

[0069] Please see Figure 4 , Figure 4 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0070] For example, such as Figure 4 As shown, the impedance transformation module 30 can contain two transformers, including transformer 310 and transformer 320 (connected in series). For example, when a signal needs to be connected from the mixer 210 to the ADC via a connector, the transformer can be changed from one to two connected in series. In this way, the intermediate connector only needs to transmit a single-ended radio frequency signal, which can save connector costs.

[0071] For example, in this embodiment of the invention, the impedance transformation module 30 can be configured to have a preset impedance transformation ratio, and the turns ratio of each transformer in the impedance transformation module 30 can be adaptively adjusted. For instance, if the preset impedance transformation ratio is 1:4, then when the number of transformers in the impedance transformation module 30 is one, the turns ratio of that transformer is 1:4; when the number of transformers in the impedance transformation module 30 is two, such as... Figure 4 As shown, the turns ratios of transformer 310 and transformer 320 are 2:1 and 1:8 respectively (the overall ratio is 1:4).

[0072] In this embodiment of the invention, a continuous-time Sigma-delta modulator is used to replace the pipeline ADC in the related technical architecture. The anti-aliasing stopband requirement is relaxed from 108M-(33M+10M)=65M to above 2.4GHz. Since the available bandwidth of the flux-coupled transformer is only a few hundred MHz, it has a large attenuation above 2GHz. Therefore, the transformer can be used to replace the LC filter in the related technical architecture as an anti-aliasing filter, which meets the anti-aliasing requirements of CTSDM.

[0073] Please see Figure 5 , Figure 5 A schematic diagram of a superheterodyne radio frequency receiver according to an embodiment of the present invention is shown.

[0074] In one possible implementation, such as Figure 5 As shown, the superheterodyne RF receiver may further include an intermediate frequency (IF) amplification module 50, which may be disposed between the impedance transformation module 30 and the analog-to-digital conversion module 40.

[0075] The intermediate frequency amplification module 50 may include an intermediate frequency amplifier 510, a first bypass switch S1, and a second bypass switch S2.

[0076] The second terminal of the first bypass switch S1 is connected to the second terminal of the second bypass switch S2.

[0077] The third terminal of the first bypass switch S1 is connected to the input terminal of the intermediate frequency amplifier 510.

[0078] The third terminal of the second bypass switch S2 is connected to the output terminal of the intermediate frequency amplifier 510.

[0079] The first terminal of the first bypass switch S1 is the input terminal of the intermediate frequency amplifier module 50, and the first terminal of the second bypass switch S2 is the output terminal of the intermediate frequency amplifier module 50.

[0080] For example, the first bypass switch S1 and the second bypass switch S2 may include a multiplexer, a single-pole double-throw switch, etc.

[0081] For example, if it is necessary to bypass the intermediate frequency amplifier 510, the first bypass switch S1 and the second bypass switch S2 can both be turned on. At this time, the first end of the first bypass switch S1, the second end of the first bypass switch S1, the second end of the second bypass switch S2, and the first end of the second bypass switch S2 form a circuit.

[0082] For example, if the bypass intermediate frequency amplifier 510 is not required, the first bypass switch S1 and the second bypass switch S2 can both be lowered. At this time, the first end of the first bypass switch S1, the third end of the first bypass switch S1, the third end of the second bypass switch S2, and the first end of the second bypass switch S2 form a circuit.

[0083] This embodiment of the invention, by setting an intermediate frequency (IF) amplification module 50, selectively amplifies the useful IF signal, improves the SNR (Signal-to-Noise Ratio), increases the overall gain of the link before the analog-to-digital conversion module 40, provides a "cleaner" signal for subsequent ADC conversion and digital demodulation, and reduces demodulation errors. For example, as... Figure 5 As shown, in the absence of interference, the intermediate frequency amplifier 510 provides an additional gain of approximately 10dB to further suppress the noise of the ADC, thus improving the sensitivity under interference-free conditions. In the presence of interference, the link gain needs to be reduced, and the intermediate frequency amplifier 510 is bypassed, restoring the state of this invention.

[0084] This embodiment of the invention enables the bypassing of the intermediate frequency amplifier 510 via the first bypass switch S1 and the second bypass switch S2. The receiver has independent performance requirements under interference and non-interference conditions. By using the first bypass switch S1 and the second bypass switch S2 to bypass the intermediate frequency amplifier 510, the purpose is to improve link gain and reduce the equivalent noise figure at the front end under interference-free conditions, thus ensuring the receiver's reception performance in interference-free situations. For example, under interference conditions, if the intermediate frequency amplifier 510 is still connected, the amplified interference signal will cause ADC saturation. In this case, the intermediate frequency amplifier 510 can be short-circuited via the first bypass switch S1 and the second bypass switch S2 to avoid ADC saturation.

[0085] This invention does not limit the specific implementation of the continuous-time Sigma-delta modulator in the analog-to-digital converter. Those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs.

[0086] Please see Figure 6 , Figure 6 A schematic diagram of a continuous-time Sigma-delta modulator according to an embodiment of the present invention is shown.

[0087] like Figure 6 As shown, a continuous-time Sigma-delta modulator may consist of a differential input structure, a continuous-time loop filter, a feedback DAC, a quantizer, a digital decimation filter, a serializer, and a clock module.

[0088] In one possible implementation, such as Figure 6 As shown, the continuous-time Sigma-delta modulator can adopt a differential input structure. Both input terminals of the continuous-time Sigma-delta modulator are provided with input resistors, and the resistance value of the input resistors is greater than or equal to 100Ω.

[0089] In one possible implementation, the input resistor has a resistance of 200Ω.

[0090] and Figure 1 Unlike the superheterodyne RF receiver shown, the superheterodyne RF receiver of this embodiment achieves a 9dB voltage gain through the aforementioned 1:4 transformer by setting the input resistor value to be greater than or equal to 100Ω, and particularly setting the input resistor value to 200Ω. Figure 1 The architecture shown uses an LC filter scheme, which significantly reduces the requirements for front-end link gain, and... Figure 1 The architecture shown requires an intermediate frequency amplifier 510 to achieve a 9dB intermediate frequency gain. This embodiment of the invention eliminates the intermediate frequency amplifier, replacing it with a transformer, further saving power, cost, and size. Furthermore, the transformer is a passive device, and its impact on link noise and linearity is negligible compared to... Figure 1 In the illustrated scheme, the noise and linearity of the intermediate frequency amplifier are the bottlenecks of the entire link. This utility model embodiment significantly improves the overall noise and linearity performance of the link.

[0091] For example, such as Figure 6 As shown, a feedback DAC can convert the output of a digital quantizer into an analog feedback signal, forming a negative feedback closed loop with the input signal. Through closed-loop control, the system's linear response to the input signal is ensured, while simultaneously participating in the "noise shaping" process, pushing quantization noise to higher frequencies.

[0092] For example, such as Figure 6 As shown, the continuous-time loop filter (CTSDM) consists of operational amplifiers (op-amps), capacitors, and other components forming a continuous-time integrator (often a first-order or higher-order integrator structure). Its function is to continuously integrate the difference between the input signal and the feedback signal (error signal) (distinct from the discrete-time Sigma-delta integration), providing the basis for noise shaping.

[0093] For example, such as Figure 6As shown, the differential input signal VINP / VINN is subtracted from the analog signal fed back by the DAC to obtain the error signal. This error signal is continuously integrated by a continuous-time loop filter (integrator) (without discrete sampling). At this point, the closed-loop transfer function of the system exhibits a "near-full-pass" characteristic for the input signal, while exhibiting a "high-pass" characteristic for quantization noise—that is, noise shaping: transferring the energy of quantization noise from the "low-frequency bandwidth of the useful signal" to the "high-frequency region much higher than the signal bandwidth".

[0094] For example, such as Figure 6 As shown, the quantizer can operate at extremely high sampling rates ( Figure 6 (In the example, Fs=2596MHz, obtained from 108M×24) the output of the continuous-time integrator is sampled and quantized to output a low-resolution digital code (such as a 1-bit or a few-bit digital signal), completing the initial conversion from analog signal to low-precision digital code stream.

[0095] For example, in one possible implementation, the sampling rate of the continuous-time Sigma-delta modulator is 20 or 24 times the system clock of the analog-to-digital conversion module 40, and the clock of the continuous-time Sigma-delta modulator can be provided by a second phase-locked loop (PLL2).

[0096] In one possible implementation, if the system clock is 108MHz, the sampling rate of the continuous-time Sigma-delta modulator is 24 times the system clock of the analog-to-digital converter 40; or if the system clock is 124MHz, the sampling rate of the continuous-time Sigma-delta modulator is 20 times the system clock of the analog-to-digital converter 40, in which case the CTSDM sampling rate is 2.48GHz. Of course, when the system clock is different, those skilled in the art can set the corresponding intermediate frequency according to the actual situation and needs, such as: when the system clock is 108MHz, the CTSDM sampling rate is 2.596MHz and the intermediate frequency is 33MHz; when the system clock is 124MHz, the CTSDM sampling rate is 2.48MHz and the intermediate frequency is 46MHz.

[0097] For example, a digital decimation filter performs "downsampling + low-pass filtering" on the high-speed, low-precision digital bitstream output by the quantizer, such as... Figure 6 As shown, in one possible implementation, the analog-to-digital conversion module 40 further includes a first decimation filter ( / 6 or / 5 optional, / 6 corresponds to the 108M case, / 5 corresponds to the 124M case) and a second decimation filter ( / 4), wherein the decimation rate of the first decimation filter is 1 / 6 or 1 / 5, and the decimation rate of the second decimation filter is 1 / 4.

[0098] The superheterodyne RF receiver also includes a serial LVDS interface component (serial port), which is connected to the analog-to-digital converter module 40 and is used to output the target digital signal.

[0099] The bit clock of the serial LVDS interface component is four times the system clock of the analog-to-digital conversion module 40.

[0100] For example, the first decimation filter reduces the sampling rate to 1 / 6 or 1 / 5 of the original, while filtering out some high-frequency quantization noise; the second decimation filter further reduces the sampling rate to 1 / 4 and deeply filters out the high-frequency quantization noise after "noise shaping", ultimately increasing the effective number of bits (ENOB) of the digital signal.

[0101] The serial LVDS interface component converts the decimated and filtered parallel digital signal into a serial format, generates FR (frame synchronization signal, used for data alignment), and outputs the target digital signal through DOA and DOB (serial data channels) to facilitate subsequent digital circuits (such as processors and FPGAs) to receive and process it.

[0102] The digital signal DCO can be used in the Serial LVDS interface to achieve synchronous transmission of serial data. For example, an external receiver (such as an FPGA) can use the clock edge of the DCO to sample the data on the Serial LVDS bus to ensure that the data is accurately captured and avoid errors caused by timing mismatch.

[0103] The superheterodyne radio frequency receiver of this utility model embodiment has the following advantages:

[0104] By using a high-sampling-rate CTSDM and a passive transformer with limited bandwidth, the LC anti-aliasing filter in the related technical architecture is eliminated. Those skilled in the art should understand that LC filters are large, require manual adjustment during production, thus limiting production capacity, and are prone to reliability issues and high failure rates. This embodiment of the invention eliminates the need for an LC filter, also saving 2-3 dB of attenuation, which can improve the linearity and noise performance of the link.

[0105] By utilizing the high input impedance design of the CTSDM, and in conjunction with a passive transformer, lossless voltage gain is achieved during impedance transformation, reducing link gain and linearity requirements. This also eliminates the need for a single intermediate frequency amplifier stage (510), saving power and cost.

[0106] By using reasonable frequency planning, the interference problem caused by the high-frequency clock of CTSDM is avoided, while being compatible with the original ADC interface, without the need to modify the baseband design.

[0107] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A superheterodyne radio frequency receiver, characterized in that, The superheterodyne radio frequency receiver includes: Antenna, used to receive radio frequency signals; An amplification and filtering module, connected to the antenna, is used to amplify and filter the radio frequency signal and output the amplified and filtered radio frequency signal. The mixing module, connected to the amplification and filtering module, is used to perform frequency conversion processing on the amplified and filtered radio frequency signal and output an intermediate frequency signal. An impedance transformation module, connected to the mixer module, is used to perform impedance transformation on the intermediate frequency signal and output the impedance-transformed intermediate frequency signal. An analog-to-digital conversion module is connected to the impedance transformation module. The analog-to-digital conversion module includes a continuous-time Sigma-delta modulator, which is used to perform analog-to-digital conversion on the impedance-transformed intermediate frequency signal and output the target digital signal.

2. The superheterodyne radio frequency receiver according to claim 1, characterized in that, The amplification and filtering module includes: A low-noise amplifier is used to amplify the radio frequency signal; An RF filter, connected to the low-noise amplifier, is used to filter the amplified RF signal and output the amplified and filtered RF signal.

3. The superheterodyne radio frequency receiver according to claim 1, characterized in that, The superheterodyne RF receiver further includes an intermediate frequency (IF) amplification module, which is disposed between the impedance transformation module and the analog-to-digital conversion module. The intermediate frequency (IF) amplification module includes an IF amplifier, a first bypass switch, and a second bypass switch. The second terminal of the first bypass switch is connected to the second terminal of the second bypass switch. The third terminal of the first bypass switch is connected to the input terminal of the intermediate frequency amplifier. The third terminal of the second bypass switch is connected to the output terminal of the intermediate frequency amplifier. The first terminal of the first bypass switch is the input terminal of the intermediate frequency amplifier module, and the first terminal of the second bypass switch is the output terminal of the intermediate frequency amplifier module.

4. The superheterodyne radio frequency receiver according to claim 1, characterized in that, The superheterodyne RF receiver also includes a controllable attenuator, which is used to adjust the attenuation of the input signal. The controllable attenuator can be located between the mixing module and the amplification and filtering module, between the mixing module and the impedance transformation module, or between the impedance transformation module and the analog-to-digital conversion module.

5. The superheterodyne radio frequency receiver according to claim 1, characterized in that, The impedance transformation module includes at least one passive flux coupling transformer. The impedance transformation ratio of the impedance transformation module is greater than 1.

6. The superheterodyne radio frequency receiver according to claim 1, characterized in that, Both input terminals of the continuous-time Sigma-delta modulator are provided with input resistors, and the resistance value of the input resistors is greater than or equal to 100Ω.

7. The superheterodyne radio frequency receiver according to claim 6, characterized in that, The input resistor has a resistance of 200Ω.

8. The superheterodyne radio frequency receiver according to claim 1, characterized in that, The sampling rate of the continuous-time Sigma-delta modulator is 20 or 24 times the system clock of the analog-to-digital converter module.

9. The superheterodyne radio frequency receiver according to claim 8, characterized in that, If the system clock is 108MHz, the sampling rate of the continuous-time Sigma-delta modulator is 24 times the system clock of the analog-to-digital converter module; or if the system clock is 124MHz, the sampling rate of the continuous-time Sigma-delta modulator is 20 times the system clock of the analog-to-digital converter module.

10. The superheterodyne radio frequency receiver according to claim 1, characterized in that, The analog-to-digital conversion module further includes a first decimation filter and a second decimation filter, wherein the decimation rate of the first decimation filter is 1 / 6 or 1 / 5, and the decimation rate of the second decimation filter is 1 / 4. The superheterodyne RF receiver also includes a serial LVDS interface component, which is connected to the analog-to-digital conversion module and is used to output the target digital signal. The bit clock of the serial LVDS interface component is four times the system clock of the analog-to-digital conversion module.

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