U.2 storage device

Abstract

The utility model provides a kind of U.2 storage device, including adapter plate and at least one M.2 storage device being laid on adapter plate;M.2 storage device includes M.2 connector, M.2 connector includes M.2 PCIe interface, M.2 PCIe interface includes first power pin and first data pin;Adapter plate includes U.2 connector, power management circuit and at least one capacitor as backup power supply, U.2 connector includes U.2 PCIe interface, U.2 PCIe interface includes second power pin and second data pin, the first power end of power management circuit is connected second power pin, second power end connects at least one capacitor, power output end connects the first power pin of M.2 storage device, second data pin is connected with first data pin;Power management circuit provides the power from first or second power end to the first power pin of M.2 storage device.

Description

Technical Field

[0001] This utility model relates to the field of storage technology, and in particular to U.2 storage devices. Background Technology

[0002] Figure 1A A block diagram of the storage device is shown. Storage device 102 is coupled to a host computer to provide storage capabilities. The host computer and storage device 102 can be coupled in various ways, including but not limited to using storage protocols such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device in the above ways, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] Interface 103 can be adapted to exchange data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. L2P tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] Figure 1B A detailed block diagram of the control components of the storage device is shown.

[0008] The host accesses the storage device using I / O commands that conform to the storage protocol. The control unit generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the NVM chip's interface protocol based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from a single I / O command and indicates the processing results of the I / O commands to the host.

[0009] See Figure 1BThe control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface receives I / O commands from the host and generates storage commands, which are then provided to the storage command processing unit. A storage command may access a storage space of the same size, such as 4KB. The data unit recorded in the NVM chip corresponding to the data accessed by a storage command is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store four data frames. The storage media management unit maintains the translation from Logical Block Address (LBA) to Physical Page Address (PPA) for each storage command. For example, the storage media management unit includes an L2P table, which is used to record the mapping relationship between logical addresses and physical addresses.

[0010] The storage command processing unit, based on the physical address provided by the storage media management unit, operates the media interface controller to issue storage media access commands to the NVM chip. For clarity, commands sent from the host to the storage device are called I / O commands, commands sent from the host command processing unit to the storage command processing unit are called storage commands, commands sent from the storage command processing unit to the media interface controller are called media interface commands, and commands sent from the media interface controller to the NVM chip are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol.

[0011] During operation, storage devices not only read and write data according to host I / O commands, but also generate L2P tables, logs, bad block information, and valid data information (collectively known as management data). Before powering down, this data needs to be saved to the NVM chip for retrieval and use upon the next power-on. Normally, when the host notifies the storage device of an impending power-off, the storage device, in response, saves the L2P table, logs, bad block information, and / or valid data information to the NVM chip during its power-off processing. This allows the storage device to quickly retrieve and restore this data upon the next power-on, enabling it to continue responding to host I / O commands.

[0012] In some situations, unexpected power outages may occur, such as a host power failure or the storage device being accidentally removed. Providing backup power within the storage device can handle such scenarios, allowing the storage device to complete the power-down process even in the event of an unexpected power outage.

[0013] The host provides power to the storage device through an interface to enable the storage device to operate. Backup power supplies are energy storage components such as supercapacitors and batteries. When the host's power supply to the storage device is interrupted or fails, the backup power supply provides emergency power to the storage device, allowing it to continue processing ongoing but unfinished I / O commands. It also uses the power provided by the backup power supply to record the operating status of the storage device. Due to factors such as cost and reliability, the power provided by the backup power supply is limited, and the time it can support the operation of the various components of the storage device is finite.

[0014] Figure 2A A diagram illustrating how management data is organized on storage devices is shown.

[0015] exist Figure 2A In this system, the storage device includes a control unit, NAND flash memory, a backup power supply, and DRAM. The control unit is connected to the host via a PCIe interface. The backup power supply provides power to the storage device when it experiences an abnormal power failure. The DRAM is used to cache data provided by the host.

[0016] NAND flash memory comprises one or more LUNs (Logical Units). Each LUN consists of multiple physical blocks. LUNs include SLC (Single-Level Cell) regions and TLC (Triple-Level Cell) regions, each containing multiple physical blocks. The multiple physical blocks within the SLC region are further divided into a Bad Block Management (BBM) region, a System Metadata (Log Block) region, an L2P mapping table (Sys Block) region, and a Data Buffer region. The BBM, Log Block, Sys Block, and Buffer Data regions occupy different physical blocks within the SLC region.

[0017] The BBM area is used to store bad block information. The BBM area is located at a designated location within the LUN; for example, Block 0 (physical block 0) of each LUN can be used as the BBM area for that LUN. The BBM area of ​​each LUN stores the bad block information for that LUN. During storage device use, the bad blocks in each LUN may change; for example, one or more normal physical blocks in the LUN may become bad physical blocks. The control unit then updates the bad block information stored in the BBM area of ​​each LUN.

[0018] The Log Block area is used to store system metadata, such as the Read Count Table, SMART (Self-Monitoring, Analysis and Reporting Technology) information, etc. The Log Block area is arranged as follows: Figure 2B The circular buffer organization shown depicts system metadata being written to the Log Block area in the order it is generated. Multiple versions of system metadata are recorded throughout the Log Block area. System metadata is written sequentially to the Log Block area, accompanied by a sequence number (SN) to indicate that data with a larger sequence number was written later than data with a smaller sequence number. Therefore, for data with the same meaning, the version with the larger sequence number is the newer version. Upon power-up, the latest version of the system metadata is read and used.

[0019] The Sys Block area is used to store data for recovering the L2P table. The Sys Block area follows the Log Block area. Data recording updates to the L2P table is written sequentially to the Sys Block area. Upon power-up, recovering the L2P table requires accessing the Sys Block area in reverse chronological order to read the data and recover the complete L2P table.

[0020] The Buffer Data area is used to store user-written data (also known as user data) cached in the storage device cache (such as DRAM) during a power outage. When a power outage occurs, user data that has not yet been written to the NAND flash TLC area in the cache is written to the Buffer Data area.

[0021] When a storage device experiences an abnormal power outage and is subsequently powered on again, it needs to initialize before it can begin receiving host I / O commands. Storage device initialization mainly includes the following stages:

[0022] 1. Hardware Initialization

[0023] Initialize all hardware in the storage device, such as control components, DRAM, NAND flash memory, etc.

[0024] 2. Establish a PCIe link with the host.

[0025] 3. Construct the Block (physical block) information table

[0026] The control unit reads data from a specified location in each block of the NAND flash memory, such as the physical page data at the beginning and end of each block, to obtain basic information about each physical block, such as whether it is full of data, whether it has been partially written with data, whether it is empty, and the serial number (SN) of the block that has been written with data. Based on the analyzed and organized information, a block information table is constructed.

[0027] 4. Construct a Bad Block Management Table (BBM Table)

[0028] Bad block information is stored in, for example Figure 2A The BBM region is shown.

[0029] By reading bad block information from the BBM region, a bad block management table is constructed and stored in the storage device cache, such as DRAM. This bad block management table effectively distinguishes between normal physical blocks and bad blocks, preparing for subsequent read and write operations of user data.

[0030] 5. Restore system metadata

[0031] System metadata is stored in, for example Figure 2A The system metadata area is shown. When the storage device experiences an abnormal power loss, the current write position of the Log Block area is unknown, as are the locations within the Log Block area that store the latest version of the system metadata. To obtain the latest system metadata before the power loss upon power-up, the Log Block area is scanned after the storage device is powered on to find the largest sequence number. The SLC Block containing this sequence number is the last written block. One copy of the system metadata is read backward from this block as the latest system metadata at the time of the power loss.

[0032] 6. Restore L2P table

[0033] Figure 2A The Sys Block region records the data used to recover the L2P table. After the storage device is powered back on, the Sys Block region is scanned, and the data is read by accessing the Sys Block region in order from newest to oldest in order to recover the complete L2P table.

[0034] 7. Calculate and construct the necessary data for various systems based on the L2P table.

[0035] After the L2P table is restored, the data required by the control components is further constructed. This data is usually obtained from the L2P table, such as the VTC (Valid Transmission Unit Count) table. The VTC table includes multiple entries, each corresponding to a physical block. Each entry records the number of valid transmission units in the physical block associated with that entry. The position of an entry in the VTC table indicates the physical block number associated with that entry. The VTC table is described in detail in Chinese patent application number 202110251863.6.

[0036] After completing the above operations, the storage device initialization is complete, and the storage device can respond to I / O commands provided by the host.

[0037] Storage devices come in various standard types, such as M.2 SSDs (Solid State Disks), U.2 SSDs, and U.3 SSDs. Different SSD standards differ in aspects such as physical size, interface protocols, electrical specifications, compatibility, and heat dissipation. For example, M.2 SSDs use a standardized physical size, typically 22mm wide, with common sizes including 2230 (22mm*30mm), 2242 (22mm*42mm), 2260 (22mm*60mm), and 2280 (22mm*80mm). M.2 SSD connectors are used to connect to M.2 slots. U.2 SSDs, on the other hand, have standard 2.5-inch drive dimensions (100.45mm*69.85mm), with common thicknesses of 7mm / 9.5mm / 15mm, and use a 68-pin shielded connector.

[0038] Due to size limitations, M.2 SSDs typically do not have a backup power supply. To improve the reliability of M.2 SSDs, the PCI Express M.2 Specification defines a "PLN (Power Loss Notification) signal." If the host computer housing the M.2 SSD provides a short-term power supply to the M.2 SSD after a power outage, a PLN-enabled host will set the PLN signal before cutting off power to the M.2 SSD and will ensure a power supply for a period of time after setting the PLN signal.

[0039] In existing technology, there are also solid-state drive enclosures based on M.2 SSDs (https: / / www.zhihu.com / question / 512618251 / answer / 11687118186), which use an additional hard drive enclosure to house the M.2 SSD for use as a portable hard drive. By using the enclosure, the form factor of the M.2 SSD is eliminated, allowing capacitors to be incorporated within the enclosure to provide short-term protection during power outages. However, such devices no longer have an industry-standard form factor, making them unsuitable for installation in standard computer case slots and requiring connection to the host computer via a cable such as a USB (Universal Serial Bus) cable. Utility Model Content

[0040] We desire a convenient and efficient way to obtain U.2 SSDs with power-loss retention capabilities. Additionally, we want U.2 SSDs with power-loss protection to be available regardless of whether the host machine installing the U.2 SSD supports PLN.

[0041] Offering multiple SSD specifications (such as M.2 SSDs and U.2 SSDs) introduces complexity to R&D and production, requiring the development of firmware and hardware versions for various SSD product specifications. The aim is to provide an M.2 SSD that can be delivered to users as a standalone storage device, or a U.2 SSD can be derived from the same M.2 SSD. This would eliminate the need for firmware development for U.2 SSDs, simplify the hardware development process, and enrich the product range available to suppliers. When used alone, the M.2 SSD does not support power-loss protection; however, when a U.2 SSD is derived from the M.2 SSD, power-loss protection can be achieved by utilizing the power-loss capacitors integrated within the U.2 SSD.

[0042] To adapt to the different application scenarios mentioned above, this application aims to provide a solution that enables the M.2 SSD to (1) be delivered to users as an independent M.2 SSD product, operating in an environment without power-loss protection capacitors and where the host does not provide PLN signals; (2) be delivered to users as a U.2 SSD product, operating in an environment with power-loss protection capacitors and where the host does not provide PLN signals; (3) be delivered to users as a U.2 SSD product, operating in an environment with power-loss protection capacitors and where the host provides PLN signals; (4) be delivered to users as a U.2 SSD product, operating in an environment without power-loss protection capacitors and where the host provides PLN signals; (5) be delivered to users as a U.2 SSD product, operating in an environment without power-loss protection capacitors and where the host does not provide PLN signals, etc.

[0043] This utility model embodiment provides a U.2 storage device, including:

[0044] An adapter board, and at least one M.2 storage device disposed on the adapter board;

[0045] The M.2 storage device includes an M.2 connector, the M.2 connector includes an M.2 PCIe interface, and the M.2 PCIe interface includes a first power pin and a first data pin;

[0046] The adapter board includes a U.2 connector, a power management circuit, and at least one capacitor as a backup power source. The U.2 connector includes a U.2 PCIe interface, which includes a second power pin and a second data pin. The first power terminal of the power management circuit is connected to the second power pin, and the second power terminal is connected to at least one capacitor. The power output terminal of the power management circuit is connected to the first power pin of the M.2 storage device, and the second data pin is connected to the first data pin.

[0047] The power management circuit provides power from the first power terminal or the second power terminal to the first power pin of the M.2 storage device through the power output terminal.

[0048] Optionally, the power management circuit provides power from the second power supply terminal to the first power pin of the M.2 storage device when there is no power supply from the first power supply terminal.

[0049] Optionally, the adapter board is provided with an M.2 slot, and the M.2 storage device is connected to the adapter board through the M.2 slot.

[0050] Optionally, the second data pin and the first data pin are connected correspondingly via a connection line laid on the adapter board between the second data pin and the first data pin.

[0051] Optionally, the power management circuit provides power from the first power supply terminal to the first power pin of the M.2 storage device and / or the second power supply terminal, depending on whether power is available at the first power supply terminal.

[0052] Optionally, the power management circuit may cut off the power supply to the at least one capacitor based on the availability of power at the first power supply terminal.

[0053] Optionally, the M.2PCIe interface further includes a first PLN signal pin, and the U.2PCIe interface further includes a second PLN signal pin;

[0054] The power management circuit connects the first PLN signal pin and the second PLN signal pin; the power management circuit provides the PLN signal from the second PLN signal pin or the PLN signal generated when there is no power supply from the first power supply pin to the first PLN signal pin.

[0055] Optionally, the power management circuit generates the PLN signal and provides it to the first PLN signal pin based on the fact that no power is supplied to the first power supply terminal and the second PLN signal pin provides the PLN signal.

[0056] Optionally, the power management circuit generates the PLN signal and provides it to the first PLN signal pin when there is no power supply at the first power supply terminal and the second PLN signal pin does not provide a PLN signal.

[0057] Optionally, the power management circuit provides the PLN signal from the second PLN signal pin, or the PLN signal it generates itself, to at least a portion of the storage devices in the at least one M.2 storage device.

[0058] Optionally, at least two M.2 storage devices are arranged on the adapter board, and the M.2 storage devices include control components;

[0059] The two control units corresponding to the two M.2 storage devices are connected via an inter-die interconnect link.

[0060] Optionally, the M.2 storage device includes a Die Link connector, which is connected to the control component inside the M.2 storage device;

[0061] The Die Link connector is located on the edge of the circuit board where the M.2 storage device is located, and is connected to the contacts on the adapter board.

[0062] Optionally, the inter-die interconnect link between the two M.2 storage devices includes a connection routed on the adapter board between the DieLink connectors of the two M.2 storage devices, and a connection route between the control unit of each M.2 storage device and the DieLink connector.

[0063] Optionally, the at least two M.2 storage devices include a first storage device and at least one second storage device;

[0064] The first PLN signal pins corresponding to the first storage device and the at least one second storage device are respectively connected to the PLN signal output terminal of the power management circuit, and the first storage device and the at least one second storage device each receive the PLN signal provided by the power management circuit through the PLN signal output terminal; or

[0065] The first PLN signal pin of the first storage device is connected to the PLN signal output terminal of the power management circuit, while the first PLN signal pin of the second storage device is not connected to the PLN signal output terminal of the power management circuit.

[0066] Optionally, the first data pins of the M.2 PCIe interfaces corresponding to the first storage device and the at least one second storage device are all connected to the second data pins of the U.2 PCIe interface; or

[0067] The first data pin in the M.2 PCIe interface of the first storage device is connected to the second data pin in the U.2 PCIe interface, while the first data pin in the M.2 PCIe interface of the second storage device is not connected to the second data pin in the U.2 PCIe interface.

[0068] In this embodiment of the invention, by constructing a U.2SSD based on one or more M.2SSDs, storage devices with different capacity specifications can be obtained, thereby increasing the storage capacity of the storage devices. Furthermore, the constructed U.2SSD supports operation in scenarios with and without power-loss protection capacitors, and can be used with hosts that support or do not support PLN, making it applicable to different hosts. Attached Figure Description

[0069] Figure 1A A block diagram representing a storage device;

[0070] Figure 1B A detailed block diagram of the control components of the storage device is shown;

[0071] Figure 2A This diagram illustrates how management data is organized in storage devices.

[0072] Figure 2B This diagram illustrates the write order for writing data to the Log Block area.

[0073] Figure 3A A schematic diagram of the structure of a U.2SSD provided in an embodiment of this utility model is shown.

[0074] Figure 3B This invention provides a second schematic diagram of the structure of a U.2SSD according to an embodiment of the present invention.

[0075] Figure 4A This illustration shows a structural schematic diagram of a U.2SSD provided in yet another embodiment of the present invention;

[0076] Figure 4B A schematic diagram of the inter-die interconnection link provided in an embodiment of this utility model is shown;

[0077] Figure 5 A schematic diagram of the structure of a U.2SSD provided in another embodiment of the present invention is shown. Detailed Implementation

[0078] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0079] Example 1

[0080] Figure 3A A schematic diagram of the structure of a U.2SSD provided in an embodiment of this utility model is shown.

[0081] The U.2 SSD includes an adapter board (for M.2 to U.2 conversion) and an M.2 SSD mounted on the adapter board. The M.2 SSD itself conforms to the M.2 standard and does not include a power-loss protection capacitor. The M.2 SSD includes an M.2 connector, which includes an M.2 PCIe interface. The M.2 PCIe interface includes a set of PCIe-compliant pins, including power pin 1 and PLN signal pin 1. The M.2 SSD is a standalone product and can be connected to a host computer independently via the M.2 connector for use by the host computer.

[0082] The adapter board includes a U.2 connector, power management circuitry, and at least one capacitor (four are shown in the diagram). The capacitors on the adapter board serve as backup power, dedicated to energy storage, and provide the M.2 SSD with the power required for its operation. The U.2 connector is used to connect to the host computer, allowing the U.2 SSD to be accessed and used by the host. The U.2 connector includes a U.2 PCIe interface, which includes a set of PCIe-compliant pins, including power pin 2 and PLN signal pin 2. The power management circuit includes a first power supply terminal, a second power supply terminal, a power output terminal, and a PLN signal output terminal. The first power supply terminal is connected to power pin 2 in the U.2 connector to receive power from the host. The second power supply terminal is coupled to at least one capacitor to receive power from the capacitor used as a backup power source. The power output terminal is connected to power pin 1 of the M.2 connector to power the M.2 SSD. The PLN signal output terminal is connected to PLN signal pin 1 of the M.2 connector to provide a PLN signal to the M.2 SSD, enabling the M.2 SSD to enter the abnormal power-down processing procedure based on the PLN signal.

[0083] At least some pins (e.g., the second data pin) of the U.2 PCIe interface, excluding power pin 2 and PLN signal pin 2, are connected to at least some pins (e.g., the first data pin) of the M.2 PCIe interface, excluding power pin 1 and PLN signal pin 1. The wiring on the adapter board provides the corresponding connections between the pins of the U.2 PCIe interface and the M.2 PCIe interface. In the power management circuit, the first power terminal connected to power pin 2 of the U.2 connector, after receiving power from the host, supplies the power provided by the host to power pin 1 of the M.2 connector through the power output terminal, using the power provided by the host to power the M.2 SSD. At this time, the power management circuit cuts off the power supply to the M.2 SSD from the capacitor used as a backup power source. Optionally, the power management circuit also uses the power provided by the host to charge the capacitor. If the first power supply terminal connected to power pin 2 of the U.2 connector in the power management circuit does not receive power from the host, the second power supply terminal of the power management circuit receives power from the capacitor serving as a backup power source, and powers the M.2 SSD based on the power provided by the capacitor. Since the power management circuit does not receive power from the host, it generates a PLN signal and transmits the PLN signal to PLN signal pin 1 of the M.2 connector through the PLN signal output terminal to inform the M.2 SSD that a power outage is imminent. Upon receiving the PLN signal, the M.2 SSD executes the abnormal power outage handling procedure.

[0084] The adapter board features an M.2 slot, through which the M.2 SSD connects to the adapter board. This eliminates the need for additional specialized equipment or procedures to install the M.2 SSD into the U.2 SSD. The M.2 slot is a standardized component; its thickness, even when combined with the adapter board's thickness, still meets the U.2 SSD's thickness requirement (not exceeding 7mm). The power-loss protection capacitors also need to meet this thickness requirement. Supercapacitors, multilayer ceramic capacitors, and tantalum capacitors can all meet this requirement. Multiple capacitors can be used to balance power capacity, U.2 SSD size specifications, and capacitor cost. Optionally, a thin battery (such as a lithium battery) can be used instead of the capacitor as a backup power source.

[0085] exist Figure 3A In the structure shown, a U.2 SSD is constructed by combining an M.2 SSD with an adapter board with capacitors (for M.2 to U.2 conversion). A U.2 SSD with power-loss protection capacitors can be obtained based on the M.2 SSD. When the host loses power abnormally, the capacitors supply power to the U.2 SSD, so as to obtain a U.2 SSD with power loss retention capability conveniently and efficiently.

[0086] U.2 SSDs, built using M.2 SSDs and adapter boards, can be connected to both PLN-enabled and non-PLN-enabled hosts. Figure 3A In this configuration, the host connected to the U.2 SSD does not support PLN; the host only provides power and does not provide a PLN signal until the host loses power. After the host stops supplying power, the power management circuit receives power from the capacitor at its second power supply terminal and powers the M.2 SSD based on the capacitor's power supply. Additionally, the power management circuit automatically generates a PLN signal and transmits it to the M.2 SSD's PLN signal pin 1 via the PLN signal output terminal to trigger the M.2 SSD to execute the abnormal power failure handling procedure.

[0087] Figure 3B The second schematic diagram shows the structure of a U.2SSD provided in one embodiment of the present invention.

[0088] exist Figure 3BIn this system, the host connected to the U.2 SSD supports PLN (Power Line Network). The host provides not only power but also the PLN signal. Before the host stops supplying power, the PLN signal is set, and after setting the PLN signal, a power supply is ensured for a period of time. The host transmits the PLN signal to the power management circuitry via pin 2 of the U.2 connector. The power management circuitry then provides this PLN signal to the M.2 SSD, or generates a PLN signal based on this PLN signal and provides it to the M.2 SSD. Because the host provides power for a period of time after setting the PLN signal, the M.2 SSD can prepare for power failure during this period (execute an abnormal power failure handling process), such as writing cached user data, L2P tables, and power-on initialization related content to the NAND flash memory.

[0089] Optionally, after the host power supply stops, the second power supply terminal connected to the capacitor in the power management circuit receives power from the capacitor and supplies power to the M.2 SSD based on the power provided by the capacitor, thus utilizing the backup power supply. Since the host only provides power for a period of time after setting the PLN signal, the M.2 SSD may not be able to complete the power-down preparation work based on the PLN signal provided by the host during this period. For example, the content related to power-on initialization may not be fully written to the NAND flash memory. When the power management circuit detects that the host power supply has stopped, it uses the backup power supply to take over from the host to supply power to the M.2 SSD. For example, the power management circuit provides power from the backup power supply to the M.2 SSD based on a voltage drop in the host power supply.

[0090] Optionally, during the process of using backup power (capacitor) for power supply, the power management circuit also spontaneously generates a PLN signal and transmits it to the PLN signal pin 1 of the M.2 SSD through the PLN signal output terminal, triggering the M.2 SSD to continue preparing for power failure, such as continuing to write the content related to power-on initialization to the NAND flash memory. Alternatively, if the power management circuit recognizes that the host issued a PLN signal before the power failure and has already provided a PLN signal to the M.2 SSD based on this PLN signal, in response, when the backup power supply continues to power the M.2 SSD, the power management circuit will no longer generate a PLN signal to avoid the M.2 SSD re-executing the power failure process.

[0091] based on Figure 3A and Figure 3BAs shown, when a U.2 SSD is connected to a host that does not support PLN, the host does not provide a PLN signal before power loss. The power management circuit then supplies power to the M.2 SSD using a capacitor as a backup power source after the host stops supplying power. During this backup power supply period, the M.2 SSD prepares for power loss. When a U.2 SSD is connected to a host that supports PLN, the host provides a PLN signal before power loss. This PLN signal is forwarded to the M.2 SSD by the power management circuit. Alternatively, the power management circuit generates a PLN signal based on the PLN signal provided by the host and provides it to the M.2 SSD. During the short period of power supply from the host, the M.2 SSD prepares for power loss. After the host stops supplying power, the power management circuit continues to supply power to the M.2 SSD based on the power provided by the capacitor. During this capacitor-powered period, the M.2 SSD continues to prepare for power loss.

[0092] The form factor of M.2 SSDs is limited, thus restricting the number of NVM chips that can be installed on an M.2 SSD. U.2 SSDs, on the other hand, have a larger form factor than M.2 SSDs, making them more suitable for accommodating a larger number of NVM chips to provide greater storage capacity. According to embodiments of this invention, U.2 SSDs with different capacity specifications are obtained by accommodating more M.2 SSDs within a U.2 SSD.

[0093] Example 2

[0094] Figure 4A A schematic diagram of the structure of a U.2SSD provided in another embodiment of the present invention is shown.

[0095] U.2 SSDs include an adapter board (for M.2 to U.2 conversion) and at least two M.2 SSDs mounted on the adapter board. Figure 4A The diagram illustrates the configuration of two M.2 SSDs. It should be understood that because U.2 SSDs use the U.2 standard size, the number of M.2 SSDs that can be configured with a U.2 SSD is limited. By configuring two, three, or other numbers of M.2 SSDs on the adapter board, different capacity U.2 SSDs can be obtained.

[0096] Multiple M.2 SSDs located within the same U.2 SSD need to communicate with each other to work together to achieve a large capacity U.2 SSD. In particular, when the U.2 SSD only provides a single PCIe interface, it is not possible to connect multiple M.2 SSDs to the U.2 PCIe interface.

[0097] In this embodiment, for a U.2 SSD, at least two M.2 SSDs are configured, and the M.2 SSDs are connected to each other via a die-to-die link (inter-die communication interconnect or inter-die interconnect) to enable the use of multiple M.2 SSDs to provide a large-capacity storage device. Chinese patent application number 202311240753.5 describes a scheme that utilizes multiple control components via inter-die interconnects to collaboratively implement a storage device.

[0098] Each M.2 SSD mounted on the adapter board includes a Die Link connector for connecting the signals of the inter-die interconnect to the adapter board. The Die Link connector includes pins for all signals corresponding to the inter-die interconnect. Since the M.2 SSD is mounted to the adapter board via an M.2 slot, the M.2 slot determines the relative position of the M.2 SSD and the adapter board, thus determining the position where the Die Link connector connects to the adapter board. The Die Link connector, for example, is a gold finger for each signal, located on the edge of the circuit board where the M.2 SSD is located, and it mates with the gold fingers on the adapter board. Alternatively, the Die Link connector could be a solder pad for each signal. The Die Link connector can also be a board-to-board connector. The Die Link connector can also be a flexible PCB (Printed Circuit Board) connected to the adapter board via the connector. Flexible PCBs facilitate connection to the adapter board after the M.2 SSD is inserted into the M.2 slot.

[0099] like Figure 4B As shown, the inter-die interconnect includes the connection between the Die Link connectors of the two M.2 SSDs (located on the adapter board) and the connection between the internal control components of each M.2 SSD and the Die Link connector (located on the M.2 SSD's circuit board). The inter-die interconnect does not require connection to the DRAM and / or NVM chips inside the M.2 SSD.

[0100] For each of the at least two M.2 SSDs deployed on the adapter board, the power pin 1 of its M.2 PCIe interface is connected to the power output terminal of the power management circuit on the adapter board. After receiving power from the host or from the capacitor serving as a backup power supply, the power management circuit supplies power to the power pin 1 of the M.2 PCIe interface of each M.2 SSD through the power output terminal, thus powering the M.2 SSD.

[0101] For at least two M.2 SSDs mounted on the adapter board, at least one M.2 SSD's M.2 PCIe interface PLN signal pin 1 is connected to the PLN signal output terminal of the power management circuit. Figure 4A This illustration shows that the PLN signal pin 1 of both M.2 SSDs is connected to the PLN signal output terminal of the power management circuit. After receiving the PLN signal from the host or generating its own PLN signal, the power management circuit provides the PLN signal to the PLN signal pin 1 connected to the PLN signal output terminal, thus transmitting the PLN signal to the corresponding M.2 SSD. The M.2 SSD receiving the PLN signal executes the abnormal power-down processing procedure. For M.2 SSDs whose PLN signal pin 1 is not connected to the PLN signal output terminal of the power management circuit, it receives a warning message indicating an impending power-down, sent by the M.2 SSD receiving the PLN signal through the inter-die interconnect link. In response to receiving this warning message, the corresponding M.2 SSD also executes the abnormal power-down processing procedure.

[0102] For at least two M.2 SSDs mounted on the adapter board, at least one M.2 SSD's M.2 PCIe interface is connected to the U.2 PCIe interface in the U.2 connector. One or more M.2 SSDs' M.2 PCIe interfaces are not connected to the U.2 PCIe interface in the U.2 connector. Thus, the host only communicates with the M.2 SSD connected to the U.2 PCIe interface, and this M.2 SSD forwards data to the M.2 SSD not connected to the U.2 PCIe interface via the inter-die interconnect link to access the storage space provided by the M.2 SSD not connected to the U.2 PCIe interface. Furthermore, various types of data coordinated by the two control units are transmitted between the two M.2 SSDs via the inter-die interconnect link.

[0103] For example, the two M.2 SSDs within a U.2 SSD are designated SSD1 and SSD2. SSD1 is connected to the U.2 PCIe interface, while SSD2 is not. After receiving an I / O command from the host via the U.2 PCIe interface, SSD1 generates one or more storage commands. Based on the parity of the LBA address accessed by the storage command, it determines whether the storage command should be processed by itself or by SSD2. It then sends the storage commands that need to be processed by SSD2 to SSD2 via the inter-die interconnect link and receives the processing results. After all storage commands generated based on the I / O commands have been processed, SSD1 generates a completion message for the I / O commands and sends it to the host. Various schemes for co-processing host I / O commands by two control units interconnected via inter-die interconnect links are described in detail in Chinese patent applications 202311240753.5, 202311240800.6, 2023112408218, 2024108247773, 2024108247684 and 2024108247881, the full text of which is incorporated herein by reference.

[0104] exist Figure 4AIn the structure shown, the U.2SSD operates in a manner similar to... Figure 3A and Figure 3B The operation of a U.2 SSD is similar, with the power management circuit supplying power to the M.2 SSD based on power provided by the host or by capacitors. The difference lies in: Figure 4A The structure shown has two PLN response modes. If each M.2SSD is connected to the PLN signal output terminal of the power management circuit, each M.2SSD receives the PLN signal and performs power-down processing based on the PLN signal. If one of the M.2SSDs (such as M.2SSD1) receives the PLN signal, it performs power-down processing based on the PLN signal and notifies other M.2SSDs (such as M.2SSD2) through the inter-die interconnection link. M.2SSD2 performs power-down processing based on the received notification (such as a prompt message).

[0105] exist Figure 4A In the illustrated configuration, the U.2SSD is compatible with both PLN-supporting and PLN-unsupporting hosts. If the U.2SSD is connected to a PLN-supporting host, the host will send a PLN signal before power loss. The M.2SSD prepares for power loss based on this signal or a notification message. After the host stops supplying power, the power management circuit generates its own PLN signal and provides it to at least one M.2SSD. The M.2SSD continues to prepare for power loss based on this signal or a notification message, and the power management circuit trigger capacitor acts as a backup power source for the M.2SSD. If the U.2SSD is connected to a PLN-unsupporting host, after the host stops supplying power, the power management circuit generates its own PLN signal and provides it to at least one M.2SSD. The M.2SSD prepares for power loss based on this signal or a notification message, and the power management circuit trigger capacitor acts as a backup power source for the M.2SSD.

[0106] Example 3

[0107] Figure 5 A schematic diagram of the structure of a U.2SSD provided in another embodiment of the present invention is shown.

[0108] The U.2 SSD includes an adapter board (for M.2 to U.2 conversion) and three M.2 SSDs (M.2SSD_1, M.2SSD_2, and M.2SSD_3) mounted on the adapter board. M.2SSD_1 and M.2SSD_2 are connected via an inter-die interconnect, as are M.2SSD_2 and M.2SSD_3. The power pin 1 of the M.2PCIe interface of M.2SSD_1, M.2SSD_2, and M.2SSD_3 is connected to the power output of the power management circuit. The PLN signal pin 1 of the M.2PCIe interface of M.2SSD_1 is connected to the PLN signal output of the power management circuit, while the PLN signal pin 1 of the M.2PCIe interfaces of M.2SSD_2 and M.2SSD_3 is not connected to the PLN signal output of the power management circuit. After generating a PLN signal or receiving a PLN signal from the host, the power management circuit provides the PLN signal to M.2SSD_1. M.2SSD_1 then provides an indication message that a power failure is about to occur to M.2SSD_2 through the inter-die interconnect link between M.2SSD_1 and M.2SSD_2. Upon receiving the indication message, M.2SSD_2 provides the same indication message to M.2SSD_3 through the inter-die interconnect link between M.2SSD_2 and M.2SSD_3.

[0109] The U.2 PCIe interface in the U.2 connector connects to the M.2 PCIe interface in the M.2 connector of M.2SSD_1. The M.2 PCIe interfaces of M.2SSD_2 and M.2SSD_3 are not connected to the U.2 PCIe interfaces in the U.2 connector. M.2SSD_2 receives data (such as storage commands generated based on IO commands) provided by the host and forwarded by M.2SSD_1 via the inter-die interconnect link with M.2SSD_1, and also receives various types of data coordinated between the two control units via the same inter-die interconnect link. M.2SSD_3 receives data sent by the host, forwarded to M.2SSD_2 via M.2SSD_1, and provided by M.2SSD_2 (such as storage commands generated based on IO commands) through the inter-die interconnect link with M.2SSD_2. It also receives various types of data coordinated between the two control units through the inter-die interconnect link with M.2SSD_2.

[0110] Figure 5 The provided U.2SSD works in the same way as Figure 4A The U.2SSD provided works in the same way, so it will not be repeated here.

[0111] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A U.2 storage device, characterized in that, include: An adapter board, and at least one M.2 storage device disposed on the adapter board; The M.2 storage device includes an M.2 connector, the M.2 connector includes an M.2 PCIe interface, and the M.2 PCIe interface includes a first power pin and a first data pin; The adapter board includes a U.2 connector, a power management circuit, and at least one capacitor as a backup power source. The U.2 connector includes a U.2 PCIe interface, which includes a second power pin and a second data pin. The first power terminal of the power management circuit is connected to the second power pin, and the second power terminal is connected to at least one capacitor. The power output terminal of the power management circuit is connected to the first power pin of the M.2 storage device, and the second data pin is connected to the first data pin. The power management circuit provides power from the first power terminal or the second power terminal to the first power pin of the M.2 storage device through the power output terminal.

2. The U.2 storage device according to claim 1, characterized in that, The power management circuit provides power from the second power supply terminal to the first power pin of the M.2 storage device when there is no power supply from the first power supply terminal.

3. The U.2 storage device according to claim 1, characterized in that, The adapter board is provided with an M.2 slot, and the M.2 storage device is connected to the adapter board through the M.2 slot.

4. The U.2 storage device according to claim 1, characterized in that, The second data pin is connected to the first data pin via a connection line laid on the adapter board between the second data pin and the first data pin.

5. The U.2 storage device according to claim 1, characterized in that, The power management circuit provides power from the first power supply terminal to the first power pin of the M.2 storage device, and / or the second power supply terminal, based on the availability of power at the first power supply terminal.

6. The U.2 storage device according to claim 1, characterized in that, The M.2PCIe interface also includes a first PLN signal pin, and the U.2PCIe interface also includes a second PLN signal pin; The power management circuit connects the first PLN signal pin and the second PLN signal pin; the power management circuit provides the PLN signal from the second PLN signal pin or the PLN signal generated when there is no power supply from the first power supply pin to the first PLN signal pin.

7. The U.2 storage device according to any one of claims 1 to 6, characterized in that, At least two M.2 storage devices are arranged on the adapter board, and each M.2 storage device includes a control component; The two control units corresponding to the two M.2 storage devices are connected via an inter-die interconnect link.

8. The U.2 storage device according to claim 7, characterized in that, The M.2 storage device includes a Die Link connector, which is connected to the control component inside the M.2 storage device. The Die Link connector is located on the edge of the circuit board where the M.2 storage device is located, and is connected to the contacts on the adapter board.

9. The U.2 storage device according to claim 7, characterized in that, The at least two M.2 storage devices include a first storage device and at least one second storage device; The first PLN signal pins corresponding to the first storage device and the at least one second storage device are respectively connected to the PLN signal output terminal of the power management circuit, and the first storage device and the at least one second storage device receive the PLN signal provided by the power management circuit through the PLN signal output terminal. or The first PLN signal pin of the first storage device is connected to the PLN signal output terminal of the power management circuit, while the first PLN signal pin of the second storage device is not connected to the PLN signal output terminal of the power management circuit.

10. The U.2 storage device according to claim 9, characterized in that, The first data pins in the M.2 PCIe interfaces corresponding to the first storage device and the at least one second storage device are all connected to the second data pins in the U.2 PCIe interface; or The first data pin in the M.2 PCIe interface of the first storage device is connected to the second data pin in the U.2 PCIe interface, while the first data pin in the M.2 PCIe interface of the second storage device is not connected to the second data pin in the U.2 PCIe interface.

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