Logic operation device and chip

Abstract

The utility model provides a kind of logic operation device and chip;Logic operation device includes: level encoding module, level calibration module, logic operation module and output judging module;The input end of level encoding module is used to receive the first digital logic signal of the decimal value, level encoding module, for converting the first analog voltage signal of first digital logic signal;Level calibration module, for outputting the reference voltage signal after calibration, the output end of level calibration module is connected with the reference voltage input end of output judging module;Logic operation module, for logic operation based on the first analog voltage signal, and output second analog voltage signal;Output judging module, for converting the second digital logic signal of the decimal value of second analog voltage signal。Through the utility model, the logic operation efficiency of decimal data source can be improved.

Description

Technical Field

[0001] This utility model relates to integrated circuit and chip technology, and in particular to a logic operation device and chip. Background Technology

[0002] In related technologies, the logic operation systems of general-purpose digital integrated circuits, field-programmable gate arrays (FPGAs), microcontroller units (MCUs), and central processing units (CPUs) are all built on binary Boolean logic (0 / 1 binary levels). Logic operations rely on basic binary gate circuits such as AND gates, OR gates, NOT gates, and NAND gates. However, with the explosive growth of demand for AI matrix reasoning and large-scale decimal business operations, the limitations of traditional binary architecture have become increasingly apparent: extremely low information density and huge conversion overhead. When processing decimal data, a large number of redundant binary encoding and decoding conversions and multiple iterative judgments are required, resulting in high computational latency, limited throughput, and a surge in device power consumption. This, in turn, leads to an increase in device failure rate (FIT) and a shortened mean time between failures (MTBF). Multilevel technology cannot achieve breakthroughs in low-level computing. Multilevel technologies such as four-level pulse amplitude modulation (PAM4) and eight-level pulse amplitude modulation (PAM8) are currently only used for signal modulation and demodulation of high-speed interfaces. They cannot realize native hardware logic operations, and data still needs to be converted back to binary before entering the computing core, thus failing to improve computing power from the bottom layer. Utility Model Content

[0003] This utility model provides a logic operation device and chip that can improve the logic operation efficiency of decimal data sources.

[0004] The technical solution of this utility model embodiment is implemented as follows: This utility model provides a logic operation device, which includes: a level encoding module, a level calibration module, a logic operation module, and an output judgment module; The input terminal of the level encoding module is used to receive a first digital logic signal representing a decimal value, and the level encoding module is used to convert the first digital logic signal into a first analog voltage signal. The output terminal of the level encoding module is connected to the signal receiving terminal of the logic operation module via a first signal line. The signal receiving terminal of the logic operation module is used to receive the first analog voltage signal. The output terminal of the level encoding module is connected to the input terminal of the level calibration module via another signal line. The input terminal of the level calibration module is used to receive the first analog voltage signal. The level calibration module is used to output a calibrated reference voltage signal, and the output terminal of the level calibration module is connected to the reference voltage input terminal of the output judgment module. The logic operation module is used to perform logic operations based on the first analog voltage signal and output a second analog voltage signal; The output terminal of the logic operation module is connected to the input terminal of the output judgment module via a second signal line. The input terminal of the output judgment module is used to receive the second analog voltage signal. The reference voltage input terminal of the output judgment module is connected to the output terminal of the level calibration module. The output judgment module is used to convert the second analog voltage signal into a second digital logic signal representing a decimal value.

[0005] In some embodiments, the level encoding module includes a reference voltage source, a voltage divider resistor array, and a buffer amplifier. One end of the voltage divider resistor array is connected to the reference voltage source. The input terminal of the voltage divider resistor array is used to receive a first digital logic signal representing a decimal value. The output terminal of the voltage divider resistor array is used to output the first analog voltage signal.

[0006] In some embodiments, the reference voltage source is used to output a reference voltage, and the voltage divider resistor array is used to divide the reference voltage into ten level signals in equal proportions. Each voltage divider node in the voltage divider resistor array is connected to a different buffer amplifier.

[0007] In some embodiments, the level calibration module includes: a temperature sensor, a bandgap reference source, a feedback calibration circuit, a multiplexer, and a voltage comparator array; The input terminal of the voltage comparator array is connected to one end of the level encoding module, one end of the bandgap reference source is connected to one end of the voltage comparator array, one end of the temperature sensor is connected to one end of the voltage comparator array, the output terminal of the voltage comparator array is connected to the input terminal of the feedback calibration circuit, the output terminal of the feedback calibration circuit is connected to one end of the multiplexer, and the output terminal of the multiplexer is used to output the calibrated reference voltage signal.

[0008] In some embodiments, the feedback calibration circuit includes: a successive approximation register, a calibration analog-to-digital converter, and an error detector. One end of the successive approximation register is connected to one end of the voltage comparator array, the other end of the successive approximation register is connected to the calibration analog-to-digital converter, the other end of the calibration analog-to-digital converter is connected to the error detector, and one end of the error detector is connected to one end of the multiplexer.

[0009] In some embodiments, the logic operation module includes multiple hardware logic operation units, the input terminals of the hardware logic operation units are connected to the output terminals of the level encoding module, and the output terminals of the hardware logic operation units are connected to the input terminals of the output judgment module.

[0010] In some embodiments, the types of the logical operations include: AND, OR, NOT, and XOR.

[0011] In some embodiments, the plurality of hardware logic operation units include: a first hardware logic operation unit for performing AND operation, a second hardware logic operation unit for performing OR operation, a third hardware logic operation unit for performing NOT operation, and a fourth hardware logic operation unit for performing XOR operation. The non-inverting input of the third hardware logic operation unit is connected to one end of the level calibration module, and the inverting input of the third hardware logic operation unit is connected to the output of the level encoding module.

[0012] In some embodiments, the output judgment module includes: a multi-channel comparator array; one end of the multi-channel comparator array is connected to the output terminal of the level calibration module, and the other end of the multi-channel comparator array is connected to the output terminal of the logic operation module, and the multi-channel comparator array outputs the second digital logic signal.

[0013] This utility model provides a chip, which includes the logic operation device described in this utility model embodiment.

[0014] The present invention has the following beneficial effects: Because the level encoding module can directly convert the received first digital logic signal representing a decimal value into a first analog voltage signal, and transmit it to the logic operation module and the level calibration module respectively through a single signal line, while the logic operation module also outputs a second analog voltage signal through a single signal line, this significantly improves the information transmission density of a single signal line and optimizes the hardware wiring architecture. By mapping multi-state decimal digital signals to analog voltage signals, a single physical signal line can carry multi-value information, thereby greatly increasing the data information capacity per unit physical channel and simplifying the underlying wiring requirements of the chip or circuit board. The logic operation module directly receives the first analog voltage signal and performs logic operations based on the analog voltage signal itself, and then outputs the calculated second analog voltage signal. This allows the operation process to occur directly in the analog voltage domain, without needing to pre-decompose the decimal data into multiple binary states for iterative calculation in the gate circuit network, thus achieving efficient processing of decimal information, improving the overall data throughput of the logic operation device, and increasing data processing efficiency. The device incorporates an independent level calibration module. This module synchronously receives the first analog voltage signal and generates a calibrated reference voltage signal, which is then sent to the output judgment module. Upon receiving the second analog voltage signal after logic processing, the output judgment module uses this calibrated reference voltage signal to make a judgment, ultimately converting the second analog voltage signal into a second digital logic signal. This ensures that the final signal output judgment has a synchronous calibration reference, guaranteeing accurate determination of the logic operation result during analog-to-digital conversion, improving computational accuracy, and enhancing the accuracy of analog-to-digital signal conversion and the reliability of the system output. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of the logic operation device provided in this embodiment of the utility model; Figure 2 This is a schematic diagram of the correspondence between voltage level divisions provided in an embodiment of the present invention; Figure 3 This is a schematic representation of the decimal values ​​and the true values ​​of operations provided in this embodiment of the utility model; Figure 4 This is a schematic representation of the decimal value or operational truth value provided in this embodiment of the utility model; Figure 5 This is a schematic representation of the true value of the decimal XOR operation provided in this embodiment of the utility model; Figure 6 This is a schematic representation of the decimal NOT operation truth value provided in this embodiment of the utility model; Figure 7 This is a schematic diagram of the level calibration module provided in this embodiment of the utility model; Figure 8This is a timing diagram for single-cycle signal processing provided in an embodiment of the present invention.

[0016] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on the present utility model. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0018] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein.

[0020] In this embodiment of the invention, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0022] Before providing a further detailed description of the embodiments of this utility model, the nouns and terms involved in the embodiments of this utility model will be explained, and the nouns and terms involved in the embodiments of this utility model are subject to the following interpretations.

[0023] 1) Level Encoding: This is a baseband line encoding method that directly maps binary data (0 / 1) or multi-level symbols using different voltage level states. Its core feature is that the level remains constant (does not return to zero) or jumps according to rules within the symbol period, and information is distinguished by high / low level and polarity (positive / negative / zero). In this embodiment of the present invention, level encoding is the process of establishing a one-to-one correspondence between abstract logical values ​​in the digital domain that do not have continuous physical amplitude (such as decimal numbers 0, 1, 2...9) and a set of physical potentials in the analog domain with definite absolute voltage values ​​(such as 0.1V, 0.2V...1.0V), and outputting this specific voltage through hardware circuitry.

[0024] 2) Pulse-Amplitude Modulation (PAM): This is a pulse modulation technique that transmits information by changing the amplitude of a carrier pulse. The core feature of PAM is to keep the pulse duration and position constant, while making the pulse amplitude change periodically with the modulating signal, thus achieving discretization sampling of continuous signals. Based on the sampling method, it can be divided into two categories: natural sampling and flat-top sampling. Flat-top sampling maintains voltage stability through a holding circuit.

[0025] In related technologies, logic operation systems have undergone decades of development, resulting in mature technology, strong anti-interference capabilities, and stable timing convergence, making them the mainstream logic operation method in modern digital circuits.

[0026] However, the binary architecture of digital circuits in related technologies has the following problems: First, a single signal line and a single clock cycle can only carry 1 binary digit (BIT) of information, resulting in extremely low information density. When performing decimal business operations, artificial intelligence inference matrix operations, and high-precision financial calculations, a large number of binary encoding / decoding conversions and multiple iterative judgments are required, leading to high computational latency and limited throughput. Second, existing multi-level technologies such as four-level pulse amplitude modulation (PAM4) and eight-level pulse amplitude modulation (PAM8) are only used for high-speed transmission interfaces, capable of only level modulation and demodulation, and cannot achieve native hardware logic operations. After transmission, the data must be converted back to binary logic, failing to improve computational efficiency from the underlying layer. Third, current research on multi-valued logic largely remains at the theoretical simulation level of ternary and quaternary logic, lacking mature and mass-producible ten-level hardware implementation solutions. Furthermore, it lacks reliability calibration mechanisms under high and low temperature conditions, failing to meet the high-temperature operating life (HTOL) and mean time between failures (MTBF) reliability requirements of industrial-grade, automotive-grade, and server-grade chips. Fourth, binary processing of decimal data incurs significant redundant conversion overhead, and multiple judgment iterations lead to increased device power consumption and higher device failure rates. Increased Time (FIT) leads to decreased system MTBF lifespan.

[0027] Therefore, there is an urgent need for a new computing architecture that can be mass-produced in hardware, has reliable calibration capabilities, can natively implement decimal logic operations, and enables high-density transmission in a single channel.

[0028] This utility model provides a logic operation device and chip to address the aforementioned problems in related technologies, thereby improving the logic operation efficiency of decimal data sources.

[0029] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the logic operation device provided in this embodiment of the present invention. This embodiment of the present invention provides a logic operation device, which includes: a level encoding module 101, a level calibration module 102, a logic operation module 103, and an output judgment module 104.

[0030] The input terminal of the level encoding module is used to receive the first digital logic signal representing a decimal value. The level encoding module is used to convert the first digital logic signal into a first analog voltage signal.

[0031] The output of the level encoding module is connected to the signal receiving end of the logic operation module via a first signal line. The signal receiving end of the logic operation module is used to receive the first analog voltage signal. The output of the level encoding module is connected to the input of the level calibration module via another signal line. The input of the level calibration module is used to receive the first analog voltage signal. In some embodiments, the level encoding module includes a reference voltage source, a voltage divider resistor array, and a buffer amplifier. One end of the voltage divider resistor array is connected to the reference voltage source. The input end of the voltage divider resistor array is used to receive a first digital logic signal representing a decimal value, and the output end of the voltage divider resistor array is used to output a first analog voltage signal.

[0032] In some embodiments, a reference voltage source is used to output a reference voltage, and a voltage divider resistor array is used to divide the reference voltage into ten level signals in equal proportions. Each voltage divider node in the voltage divider resistor array is connected to a different buffer amplifier.

[0033] For example, the level encoding module uses a reference voltage source and a voltage divider resistor array to generate ten levels. The ten step levels are evenly divided within the preset power supply range, corresponding to decimal 0 to 9 respectively. Each voltage level is equipped with an independent buffer operational amplifier to ensure load consistency and edge integrity.

[0034] For example, assuming a reference voltage of 1V, the voltage divider array maps the decimal digits 0-9 into ten independent, equally spaced discrete voltage level signals according to a preset voltage ratio, resulting in the first analog voltage signal. For instance, using a 1.0V high-precision reference source with temperature drift compensation, paired with nine 0.1% precision voltage divider resistors, ten voltage levels are evenly distributed: 0.0V, 0.1V, 0.2V…0.9V, corresponding to decimal 0-9 respectively. Each level is output through a rail-to-rail buffered operational amplifier to ensure load capacity and prevent level collapse. 1V is the reference voltage, and the span of a single level is 0.1V, with ten levels spanning 0.9V (0.1V is the first level level). Reference Figure 2 , Figure 2 This is a schematic diagram illustrating the voltage level correspondence provided in this embodiment of the invention. Number 0 corresponds to 0V, number 1 to 0.1V, number 2 to 0.2V, number 3 to 0.3V, number 4 to 0.4V, number 5 to 0.5V, number 6 to 0.6V, number 7 to 0.7V, number 8 to 0.8V, and number 9 to 0.9V. The noise margin window for each voltage level is centered at the corresponding voltage value and extends 20mV above and below it. For example, the noise margin window for number 1 is centered at 0.1V, and the range of the noise margin window for number 1 is [0.1V-20mV, 0.1V+20mV].

[0035] Continue to refer to Figure 1 The level calibration module is used to output the calibrated reference voltage signal. The output terminal of the level calibration module is connected to the reference voltage input terminal of the output judgment module.

[0036] For example, the level calibration module is electrically connected to the level encoding module. The level calibration module includes devices for real-time acquisition of operating temperature, power fluctuations, and signal crosstalk noise. The feedback calibration circuit in the level calibration module adaptively adjusts the reference voltage threshold to dynamically compensate for the level judgment window of each level and filter out in-band random noise. The judgment tolerance window can be set to ±0.03V. When temperature drift or power fluctuation is detected, the judgment window is automatically widened or narrowed to ensure zero false judgment of level identification under high and low temperature HTOL conditions.

[0037] Assumptions: The preset judgment tolerance is ±0.03V. When the temperature exceeds 85℃ or the power supply ripple exceeds 0.05V, the system automatically widens the judgment window to ±0.04V to compensate for high-temperature drift errors. Under long-term HTOL aging conditions at 125℃, the reference voltage is corrected in real time to ensure that the range offset is less than 0.02V and there are no judgment errors. The widening or narrowing range of the judgment window is ±0.02V to avoid judgment distortion caused by an excessively wide range.

[0038] In some embodiments, the level calibration module includes: a temperature sensor, a bandgap reference source, a feedback calibration circuit, a multiplexer, and a voltage comparator array. (Reference) Figure 7 , Figure 7 This is a schematic diagram of the level calibration module provided in this embodiment of the present invention. The temperature sensor can be an on-chip temperature sensor, and the level calibration module includes: an on-chip temperature sensor 220, a bandgap reference source 230, a feedback calibration circuit 210, a multiplexer 260, and a voltage comparator array 240.

[0039] The input of the voltage comparator array is connected to one end of the level encoding module, one end of the bandgap reference source is connected to one end of the voltage comparator array, one end of the temperature sensor is connected to one end of the voltage comparator array, the output of the voltage comparator array is connected to the input of the feedback calibration circuit, the output of the feedback calibration circuit is connected to one end of the multiplexer, and the output of the multiplexer is used to output the calibrated reference voltage signal.

[0040] For example, a bandgap reference source is a core circuit in analog integrated circuits that provides a reference voltage or current, widely used in high-precision comparators, data converters, and other fields. A bandgap reference source achieves a reference output independent of process and temperature variations by canceling out the positive and negative temperature coefficients of the base-emitter voltage difference in a bipolar transistor. A bandgap reference source includes a temperature compensation network, which can be constructed using a Complementary To Absolute Temperature (CTAT) resistor and a Proportional To Absolute Temperature (CTAT) resistor. The bandgap reference voltage source utilizes the superposition of the PTAT and CTAT voltages to achieve a temperature-stable voltage output: the CTAT term cancels out the temperature drift of the PTAT term; by adjusting the ratio of the two, a reference voltage with zero temperature coefficient (e.g., 1.0V) can be achieved.

[0041] In some embodiments, continue to refer to Figure 7 The feedback calibration circuit 210 includes: a successive approximation register 211, a calibration analog-to-digital converter 212, and an error detector 213. One end of the successive approximation register is connected to one end of the voltage comparator array, the other end of the successive approximation register is connected to the calibration analog-to-digital converter, the other end of the calibration analog-to-digital converter is connected to the error detector, and one end of the error detector is connected to one end of the multiplexer.

[0042] The analog input terminal 250 (Vin) of the voltage comparator array receives the signal to be compared. This signal can be the output signal of the level encoding module. The comparison result of the voltage comparator array is output to the successive approximation register. The error detector outputs a reference voltage code, which is transmitted to the multiplexer via the Vref bus. The multiplexer outputs Vref out as the corrected reference voltage value. Vref out contains a compensation bias that is opposite to the main data signal and is fed forward / injected into the subsequent logic operation module and output judgment module.

[0043] For example, the Successive Approximation Register (SAR) is a common implementation architecture for analog-to-digital converters (ADCs). Based on a binary search algorithm, the SAR register acquires the input analog voltage through a sample-and-hold circuit. Then, an internal digital-to-analog converter (DAC) generates a reference voltage sequentially from the most significant bit (MSB) to the least significant bit (LSB), compares it with the input voltage, and finally determines the digital code for each bit, completing the analog-to-digital conversion. SAR ADCs feature moderate conversion speed (typically below 10 MSPS), medium to high resolution (8-18 bits), low power consumption, small size, and zero latency, and are widely used in industrial control, portable instruments, medical devices, data acquisition systems, and battery-powered equipment. A calibration DAC is a device that converts digital signals into analog signals. The calibration DAC is a crucial bridge connecting digital systems and analog actuators. Its core function is to receive binary digital input and convert it into the corresponding analog signal through internal precision circuitry. It is widely used in audio playback, industrial control, and communication systems.

[0044] Continue to refer to Figure 1 The logic operation module is used to perform logic operations based on the first analog voltage signal and output a second analog voltage signal. The output terminal of the logic operation module is connected to the input terminal of the output judgment module through a second signal line. The input terminal of the output judgment module is used to receive the second analog voltage signal. The reference voltage input terminal of the output judgment module is connected to the output terminal of the level calibration module.

[0045] In some embodiments, the logic operation module includes multiple hardware logic operation units, the input terminals of the hardware logic operation units are connected to the output terminals of the level encoding module, and the output terminals of the hardware logic operation units are connected to the input terminals of the output judgment module.

[0046] In some embodiments, the types of logical operations include: AND, OR, NOT, and XOR.

[0047] For example, the logic operation rules are as follows: AND operation takes the minimum value of the two input values, OR operation takes the maximum value of the two input values, NOT operation takes 9 minus the input value, and XOR operation takes the absolute value of the difference between the two input values. All operations are completed by direct comparison based on analog levels.

[0048] In some embodiments, the plurality of hardware logic operation units include: a first hardware logic operation unit for performing an AND operation, a second hardware logic operation unit for performing an OR operation, a third hardware logic operation unit for performing a NOT operation, and a fourth hardware logic operation unit for performing an XOR operation; the non-inverting input terminal of the third hardware logic operation unit is connected to one end of the level calibration module, and the inverting input terminal of the third hardware logic operation unit is connected to the output terminal of the level encoding module.

[0049] For example, regarding the first hardware logic unit used to perform an AND operation, the first hardware logic unit can be a minimum selector circuit. The rule for the AND operation is to take the minimum value of the two input values. The minimum selector circuit is used to filter and output the signal with the lowest level. (See reference) Figure 3 , Figure 3 This is a schematic representation of the true value of the AND operation provided in this embodiment of the utility model. Assuming input signals A and B, performing an AND operation is represented by the formula Min(A·B), selecting the signal with the lowest level between signals A and B as the calculation result.

[0050] For example, regarding the second hardware logic unit used to perform OR operations, the second hardware logic unit can be a maximum selector circuit, or the operation rule is to take the maximum value of two input values. The maximum selector circuit receives the input signals in parallel and automatically outputs the signal with the highest level. (See reference) Figure 4 , Figure 4 This is a schematic representation of the true value of the OR operation provided in this embodiment of the utility model. Assuming input signals A and B, the OR operation is performed, represented by the formula max(A·B), and the signal with the highest level between signals A and B is selected as the calculation result.

[0051] For example, regarding the third hardware logic unit used to perform the NOT operation, the third hardware logic unit can be an analog subtractor or a differential amplifier. The third hardware logic unit consists of an operational amplifier (Op-Amp) and a precision resistor network. The reference voltage representing logic 9 is received through the non-inverting input of the third hardware logic unit, the input signal is received through the inverting input of the third hardware logic unit, and the output is a difference level. (Reference) Figure 6 , Figure 6This is a schematic representation of the decimal NOT operation truth value provided in this embodiment of the utility model. Input signal A, then output the difference between the reference voltage signal and signal A. The reference voltage signal is represented by the digit 9, and the NOT operation is performed, expressed as formula (9-A).

[0052] For example, regarding the fourth hardware logic unit used to perform the XOR operation, the fourth hardware logic unit could be an absolute difference circuit, which includes an analog subtractor (calculating AB), a full-wave rectifier circuit (composed of operational amplifiers and diode networks, flipping a negative voltage to a positive voltage), and outputs the absolute difference of the signal levels. (Reference) Figure 5 , Figure 5 This is a schematic representation of the truth value of the ten-value XOR operation provided in this embodiment of the utility model. Assuming input signals A and B, the XOR operation is performed, represented by the formula |AB|, and the absolute value of the difference between signals A and B is selected as the calculation result.

[0053] Continue to refer to Figure 1 The output judgment module is used to convert the second analog voltage signal into a second digital logic signal representing a decimal value.

[0054] In some embodiments, the output judgment module includes: a multi-channel comparator array; one end of the multi-channel comparator array is connected to the output of the level calibration module, the other end of the multi-channel comparator array is connected to the output of the logic operation module, and the multi-channel comparator array outputs a second digital logic signal.

[0055] For example, the output judgment module completes the transmission of ten-level signals through a single differential or single-ended signal line, and outputs the corresponding decimal value at once through a multi-channel comparator array to realize a single logic operation.

[0056] For example, a multi-channel comparator array can be a 10-channel parallel high-speed comparator that completes the level range judgment in one go and outputs a one-bit decimal operation result in a single cycle, greatly reducing the number of logic judgments. A voltage comparator is a circuit that distinguishes and compares input signals and is a basic unit circuit for building non-sinusoidal wave generation circuits. Commonly used voltage comparators include single-limit comparators, hysteresis comparators, window comparators, and three-state voltage comparators. Voltage comparators can be used as interfaces between analog and digital circuits, and also as waveform generation and transformation circuits. A simple voltage comparator can convert a sine wave into a square wave or rectangular wave of the same frequency.

[0057] For example, a combination of high and low digital levels output by a 10-channel parallel comparator array after instantaneous flipping (such as typical thermometer code or directly encoded digital bitstream) completes the transition of the signal from the analog domain to the digital domain. The comparators strip away all analog continuous properties of the signal (amplitude, noise, edge slope), quantizing and reconstructing the signal into a perfectly clear combination of digital 0s and 1s, which is then output to the subsequent digital processor as the final decimal calculation result. By performing a single parallel sampling and judgment of the ten-level encoded signal carried on a single differential or single-ended signal line using the comparator array, the equivalent information content of a single sampling is log2¹0 ≈ 3.32 bits; compared to the traditional binary single-channel single-cycle 1-bit information density, in N-bit decimal numerical calculation scenarios, the number of logical judgment iterations is reduced from that of the binary scheme. N×log210 The number of times is reduced from 1 to N, effectively improving the system throughput rate.

[0058] refer to Figure 8 , Figure 8 This is a timing diagram for single-cycle signal processing provided in this embodiment of the invention. Level encoding is performed in cycles 0 to 2, with the encoding enable (ENCODE) at a high level. After the encoding generates a ten-level encoded value, the analog input (VIN) is at a high level. Level signal transmission occurs in cycles 2 to 4, signal calibration is performed in cycles 4 to 6, with the calibration enable (CALIB) at a high level, logic operations are performed in cycles 6 to 8, with the operation enable (OPERATE) at a high level, and output judgment is performed in cycles 8 to 10, with the output data (DATE OUT) at a high level.

[0059] In this embodiment of the invention, the single-signal line has a single-time equivalent information density of log210≈3.32 bits, which significantly reduces the number of computation iterations and clock cycles compared to binary encoding, resulting in a substantial increase in information density. It eliminates the need for repeated binary-to-decimal conversion, removing encoding / decoding redundancy overhead and reducing computational latency. It possesses dynamic calibration capabilities for temperature, voltage, and noise, and can withstand long-term aging at HTOL high temperatures, ensuring low FIT and high MTBF characteristics. Under the same throughput requirements, the number of signal lines is significantly reduced, lowering the complexity of PCB wiring and the risk of crosstalk. The architecture is simple and the wiring cost is low. Based on comparators, operational amplifiers, and voltage divider circuits, it requires no new process and is compatible with existing semiconductor production lines.

[0060] In this embodiment of the invention, ten discrete voltage levels corresponding to decimal digits 0-9 are used, enabling a single signal line to complete the reading of a decimal value and logical operation with a single sampling. Ten-value logic operation rules are defined to adapt to the hardware circuit, enabling native hardware operations such as AND, OR, NOT, and XOR without binary conversion. Simultaneously, temperature drift compensation, voltage tolerance adaptive calibration, and multi-level noise suppression structures address the problems of poor anti-interference, low reliability at high and low temperatures, and low tolerance for process drift in multi-level circuits. This improves the single-channel information transmission density and computational efficiency, reduces the number of logic iterations, and can be widely applied in high-speed logic operations, artificial intelligence inference calculations, high-speed serializer / deserializer interfaces, and embedded control chip scenarios, offering advantages such as high reliability, high throughput, and low latency.

[0061] This utility model embodiment also provides a chip, which includes the logic operation device of this utility model embodiment.

[0062] In summary, through this embodiment of the invention, the level encoding module can directly convert the received first digital logic signal representing a decimal value into a first analog voltage signal, and transmit it to the logic operation module and the level calibration module respectively through a single signal line. Simultaneously, the logic operation module also outputs a second analog voltage signal through a single signal line. This significantly improves the information transmission density of a single signal line and optimizes the hardware wiring architecture. By mapping multi-state decimal digital signals to analog voltage signals, a single physical signal line can carry multi-value information, thereby greatly increasing the data information capacity per unit physical channel and simplifying the underlying wiring requirements of the chip or circuit board. The logic operation module directly receives the first analog voltage signal and performs logic operations based on the analog voltage signal itself, then outputs the calculated second analog voltage signal. This allows the operation process to occur directly in the analog voltage domain, eliminating the need to pre-decompose the decimal data into multiple binary states for iterative calculation in the gate circuit network. This achieves efficient processing of decimal information, improves the overall data throughput of the logic operation device, and enhances data processing efficiency. The device incorporates an independent level calibration module. This module synchronously receives the first analog voltage signal and generates a calibrated reference voltage signal, which is then sent to the output judgment module. Upon receiving the second analog voltage signal after logic processing, the output judgment module uses this calibrated reference voltage signal to make a judgment, ultimately converting the second analog voltage signal into a second digital logic signal. This ensures that the final signal output judgment has a synchronous calibration reference, guaranteeing accurate determination of the logic operation result during analog-to-digital conversion, improving computational accuracy, and enhancing the accuracy of analog-to-digital signal conversion and the reliability of the system output.

[0063] Those skilled in the art will recognize that the modules of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware or a combination of software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different devices to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.

[0064] It should also be noted that, in this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, article, or apparatus that includes that element.

[0065] The above description is merely an embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this utility model are included within the scope of protection of this utility model.

Claims

1. A logic operation device, characterized in that, The logic operation device includes: a level encoding module, a level calibration module, a logic operation module, and an output judgment module; The input terminal of the level encoding module is used to receive a first digital logic signal representing a decimal value, and the level encoding module is used to convert the first digital logic signal into a first analog voltage signal. The output terminal of the level encoding module is connected to the signal receiving terminal of the logic operation module via a first signal line. The signal receiving terminal of the logic operation module is used to receive the first analog voltage signal. The output terminal of the level encoding module is connected to the input terminal of the level calibration module via another signal line. The input terminal of the level calibration module is used to receive the first analog voltage signal. The level calibration module is used to output a calibrated reference voltage signal, and the output terminal of the level calibration module is connected to the reference voltage input terminal of the output judgment module. The logic operation module is used to perform logic operations based on the first analog voltage signal and output a second analog voltage signal; The output terminal of the logic operation module is connected to the input terminal of the output judgment module via a second signal line. The input terminal of the output judgment module is used to receive the second analog voltage signal. The reference voltage input terminal of the output judgment module is connected to the output terminal of the level calibration module. The output judgment module is used to convert the second analog voltage signal into a second digital logic signal representing a decimal value.

2. The apparatus according to claim 1, characterized in that, The level encoding module includes a reference voltage source, a voltage divider resistor array, and a buffer amplifier. One end of the voltage divider resistor array is connected to the reference voltage source. The input end of the voltage divider resistor array is used to receive a first digital logic signal representing a decimal value. The output end of the voltage divider resistor array is used to output the first analog voltage signal.

3. The apparatus according to claim 2, characterized in that, The reference voltage source is used to output a reference voltage, and the voltage divider resistor array is used to divide the reference voltage into ten levels of signal level in equal proportion. Each voltage divider node in the voltage divider resistor array is connected to a different buffer amplifier.

4. The apparatus according to claim 1, characterized in that, The level calibration module includes: a temperature sensor, a bandgap reference source, a feedback calibration circuit, a multiplexer, and a voltage comparator array; The input terminal of the voltage comparator array is connected to one end of the level encoding module, one end of the bandgap reference source is connected to one end of the voltage comparator array, one end of the temperature sensor is connected to one end of the voltage comparator array, the output terminal of the voltage comparator array is connected to the input terminal of the feedback calibration circuit, the output terminal of the feedback calibration circuit is connected to one end of the multiplexer, and the output terminal of the multiplexer is used to output the calibrated reference voltage signal.

5. The apparatus according to claim 4, characterized in that, The feedback calibration circuit includes: a successive approximation register, a calibration analog-to-digital converter, and an error detector. One end of the successive approximation register is connected to one end of the voltage comparator array, the other end of the successive approximation register is connected to the calibration analog-to-digital converter, the other end of the calibration analog-to-digital converter is connected to the error detector, and one end of the error detector is connected to one end of the multiplexer.

6. The apparatus according to claim 1, characterized in that, The logic operation module includes multiple hardware logic operation units. The input terminal of each hardware logic operation unit is connected to the output terminal of the level encoding module, and the output terminal of each hardware logic operation unit is connected to the input terminal of the output judgment module.

7. The apparatus according to claim 6, characterized in that, The types of logical operations include: AND, OR, NOT, and XOR.

8. The apparatus according to claim 6, characterized in that, The plurality of hardware logic operation units include: a first hardware logic operation unit for performing AND operation, a second hardware logic operation unit for performing OR operation, a third hardware logic operation unit for performing NOT operation, and a fourth hardware logic operation unit for performing XOR operation. The non-inverting input of the third hardware logic operation unit is connected to one end of the level calibration module, and the inverting input of the third hardware logic operation unit is connected to the output of the level encoding module.

9. The apparatus according to claim 1, characterized in that, The output judgment module includes a multi-channel comparator array; one end of the multi-channel comparator array is connected to the output of the level calibration module, and the other end of the multi-channel comparator array is connected to the output of the logic operation module; the multi-channel comparator array outputs the second digital logic signal.

10. A chip, characterized in that, The chip includes a logic operation device as described in any one of claims 1 to 9.

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