Anti-lock circuit, communication bus, chip and electronic device

Abstract

The present disclosure provides a deadlock prevention circuit, a communication bus, a chip and an electronic device. The deadlock prevention circuit comprises a first signal terminal and a second signal terminal; the first signal terminal is electrically connected with a first signal line of the communication bus, and the second signal terminal is electrically connected with a second signal line of the communication bus; the deadlock prevention circuit is configured to output a reset signal to the second signal line in the case that the first signal line continuously transmits a first preset level; the reset signal is configured to control a slave device of the communication bus to end the state of continuously outputting the first preset level to the first signal line. In this way, the deadlock prevention circuit can automatically reset the slave device in the case that the master device and the slave device of the communication bus appear deadlock, so as to ensure the normal work of the communication bus.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to an anti-lockdown circuit, a communication bus, a chip, and an electronic device. Background Technology

[0002] A communication bus typically consists of a master device and a slave device, which cooperate to transmit data. In some scenarios, a deadlock can occur between the master and slave devices because both are waiting for the other to perform an action, thus affecting data transmission. Utility Model Content

[0003] This disclosure provides an anti-lockdown circuit, a communication bus, a chip, and an electronic device to solve the aforementioned technical problems.

[0004] According to a first aspect of this disclosure, an anti-lockdown circuit is provided, applicable to a communication bus, the anti-lockdown circuit comprising: a first signal terminal and a second signal terminal; the first signal terminal is electrically connected to a first signal line of the communication bus, and the second signal terminal is electrically connected to a second signal line of the communication bus; The anti-deadlock circuit is used to output a reset signal to the second signal line when the first signal line continuously transmits a first preset level; the reset signal is configured to control the slave device of the communication bus to stop continuously outputting the first preset level to the first signal line.

[0005] In one embodiment, the anti-deadlock circuit includes: a first switching circuit, a second switching circuit, and a logic circuit; the first switching circuit is electrically connected to the first signal terminal and the logic circuit respectively; the second switching circuit is electrically connected to the second signal terminal and the logic circuit respectively. The first switching circuit is used to output a clock signal to the logic circuit while the first signal line continuously transmits a first preset level; The logic circuit is used to output an enable control signal to the second switching circuit when a preset number of clock signals are received. The second switching circuit is used to output a reset signal to the second signal line when the enable control signal is received.

[0006] In one embodiment, the first switching circuit includes a first clock generator, a first switching device, and a first resistor; a first terminal of the first switching device is electrically connected to the first clock generator, a second terminal of the first switching device is electrically connected to the logic circuit and the first resistor respectively, and a control terminal of the first switching device is electrically connected to the first signal terminal; the second terminal of the first resistor is grounded. The first switching device is used to be in a conducting state when the first signal terminal is at a first preset level.

[0007] In one embodiment, the second switching circuit includes a second clock generator, a second switching device, and a second resistor; the first terminal of the second switching device is electrically connected to the first terminal of the second resistor and the second signal terminal, respectively; the second terminal of the second switching device is electrically connected to the second clock generator; the control terminal of the second switching device is electrically connected to the logic circuit; and the second terminal of the second resistor is electrically connected to a power supply. The second switching device is used to be in the on state when an enable control signal is received.

[0008] In one embodiment, the first switching device in the first switching circuit is implemented using a PMOS transistor, and / or the second switching device in the second switching circuit is implemented using an NMOS transistor.

[0009] In one embodiment, the first switching circuit and the second switching circuit are implemented using the same clock generator.

[0010] In one embodiment, the logic circuit includes a first counter and a flip-flop; the first counter is electrically connected to the first switching circuit and the flip-flop respectively; the flip-flop is electrically connected to the second switching circuit. The first counter is used to output a pulse signal to the trigger when a clock signal is received; The trigger is used to output an enable control signal to the second switching circuit when a pulse signal is received. The enable control signal is configured to control the second switching device in the second switching circuit to switch to the on state.

[0011] In one embodiment, the first counter includes a clock terminal, a reset terminal, and an output terminal; the flip-flop includes a clock terminal, an input terminal, and an output terminal. The clock terminal of the first counter is electrically connected to the first switching circuit, the reset terminal of the first counter is electrically connected to the first signal line, and the output terminal of the first counter is electrically connected to the clock terminal of the flip-flop. The input terminal of the trigger is electrically connected to the power supply, and the output terminal of the trigger is electrically connected to the second switching circuit.

[0012] In one embodiment, the logic circuit further includes a second counter; the second counter is electrically connected to the second switching circuit and the flip-flop, respectively; The second counter is used to output a reset signal to the trigger when a preset number of pulse signals are detected on the second signal line.

[0013] In one embodiment, the second counter includes a clock terminal and an output terminal; The clock terminal of the second counter is electrically connected to the second switching circuit, and the output terminal of the second counter is electrically connected to the reset terminal of the flip-flop.

[0014] According to a second aspect of this disclosure, a communication bus is provided, comprising: a first port, a second port, a first signal line, a second signal line, and an anti-lock-up circuit; the first port is used for electrical connection with a master device, and the second port is used for electrical connection with a slave device; a first signal line and a second signal line are provided between the first port and the second port; a first signal terminal of the anti-lock-up circuit is electrically connected to the first signal line, and a second signal terminal of the anti-lock-up circuit is electrically connected to the second signal line.

[0015] According to a third aspect of this disclosure, a chip is provided, including the anti-lockdown circuit as described in the first aspect.

[0016] According to a fourth aspect of this disclosure, an electronic device is provided, including an anti-lockdown circuit as described in the second aspect or a chip as described in the third aspect.

[0017] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: The anti-deadlock circuit provided in this embodiment includes: a first signal terminal and a second signal terminal; the first signal terminal is electrically connected to a first signal line of the communication bus, and the second signal terminal is electrically connected to a second signal line of the communication bus; the anti-deadlock circuit is used to output a reset signal to the second signal line when the first signal line continuously transmits a first preset level; the reset signal is configured to control the slave device of the communication bus to stop continuously outputting the first preset level to the first signal line. Thus, the anti-deadlock circuit of this embodiment can automatically reset the slave device in the event of a deadlock between the master and slave devices of the communication bus, ensuring the normal operation of the communication bus; furthermore, the anti-deadlock circuit in this embodiment can be set independently, integrated into the communication bus, or integrated into the master device and / or slave device, making it simple and easy to implement.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] Figure 1 This is a connection diagram of an anti-lockdown circuit according to an embodiment of the present disclosure.

[0020] Figure 2 This is a block diagram of an anti-lockdown circuit according to an embodiment of the present disclosure.

[0021] Figure 3 This is a circuit diagram of a first switching circuit according to an embodiment of the present disclosure.

[0022] Figure 4 This is a circuit diagram of a second switching circuit according to an embodiment of the present disclosure.

[0023] Figure 5 This is a block diagram of a logic circuit according to an embodiment of the present disclosure.

[0024] Figure 6 This is a block diagram of another logic circuit according to an embodiment of the present disclosure.

[0025] Figure 7 This is a block diagram of another logic circuit according to an embodiment of the present disclosure.

[0026] Figure 8 This is a block diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0028] Considering that communication buses can include I2C, RS-232, RS-485, SPI, USB, and CAN communication buses, deadlock may occur between the master and slave devices. Taking the I2C communication bus as an example, an I2C deadlock may occur, where the slave device is still communicating, waiting for the master device to pull the SCL signal low to release the acknowledgment signal; while the master device, after resetting, waits for the slave device to release the SDA signal; both are waiting for each other, and the I2C communication bus enters a deadlock state.

[0029] To address the aforementioned technical problems, this disclosure provides an anti-deadlock circuit, a communication bus, a chip, and an electronic device. The anti-deadlock circuit is designed to be connected in parallel between two signal lines of the communication bus. This anti-deadlock circuit can read signals from one signal line and, in the event of a deadlock, output a reset signal to the other signal line. This effectively replaces the master device in sending a reset signal to the slave device, thus resetting the slave device. In other words, it terminates the deadlock state between the master and slave devices, allowing them to resume normal data transmission.

[0030] Figure 1 This is a schematic diagram of the connection of an anti-lockdown circuit according to an embodiment of this disclosure. See also... Figure 1An anti-lock circuit 13 is applicable to a communication bus. The anti-lock circuit 13 includes: a first signal terminal T1 and a second signal terminal T2; the first signal terminal T1 is electrically connected to the first signal line S1 of the communication bus, and the second signal terminal T2 is electrically connected to the second signal line T2 of the communication bus. The anti-lock circuit 13 is used to output a reset signal to the second signal line T2 when the first signal line continuously transmits a first preset level; the reset signal is configured to control the slave device of the communication bus to stop continuously outputting the first preset level to the first signal line T1.

[0031] It should be noted that, taking the I2C communication bus as an example, the first signal line T1 is the SDA line, configured for bidirectional data transmission, as well as transmission of start, stop, and acknowledge signals; the second signal line T2 is the SCL line, configured for the master device to provide a clock signal unidirectionally to the slave device to synchronize data transmission and control the communication rate. For ease of description, the I2C communication bus will be used as an example to describe the solutions in subsequent embodiments.

[0032] Thus, the anti-deadlock circuit in this embodiment can automatically reset the slave device in the event of a deadlock between the master and slave devices on the communication bus, ensuring the normal operation of the communication bus. Furthermore, the anti-deadlock circuit in this embodiment can be set up independently, integrated into the communication bus, or integrated into the master device and / or slave device, making it simple and easy to implement.

[0033] In one embodiment, see Figure 2 The anti-lock circuit 13 includes a first switch circuit 131, a logic circuit 132, and a second switch circuit 133; the first switch circuit 131 is electrically connected to the first signal terminal T1 and the logic circuit 132 respectively; the second switch circuit 133 is electrically connected to the second signal terminal T2 and the logic circuit 132 respectively. The first switching circuit 131 is used to output a preset number of clock signals to the logic circuit 132 when the first signal line S1 continuously transmits a first preset level. Logic circuit 132 is used to output an enable control signal to the second switching circuit 133 when a preset number of clock signals are received; The second switching circuit 133 is used to output a reset signal to the second signal line S2 when an enable control signal is received.

[0034] In one embodiment, see Figure 3The first switching circuit 131 includes a first clock generator clk1, a first switching device Q1, and a first resistor R1. The first terminal of the first switching device Q1 is electrically connected to the first clock generator clk1, the second terminal of the first switching device Q1 is electrically connected to the logic circuit 132 and the first resistor R1, and the control terminal of the first switching device Q1 is electrically connected to the first signal terminal T1. The second terminal of the first resistor R1 is grounded to GND. The first switching device Q1 is used to be in a conducting state when the first signal terminal T1 is at a first preset level, so as to transmit the clock signal of the first clock generator clk1 to the logic circuit 132.

[0035] In the event of a deadlock between master device 11 and slave device 12, the slave device will occupy the first signal line S1, and slave device 12 will continuously output a first preset level to the first signal line S1. In other words, the characteristic of a deadlock between master device 11 and slave device 12 is that slave device 12 continuously outputs a first preset level to the first signal line S1.

[0036] In this way, the first switching circuit 131 can switch to the on state when the first signal line S1 continuously transmits the first preset level; when the first switching device Q1 is on, the clock signal of the first clock generator clk1 will be output to the logic circuit 132.

[0037] In one embodiment, the first switching device Q1 can be implemented using a PMOS transistor. In this scenario, the first preset level is low, and the PMOS transistor switches to the on state. If the first switching device Q1 is implemented using an NMOS transistor, the first preset level is high, and the NMOS transistor switches to the on state. It should be noted that the device type of the first switching device Q1 can be associated with the first preset level of the communication bus. When the first preset level is selectable or known, the first switching device Q1 can be adjusted accordingly, and the corresponding scheme falls within the protection scope of this disclosure.

[0038] In one embodiment, the first resistor R1 is used as a lower-level resistor. When the first switching device Q1 is off, the second terminal of the first switching device is grounded to GND; when the first switching device Q1 is on, it prevents the signal from directly entering GND. In one example, the resistance value of the first resistor R1 can be 1K ohms.

[0039] In one embodiment, see Figure 4The second switching circuit 133 includes a second clock generator clk2, a second switching device Q2, and a second resistor R2. The first terminal of the second switching device Q2 is electrically connected to the first terminal of the second resistor R2 and the second signal terminal T2, respectively. The second terminal of the second switching device Q2 is electrically connected to the second clock generator clk2, and the control terminal of the second switching device Q2 is electrically connected to the logic circuit 132. The second terminal of the second resistor R2 is electrically connected to the power supply VCC. The power supply VCC can be the power supply of the communication bus, such as 1.8V for the I2C communication bus. The second switching device Q2 is used to be in a conducting state when it receives the enable control signal EN, so as to transmit the clock signal of the second clock generator clk2 to the second signal line S2. Alternatively, the second switching circuit 133 in the anti-deadlock circuit 13 transmits reset information to the second signal line S2 on behalf of the master device 11. Upon receiving the reset signal, the slave device 12 performs a reset operation, thus resolving the deadlock state between the master device 11 and the slave device 12.

[0040] In one embodiment, the second switching device Q2 can be implemented using a PMOS transistor. In this scenario, the enable control signal EN can be low, and the PMOS transistor switches to the on state. If the second switching device Q2 is implemented using an NMOS transistor, in this scenario, the enable control signal EN is high, and the NMOS transistor switches to the on state. It should be noted that the device type of the second switching device Q2 can be associated with the enable control signal EN output by the logic circuit. When the device selection within the logic circuit 132 is known, the control level of the second switching device Q2 can be adjusted accordingly, and the corresponding scheme falls within the protection scope of this disclosure.

[0041] In one embodiment, the second resistor R2 is used as a supervising resistor to prevent the second switching device Q2 from being directly connected to the power supply VCC, thereby protecting the second switching device Q2. In one example, the resistance value of the second resistor R2 can be 1K ohms.

[0042] In one embodiment, the first switching circuit 131 and the second switching circuit 133 are implemented using the same clock generator, that is, the first clock generator clk1 and the second clock generator clk2 are one clock generator, which can ensure that the clock signals of the first switching circuit 131 and the second switching circuit 133 are synchronized, and can reduce the number of clock generators, which is beneficial to reducing the size of the anti-deadlock circuit.

[0043] In one embodiment, see Figure 5The logic circuit 132 includes a first counter 1321 and a flip-flop 1322. The first counter 1321 is electrically connected to both the first switching circuit 131 and the flip-flop 1322. The flip-flop 1322 is electrically connected to the second switching circuit 133. The first counter 1321 outputs a pulse signal to the flip-flop 1322 upon receiving a clock signal. The flip-flop 1322 outputs an enable control signal EN to the second switching circuit 133 upon receiving the pulse signal. The enable control signal EN is configured to control the second switching device Q2 to switch to the on state.

[0044] Thus, in this embodiment, the logic circuit 132 can convert the deadlock signals of the master device 11 and the slave device 12 into an enable control signal EN, and then send it to the second switching device Q2, achieving the effect of resetting the slave device 12, so that after the slave device 12 is reset, it no longer continuously outputs the first preset level. It is understood that, in order to ensure reliable reset, the clock signals output by the first clock generator clk1 and the second clock generator clk2 can have different widths than the clock signal of the communication bus, thereby ensuring that the slave device 12 accurately identifies the clock signal of the second clock generator clk2 as the reset signal.

[0045] In one embodiment, see further. Figure 5 The first counter 1321 includes a clock terminal CK, a reset terminal R, and an output terminal Out; the flip-flop 1322 includes a clock terminal CK, an input terminal In, and an output terminal Out. The clock terminal CK of the first counter 1321 is electrically connected to the first switching circuit 131, the reset terminal R of the first counter 1321 is electrically connected to the first signal line S1, and the output terminal Out of the first counter 1321 is electrically connected to the clock terminal CK of the flip-flop 1322. The input terminal In of the flip-flop 1322 is electrically connected to the power supply VCC, and the output terminal Out of the flip-flop 1322 is electrically connected to the second switching circuit 133. Thus, when the first signal line S1 continuously transmits a first preset level, the first counter 1321 can output to the flip-flop 1322 upon receiving the clock signal from the first clock generator clk1; 1322 can output an enable control signal EN through the output terminal Out. After the slave device 12 is reset, it will output a second preset level, causing the first switching circuit to switch to the off state, and the first counter 1321 to be in the reset state, and finally the flip-flop no longer outputs the enable control signal.

[0046] In one embodiment, to ensure reliable reset of the trigger 1322, see [reference needed]. Figure 6The second resistor R2 can be electrically connected to the reset terminal of the flip-flop 1322. The second switching circuit 133 resets the flip-flop 1322 simultaneously with outputting a reset signal to the second signal line S2. Thus, in this embodiment, the flip-flop is reset when a reset signal is output to the second signal line S2, ensuring that the flip-flop no longer outputs the enable control signal EN, thereby achieving the effect of turning off the second switching circuit 133.

[0047] In one embodiment, see Figure 7 The logic circuit 132 further includes a second counter 1323; the second counter 1323 is electrically connected to the second switching circuit 133 and the flip-flop 1322 respectively; the second counter 1323 is used to output a reset signal to the flip-flop 1322 when a preset number of pulse signals are detected on the second signal line S2. In one example, the preset number can be 9 or 16, and can be set according to the specific scenario. In one example, the second counter 1323 includes a clock terminal CK and an output terminal Out. The clock terminal CK of the second counter 1323 is electrically connected to the first end of the second resistor R2, and the output terminal Out of the second counter 1323 is electrically connected to the reset terminal R of the flip-flop 1322. In this embodiment, the second counter 1323 can count the number of pulse signals output by the second switching circuit 133 to the second signal line S2; after the second switching circuit 133 outputs a preset number of pulse signals to the first signal line S1, a reset signal is generated for the flip-flop 1322, so that the flip-flop 1322 no longer outputs an enable control signal, thereby causing the second switching circuit 133 to no longer output pulse signals to the first signal line S1, thus achieving reliable reset.

[0048] based on Figures 1-7 The example anti-lockdown circuit, combined with Figure 7 The first switching device Q1 is implemented using a PMOS transistor, the second switching device Q2 is implemented using an NMOS transistor, the flip-flop 1322 is implemented using a D flip-flop with reset function, the first clock generator clk1 and the second clock generator clk2 are implemented using a 400KHz clock generator, and the communication bus is an I2C communication bus.

[0049] The clock generator is connected to the source of the PMOS transistor and the source of the NMOS transistor, respectively.

[0050] The gate of the second switching device Q2 is electrically connected to the output of the flip-flop, and the drain of the second switching device Q2 is electrically connected to the clock terminal CK of the second counter 1323. The output of the second counter 1323 is electrically connected to the reset terminal R of the flip-flop. The drain of the second switching device Q2 is also electrically connected to the first terminal of the second resistor R2, the second terminal of the second resistor R2 is electrically connected to the power supply VCC of the I2C communication bus, and the drain of the second switching device Q2 is electrically connected to the second signal line S2.

[0051] The gate of the first switching device Q1 is electrically connected to the first signal line S1 (i.e., the SDA line of the I2C communication bus), and the first signal line S1 is electrically connected to the reset terminal R of the first counter 1321; the drain of the first switching device Q1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded; the drain of the first switching device Q1 is electrically connected to the clock generator.

[0052] The output of the first counter 1321 is electrically connected to the clock terminal CK of the flip-flop, and the input terminal IN of the flip-flop is electrically connected to the power supply VCC.

[0053] In this example, the working principle of the anti-deadlock circuit includes: In one scenario, the first signal line SDA transmits a high level, the first switching circuit is open, the first counter 1321 is reset after receiving the high level, that is, the first counter 1321 does not work, the D flip-flop does not work, at this time there is no enable control signal between the D flip-flop and the second switching device Q2, or in other words the D flip-flop outputs a low level; the second switching device Q2 is in the open state, it has no pulse signal output, and does not affect the second signal line SCL.

[0054] In one scenario, communication occurs on the I2C communication bus, and the first signal line S1 transmits a high or low level. When the first signal line S1 transmits a high level (i.e., the second preset level), the first counter 1321 is reset and cannot trigger the aforementioned flip-flop, meaning the flip-flop outputs a low-level signal; the second switching device Q2 is in the off state, it has no pulse signal output, and it does not affect the second signal line SCL.

[0055] In one scenario, a deadlock occurs on the I2C communication bus. The first signal line SCL continuously transmits a low level, and the first switching device Q1 is in the ON state. At this time, the 400kHz clock signal output by the clock generator is transmitted to the clock input CK of the first counter 1321 through the first switching device Q1. The first counter 1321 outputs a high level to the clock input CK of the D flip-flop after counting for 1ms. The clock input CK of the D flip-flop detects the rising edge, is triggered, and outputs the enable control signal EN (high level). Upon receiving the high level, the second switching device Q2 is in the ON state, and the 400kHz clock signal is output to the second signal line S2. After the second counter 1323 detects 16 high-low level transitions on the second signal line S2, it outputs an inverted level to the reset input of the flip-flop, i.e., the flip-flop is reset and outputs a low level. At this time, the second switching device Q2 is in the OFF state, and the clock signal transmission to the first signal line SCL stops. The anti-deadlock circuit terminates its operation after outputting 16 clock pulses.

[0056] For the I2C communication bus, since the second signal line S2 transmits 16 clock pulses during the deadlock, the slave device 12 can understand it as a reset signal sent by the master device 11 and perform a reset operation, thereby releasing the first signal line S1 and achieving the effect of releasing the deadlock state.

[0057] Thus, the anti-deadlock circuit provided in this embodiment can detect whether a deadlock has occurred between the master device and the slave device by detecting the first signal line and the second signal line; and resolve the deadlock problem in the event of a deadlock by monitoring the deadlock situation through a clock counting circuit and using a trigger to latch the state, and cooperating with a counter to realize the overall control logic, thereby simplifying the circuit.

[0058] The anti-lockdown circuit in this embodiment can be configured independently or integrated into the master and / or slave devices of the communication bus, thus expanding its application scope. Compared to providing separate control signals to the master or slave devices, the aforementioned anti-lockdown circuit does not require additional external control signals or modifications to the master or slave devices, reducing implementation difficulty. Furthermore, the aforementioned anti-lockdown circuit can be implemented using conventional components, reducing production costs.

[0059] This disclosure also provides a communication bus, including, as in the following embodiments: Figures 1-7 The aforementioned anti-deadlock circuit includes a first port, a second port, a first signal line, and a second signal line. The first port is used for electrical connection with the master device, and the second port is used for electrical connection with the slave device. A first signal line and a second signal line are provided between the first port and the second port. The first signal terminal of the anti-deadlock circuit is electrically connected to the first signal line, and the second signal terminal of the anti-deadlock circuit is electrically connected to the second signal line. In this embodiment, the anti-deadlock circuit can release the deadlock state between the master device and the slave device, thereby ensuring reliable data transmission on the communication bus.

[0060] This disclosure also provides a chip, including as follows: Figures 1-7 The aforementioned anti-lockdown circuit.

[0061] This disclosure also provides an electronic device, referring to... Figure 8 The electronic device 800 may include one or more of the following components: processing component 802, memory 804, power supply component 806, multimedia component 808, audio component 810, input / output (I / O) interface 812, sensor component 814, communication component 816, and image acquisition component 818.

[0062] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute computer programs. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0063] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of such data include computer programs for any application or method operating on electronic device 800, contact data, phone book data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0064] Power supply assembly 806 provides power to various components of electronic device 800. Power supply assembly 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800. Power supply assembly 806 may include a power chip, with a controller communicating with the power chip to control the power chip to turn a first switching device on or off, allowing the battery to supply power to or from the circuit board circuitry.

[0065] Multimedia component 808 includes a screen that provides an output interface between electronic device 800 and target object.

[0066] In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input information from a target object. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation.

[0067] Audio component 810 is configured to output and / or input audio file information. For example, audio component 810 includes a microphone (MIC) configured to receive external audio file information when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio file information may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio file information.

[0068] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc.

[0069] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components (e.g., the display screen and keypad of electronic device 800), changes in position of electronic device 800 or a component, the presence or absence of a target object in contact with electronic device 800, the orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. In this example, sensor assembly 814 may include magnetic sensors, gyroscopes, and magnetic field sensors, and may also include inertial sensors, image sensors, etc., wherein the magnetic field sensor includes at least one of the following: a Hall sensor, a thin-film magnetoresistive sensor, and a magnetic fluid accelerometer.

[0070] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 2G, 3G, 4G, 5G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast information or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies. In one exemplary embodiment, communication component 816 includes the aforementioned communication bus, which includes... Figures 1-7 The example demonstrates a deadlock prevention circuit.

[0071] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital information processors (DSPs), digital information processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, or other electronic components.

[0072] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This disclosure is intended to cover any variations, uses, or adaptations that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0073] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A deadlock prevention circuit, characterized in that, Applicable to a communication bus, the anti-deadlock circuit includes: a first signal terminal and a second signal terminal; the first signal terminal is electrically connected to a first signal line of the communication bus, and the second signal terminal is electrically connected to a second signal line of the communication bus; The anti-deadlock circuit is used to output a reset signal to the second signal line when the first signal line continuously transmits a first preset level; the reset signal is configured to control the slave device of the communication bus to stop continuously outputting the first preset level to the first signal line.

2. The anti-lockdown circuit according to claim 1, characterized in that, The anti-lock circuit includes: a first switching circuit, a second switching circuit, and a logic circuit; the first switching circuit is electrically connected to the first signal terminal and the logic circuit respectively; the second switching circuit is electrically connected to the second signal terminal and the logic circuit respectively; The first switching circuit is used to output a clock signal to the logic circuit while the first signal line continuously transmits a first preset level; The logic circuit is used to output an enable control signal to the second switching circuit when a preset number of clock signals are received. The second switching circuit is used to output a reset signal to the second signal line when the enable control signal is received.

3. The anti-lockdown circuit according to claim 2, characterized in that, The first switching circuit includes a first clock generator, a first switching device, and a first resistor; the first terminal of the first switching device is electrically connected to the first clock generator, the second terminal of the first switching device is electrically connected to the logic circuit and the first resistor respectively, the control terminal of the first switching device is electrically connected to the first signal terminal; the second terminal of the first resistor is grounded. The first switching device is used to be in a conducting state when the first signal terminal is at a first preset level.

4. The anti-lockdown circuit according to claim 2, characterized in that, The second switching circuit includes a second clock generator, a second switching device, and a second resistor; the first terminal of the second switching device is electrically connected to the first terminal of the second resistor and the second signal terminal, respectively; the second terminal of the second switching device is electrically connected to the second clock generator; the control terminal of the second switching device is electrically connected to the logic circuit; and the second terminal of the second resistor is electrically connected to the power supply. The second switching device is used to be in the on state when an enable control signal is received.

5. The anti-lockdown circuit according to claim 3 or 4, characterized in that, The first switching device in the first switching circuit is implemented using a PMOS transistor, and / or the second switching device in the second switching circuit is implemented using an NMOS transistor.

6. The anti-lockdown circuit according to any one of claims 2 to 4, characterized in that, The first switching circuit and the second switching circuit are implemented using the same clock generator.

7. The anti-lockdown circuit according to claim 2, characterized in that, The logic circuit includes a first counter and a flip-flop; the first counter is electrically connected to the first switching circuit and the flip-flop respectively; the flip-flop is electrically connected to the second switching circuit. The first counter is used to output a pulse signal to the trigger when a clock signal is received; The trigger is used to output an enable control signal to the second switching circuit when a pulse signal is received. The enable control signal is configured to control the second switching device in the second switching circuit to switch to the on state.

8. The anti-lockdown circuit according to claim 7, characterized in that, The first counter includes a clock terminal, a reset terminal, and an output terminal; the flip-flop includes a clock terminal, an input terminal, and an output terminal. The clock terminal of the first counter is electrically connected to the first switching circuit, the reset terminal of the first counter is electrically connected to the first signal line, and the output terminal of the first counter is electrically connected to the clock terminal of the flip-flop. The input terminal of the trigger is electrically connected to the power supply, and the output terminal of the trigger is electrically connected to the second switching circuit.

9. The anti-lockdown circuit according to claim 7 or 8, characterized in that, The logic circuit further includes a second counter; the second counter is electrically connected to the second switching circuit and the flip-flop, respectively. The second counter is used to output a reset signal to the trigger when a preset number of pulse signals are detected on the second signal line.

10. The anti-lockdown circuit according to claim 9, characterized in that, The second counter includes a clock terminal and an output terminal; The clock terminal of the second counter is electrically connected to the second switching circuit, and the output terminal of the second counter is electrically connected to the reset terminal of the flip-flop.

11. A communication bus, characterized in that, include: The first port, the second port, the first signal line, the second signal line, and the anti-deadlock circuit as described in any one of claims 1 to 10; The first port is used for electrical connection with the master device, and the second port is used for electrical connection with the slave device; a first signal line and a second signal line are provided between the first port and the second port; the first signal terminal of the anti-lock-up circuit is electrically connected to the first signal line, and the second signal terminal of the anti-lock-up circuit is electrically connected to the second signal line.

12. A chip, characterized in that, Includes the anti-lockdown circuit as described in any one of claims 1 to 10.

13. An electronic device, characterized in that, This includes the communication bus as described in claim 11, or the chip as described in claim 12.

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