PCIe to rapidio communication card

Abstract

The application provides a PCIe-to-RapidIO communication card, which comprises: N QSFP+ interfaces, each of which contains 4 channels and is used for connecting an external RapidIO device, N being an integer greater than or equal to 1; a PCIe interface used for connecting an external host; and an FPGA used for connecting the PCIe interface and the one or more QSFP+ interfaces and realizing protocol conversion between PCIe and RapidIO; wherein the FPGA configures the RapidIO link width to be 1 channel, 2 channels or 4 channels by calling a RapidIO core, so that any one of the N QSFP+ interfaces supports 4, 2 or 1 independent RapidIO logical links.

Description

Technical Field

[0001] This application relates to the field of communication technology, and more specifically, to a PCIe to RapidIO communication card. Background Technology

[0002] RapidIO (Rapid Input / Output) is a low-latency, high-reliability packet-switched interconnect technology. Its communication interfaces typically include multiple channel configurations such as 1X, 2X, and 4X, with communication rates covering multiple levels including 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, and 6.25Gbps. It is specifically designed for embedded systems, real-time communication, and multi-processor collaborative scenarios, and is widely used in communication equipment, industrial control, radar signal processing, and other fields. RapidIO features deterministic transmission characteristics and system-level fault tolerance, making it suitable for applications with high real-time and reliability requirements.

[0003] PCIe (Peripheral Component Interconnect Express) is a high-performance serial computer expansion bus standard widely used to connect motherboards with peripherals such as graphics cards, solid-state drives, and network cards. It is the mainstream expansion interface for modern general-purpose computer systems.

[0004] In embedded real-time systems such as flight control, radar signal processing, and electronic warfare, processing units such as DSPs and FPGAs often achieve high-speed, low-latency data exchange through RapidIO interfaces. However, general-purpose computers are typically only equipped with PCIe interfaces and lack RapidIO communication capabilities, making it difficult for them to directly interact with RapidIO devices in embedded systems. This hinders the ability of general-purpose computers to perform simulation communication, data acquisition, and status monitoring of embedded systems. Therefore, there is an urgent need to provide an efficient and stable interface conversion device to achieve the conversion and interconnection between PCIe and RapidIO. Utility Model Content

[0005] The purpose of this application is to provide a PCIe-to-RapidIO communication card that, through the internal calling of the RapidIO protocol core within the FPGA, flexibly configures the four physical channels of a QSFP+ interface into multiple independent RapidIO logical links. Specifically, a QSFP+ interface can be configured as: four independent 1X links, two independent 2X links, or one 4X link, depending on actual needs. Furthermore, by supporting N QSFP+ interfaces, the communication card achieves scalability.

[0006] The embodiments of this application are implemented as follows: This application provides a PCIe-to-RapidIO communication card, comprising: N QSFP+ interfaces, each QSFP+ interface containing 4 channels for connecting to external RapidIO devices, where N is an integer greater than or equal to 1; a PCIe interface for connecting to an external host; and an FPGA for connecting the PCIe interface and the one or more QSFP+ interfaces, and implementing protocol conversion between PCIe and RapidIO; wherein, the FPGA configures the RapidIO link width to 1 channel, 2 channels, or 4 channels by calling the RapidIO core, so that any one of the N QSFP+ interfaces supports 4, 2, or 1 independent RapidIO logical links.

[0007] In some embodiments of this application, the PCIe interface includes 8 channels, and the FPGA can also configure the PCIe link width to be 1 channel, 2 channels, 4 channels or 8 channels by calling the PCIe IP core.

[0008] In some embodiments of this application, the PCIe interface is a PCIe 3.0 interface.

[0009] In some embodiments of this application, the communication card further includes: an SMA-OUT interface, which is connected to the FPGA via a BUFF circuit, for outputting a synchronization trigger signal or a B code signal to achieve triggering and time synchronization with other devices.

[0010] In some embodiments of this application, the FPGA also configures the transmission rate of the RapidIO link by calling the DRP interface of the RapidIO core, thereby achieving rate switching.

[0011] In some embodiments of this application, the communication card further includes: a programmable phase-locked loop (PLL) for outputting a clock frequency; the FPGA receives configuration instructions from the external host through the PCIe interface, and sets the frequency of the programmable PLL according to the configuration instructions to achieve clock frequency switching.

[0012] In some embodiments of this application, any one of the one or more QSFP+ interfaces supports hot-plugging.

[0013] The PCIe to RapidIO communication card provided in this application embodiment has at least the following beneficial effects, including but not limited to: This application uses FPGA to flexibly divide the four physical channels of each QSFP+ interface into one, two, or four independent RapidIO logical links, and supports scalable configuration of N interfaces. Combined with hot-swappable capability, it significantly improves the interface flexibility and system adaptability for connecting different numbers and speeds of RapidIO devices during testing.

[0014] Meanwhile, by supporting the PCIe 3.0X8 high-bandwidth interface, multi-rate adaptive configuration, remote clock frequency switching, and synchronous triggering and time synchronization functions, it achieves high-speed data transmission, multi-platform compatibility, remote dynamic debugging, and multi-device collaborative control, thereby improving the versatility, maintainability, and testing efficiency of the communication card in complex testing scenarios. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram illustrating communication between a RapidIO device and a general-purpose computer. Figure 2 An exemplary structural diagram of a PCIe to RapidIO communication card provided in this application embodiment; Figure 3 This is an exemplary structural diagram of the power supply circuit in a PCIe to RapidIO communication card provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] In this application, the terms "first" and "second" are used to distinguish identical or similar items that have essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0021] It should be noted that, in this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0022] Furthermore, "at least one" refers to one or more, while "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0023] In the description of the embodiments of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] To facilitate understanding of the embodiments of this application, the relevant technologies of this application are described below.

[0025] Figure 1 This is a schematic diagram illustrating communication between a RapidIO device and a general-purpose computer. (Example:) Figure 1As shown, RapidIO communication typically uses the built-in RapidIO interface of an embedded processor or implements a RapidIO interface using an FPGA to complete data exchange between RapidIO nodes. When performing independent testing and functional verification on each node, or when it is necessary to check the RapidIO operating status of a device, a specific embedded processor is usually designated as the master device, running a specially written test program to access and test other devices. Test results are output via serial port or transmitted to a general-purpose computer via Ethernet, where the computer then displays and operates the interface.

[0026] In this model, two sets of software programs need to be developed: one is test code running on the embedded processor, and the other is a human-computer interaction program and communication control logic with the embedded end running on a general-purpose computer. Since embedded processors may run different types of embedded operating systems, their development tools, operating mechanisms, and system interfaces differ, while general-purpose computers typically run Windows or general-purpose Linux systems, resulting in significant differences in their software environments. Therefore, developers need to master dual development techniques for both embedded and general-purpose computer platforms, or have different personnel collaborate on the task, increasing the skill requirements for personnel. Furthermore, test data communication relies on serial ports or Ethernet, which have limited bandwidth and low transmission efficiency. Adjustments to the test content often require simultaneous modifications to the software on both the embedded and general-purpose computer sides, resulting in a large maintenance workload and insufficient flexibility.

[0027] Therefore, some solutions propose using PCIe to RapidIO communication cards. PCIe to RapidIO communication cards establish a high-speed data path between general-purpose computers and embedded real-time systems, forming the foundation for general-purpose computers to perform simulation communication, data acquisition, and status monitoring functions for embedded real-time systems.

[0028] Compared to the original, complex testing environment that required both computer equipment and embedded devices, and the development of two sets of programs to achieve RapidIO business communication, the PCIe to RapidIO card can be directly installed in a general-purpose computer. Developers only need to call the functions already encapsulated on the communication card to develop the software for the general-purpose computer, thus reducing the difficulty of use.

[0029] Currently, PCIe to RapidIO communication cards can connect to external RapidIO devices via QSFP+ interfaces. Each QSFP+ interface corresponds to one RapidIO logical link, which is configured with a fixed width (such as 1X, 2X, or 4X) during initialization and remains unchanged throughout the communication process. In this architecture, each QSFP+ interface can only establish one logical link, corresponding to one external RapidIO device; it cannot be split into multiple independent links to connect to different devices.

[0030] When multiple RapidIO devices need to be connected, existing communication cards either increase the number of QSFP+ interfaces or rely on external RapidIO switching chips for routing. This increases hardware cost and size, making it unsuitable for test platforms with limited interface resources. Furthermore, the link configuration is fixed, making it impossible to dynamically adjust the number of links and bandwidth according to test requirements, resulting in poor flexibility.

[0031] This application provides a PCIe-to-RapidIO communication card, which uses an FPGA to call a RapidIO protocol core to flexibly configure the four physical channels of a QSFP+ interface into multiple independent RapidIO logical links. Specifically, a QSFP+ interface can be configured as four independent 1X links, two independent 2X links, or one 4X link, depending on actual needs. Furthermore, this application provides scalability by supporting N QSFP+ interfaces.

[0032] The embodiments of this application are described below.

[0033] In this embodiment, a PCIe-to-RapidIO communication card includes: N QSFP+ interfaces, each QSFP+ interface containing 4 channels for connecting to external RapidIO devices, where N is an integer greater than or equal to 1; a PCIe interface for connecting to an external host; and an FPGA for connecting the PCIe interface and the one or more QSFP+ interfaces, and implementing protocol conversion between PCIe and RapidIO. The FPGA, by calling a RapidIO core, configures the RapidIO link width to 1 channel, 2 channels, or 4 channels, enabling any one of the N QSFP+ interfaces to support 4, 2, or 1 independent RapidIO logical links.

[0034] This application embodiment utilizes the RapidIO protocol core integrated within the FPGA to divide the four physical channels of a QSFP+ interface into multiple independent logical links. For example, a single QSFP+ interface can be configured as four independent 1X links, each capable of connecting to one external RapidIO device, enabling a single physical interface to connect to multiple devices. This division is achieved through the link layer control logic of the RapidIO protocol core, leveraging the programmability of the FPGA to complete channel mapping and address isolation. The transmission rate of the RapidIO link can be configured to 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, or 6.25Gbps via the DRP interface of the protocol core, adapting to RapidIO devices with different speeds. Simultaneously, the communication card supports N QSFP+ interfaces, where N is an integer greater than or equal to 1, allowing for flexible configuration of the number of interfaces according to actual testing needs. This structure is suitable for testing scenarios requiring the connection of multiple RapidIO devices, balancing flexibility and scalability.

[0035] In this embodiment of the application, the PCIe interface includes 8 channels, and the FPGA can also configure the PCIe link width to be 1 channel, 2 channels, 4 channels or 8 channels by calling the PCIe IP core.

[0036] The PCIe interface in this embodiment supports x1, x2, x4, and x8 link widths, and can automatically negotiate the optimal link mode based on the motherboard slot capabilities when connected to a host. The FPGA implements the PCIe interface by calling standard PCIe IP cores, supporting speeds of 2.5Gbps, 5Gbps, and 8Gbps. This design ensures the communication card functions correctly on different host platforms, enhancing device compatibility and making it suitable for various deployment environments.

[0037] In this embodiment of the application, the PCIe interface is a PCIe 3.0 interface.

[0038] This application's embodiment adopts the PCIe 3.0 standard, with a single-channel transmission rate of 8Gbps. In x8 mode, the unidirectional bandwidth can reach approximately 8 GB / s, far exceeding the speeds of Gigabit Ethernet (1.25 GB / s) or serial communication. This high-bandwidth interface allows large amounts of data in the RapidIO network to be quickly uploaded to the host, avoiding the latency issues caused by traditional test systems relying on low-speed interfaces for data return. This design enables general-purpose computers to directly participate in real-time data acquisition and monitoring, improving the response speed and practicality of the test system.

[0039] In this embodiment of the application, the communication card further includes: an SMA-OUT interface, which is connected to the FPGA via a BUFF circuit and is used to output a synchronization trigger signal or a B code signal to achieve triggering and time synchronization with other devices.

[0040] The SMA-OUT interface is directly controlled by the FPGA and can output synchronous trigger signals or B-code signals (IRIG-B code) through a BUFF circuit, with TTL support for the output level. When the communication card acts as the master device, it can send time synchronization signals or trigger commands to external devices to initiate multi-device collaborative acquisition. This function enables the communication card not only to have data communication capabilities but also to participate in system-level timing control, making it suitable for testing environments with strict time synchronization requirements, such as radar, avionics, and power systems.

[0041] In this embodiment, the FPGA also configures the transmission rate of the RapidIO link by calling the DRP interface of the RapidIO core, thereby achieving rate switching.

[0042] The RapidIO core provides a Dynamic Reconfiguration Port (DRP), through which the FPGA can modify the link's transmission rate at runtime, supporting rates such as 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, and 6.25Gbps. This operation does not require reloading the FPGA logic or restarting the device; the host can complete the configuration via PCIe commands. This design supports compatibility testing with RapidIO devices of different rates, improving the communication card's adaptability in verification across multiple device models.

[0043] In this embodiment of the application, the communication card further includes: a programmable phase-locked loop (PLL) for outputting a clock frequency; the FPGA receives configuration instructions from the external host through the PCIe interface, and sets the frequency of the programmable PLL according to the configuration instructions to achieve clock frequency switching.

[0044] A programmable phase-locked loop (PLL) provides the operating clock for the RapidIO interface, and its output frequency is controlled by the FPGA via a bus. This PLL can output four different clock frequencies to meet the clock requirements of different modules on the communication card. The host computer can remotely adjust the clock frequency via a PCIe interface to adapt to the speed requirements of different RapidIO devices. This design avoids the need to replace the crystal oscillator or power cycle the device, supports remote configuration and automated testing, and improves debugging efficiency.

[0045] In the embodiments of this application, any one of the one or more QSFP+ interfaces supports hot-plugging.

[0046] The power and signal line design of the QSFP+ interface includes power sequence control, ESD protection, and signal pre-emphasis circuitry, supporting hot-swapping. During system operation, QSFP+ modules can be safely inserted or removed without interrupting the host or FPGA. The QSFP+ interface can be equipped with electrical or optical modules to achieve RapidIO electrical or optical interface communication. This feature allows the number of QSFP+ interfaces used to be dynamically increased or decreased according to actual needs, such as temporarily connecting new devices during commissioning or removing faulty modules during troubleshooting. This design improves the flexibility of interface configuration during testing and enhances the adaptability of the communication card in complex testing environments.

[0047] Figure 2 This is an exemplary structural diagram of a PCIe-to-RapidIO communication card provided in an embodiment of this application. N=2, meaning there are two QSFP+ interfaces. It is understood that the number of QSFP+ interfaces can be adjusted according to actual needs. Furthermore, the components, voltages, and other parameters shown in the diagram can also be changed according to specific application scenarios.

[0048] like Figure 2 As shown, exemplarily, a PCIe to RapidIO communication card according to an embodiment of this application may include the following components: (1) FPGA: The core of the PCIe-to-RapidIO protocol is to implement PCIe interface communication, receive data from the host, and then frame and send the received host data according to the RapidIO protocol requirements. When receiving data from the RapidIO interface, it parses the packet type, reassembles the packet, and transmits it to the computer via PCIe. The RapidIO interface is implemented by calling the RapidIO core as needed. Its width and speed can be configured as required. The width can be configured to 1X, 2X, and 4X, and the speed can be configured to 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps, and 6.25Gbps through the RapidIO core's DRP (Dynamic Reconfiguration Port) interface.

[0049] (2) PCIe: The PCIe 3.0 interface is implemented using a PCIe IP core within the FPGA. The communication card communicates with the computer via a PCIe connector. The PCIe speed and width are configurable as needed, with widths available in 1X, 2X, 4X, and 8X configurations. The speeds are configurable in 2.5Gbps, 5Gbps, and 8Gbps configurations.

[0050] (3) Crystal oscillator: Provides a reference clock for the RapidIO high-speed transceiver interface, which can be either 125MHz or 156.25MHz.

[0051] (4) BUFF: This is used for interface protection between external interfaces and FPGA I / O, and the protection signals include the JTAG interface, LED driver interface, and external connector I / O interface.

[0052] (5) QSFP+: The RapidIO external interface connector can be equipped with an electrical port module to achieve RapidIO electrical interface communication, or with an optical module to achieve RapidIO interface optical communication.

[0053] (6) SMA-IN: It can receive external signals, which can be synchronous trigger signals or B-code signals, and the received signal level supports TTL level.

[0054] (7) SMA-OUT: When the communication card acts as the master device, it can output a synchronization trigger signal or a time synchronization signal such as a B code for time synchronization between devices.

[0055] (8) LED: Two LEDs are onboard to indicate the working status of the communication card.

[0056] (9) JTAG connector: Used to load FPGA firmware.

[0057] (10) Connector: The internal I / O connector of the communication card functions the same as the SMA interface, but allows signal wiring to be routed inside the chassis.

[0058] (11) Programmable phase-locked loop: Through FPGA configuration, four different clock frequencies can be output to meet the different clock frequency requirements of the communication card.

[0059] (12) Temperature crystal oscillator: It provides a highly stable reference clock for programmable phase-locked loops, improving the accuracy and stability of the communication card's operating clock.

[0060] (13) Crystal oscillator: Provides the initial operating clock for the FPGA, typically a low-frequency clock, with a typical frequency of 25MHz.

[0061] (14) DDR4 memory 1: 32-bit or 64-bit DDR4 memory, 1-2GB in capacity, to provide cache for the first RapidIO channel.

[0062] (15) DDR4 memory 2: 32-bit or 64-bit DDR4 memory, 1-2GB in capacity, to provide cache for the second RapidIO.

[0063] (16) NOR FLASH: The FPGA firmware can be loaded via JTAG or via software through the PCIe interface.

[0064] (17) EEPROM: Store user information and configuration information, such as hardware version number, communication card serial number, software version number, and default configuration of programmable phase-locked loop.

[0065] (18) Power supply circuit: The power input from the host via the PCIe interface is converted into the power required by each chip on the communication card. The converted power supplies include the FPGA core power supply, auxiliary power supply, IO power supply, GTX core power supply, GTX auxiliary power supply, GTX transceiver power supply, QSFP interface operating power supply, BUFF power supply, NOR FLASH, EEPROM, DDR4 operating power supply, programmable phase-locked loop operating power supply, and crystal oscillator operating power supply.

[0066] Figure 3 This is an exemplary structural diagram of the power supply circuit in a PCIe to RapidIO communication card provided in an embodiment of this application. It is understood that the components, voltages, and other parameters shown in the diagram can be changed according to specific application scenarios.

[0067] This power supply circuit can consist of two DC-DC converters and multiple LDOs, capable of converting the input 3.3V and 12V DC voltages into different voltage levels to meet the needs of various chips and modules in communication.

[0068] First, a DC-DC converter transforms the input 3.3V and 12V voltages into a maximum current of 18A and outputs 0.85V to power the FPGA's VCCINT, with a maximum current of 14A. Additionally, the converter outputs 1.5V, which is converted to 0.9V and 1.2V respectively via two LDOs to power different sections of the GTY transceiver. The 0.9V voltage provides a maximum current of 5A, while the 1.2V voltage provides a maximum current of 4.5A.

[0069] Another DC-DC converter also accepts 3.3V and 12V input voltages, but outputs different voltage levels. It initially outputs a maximum current of 8A to power the FPGA's DDR at 1.2V. Then, the voltage is converted to 3.3V via an LDO to power the I / O interface and peripheral circuitry, with a maximum current of 0.5A. Additionally, this converter also outputs 4V, which is converted to 3.3V via two LDOs to power the GTY peripheral circuitry and QSFP+ interface, with a maximum current of 3A.

[0070] Finally, the DC-DC converter also outputs a 2.5V voltage, which is converted to 1.8V via an LDO to power the FPGA's auxiliary power supply and the GTY transceiver, with a maximum current of 1A. Simultaneously, this 2.5V voltage also directly powers the DDR memory, with a maximum current of 0.1A.

[0071] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A PCIe to RapidIO communication card, characterized in that, include: There are N QSFP+ interfaces, each containing 4 channels, used to connect to external RapidIO devices, where N is an integer greater than or equal to 1; PCIe interface, used for connecting to an external host; An FPGA is used to connect the PCIe interface and one or more QSFP+ interfaces, and to implement protocol conversion between PCIe and RapidIO. The FPGA configures the RapidIO link width to 1, 2, or 4 channels by calling the RapidIO core, so that any one of the N QSFP+ interfaces supports 4, 2, or 1 independent RapidIO logical links.

2. The communication card as described in claim 1, characterized in that, The PCIe interface contains 8 channels, and the FPGA can also configure the PCIe link width to be 1 channel, 2 channels, 4 channels or 8 channels by calling the PCIe IP core.

3. The communication card as described in claim 1, characterized in that, The PCIe interface is a PCIe 3.0 interface.

4. The communication card as described in claim 1, characterized in that, Also includes: The SMA-OUT interface, connected to the FPGA via a BUFF circuit, is used to output synchronous trigger signals or B-code signals, enabling triggering and time synchronization with other devices.

5. The communication card as described in claim 1, characterized in that, The FPGA also configures the transmission rate of the RapidIO link by calling the DRP interface of the RapidIO core, thereby achieving rate switching.

6. The communication card as described in claim 1, characterized in that, Also includes: Programmable phase-locked loop (PLL) for outputting clock frequency; The FPGA receives configuration commands from the external host through the PCIe interface, and sets the frequency of the programmable phase-locked loop according to the configuration commands to achieve clock frequency switching.

7. The communication card as described in claim 1, characterized in that, Any one of the one or more QSFP+ interfaces supports hot-plugging.

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