Switching circuit of pcie slot

Abstract

This utility model relates to a switching circuit for a PCIe slot, including a signal switching circuit, a signal switching switch, a CPU, a first slot, and a second slot. The signal switching switch includes an uplink signal pin for connecting to an uplink PCIe signal, a first downlink signal pin for connecting to the first slot, a second downlink signal pin for connecting to the second slot, and a control pin for connecting to the signal switching circuit. The signal switching circuit includes a first NMOS transistor, the gate of which is connected to the control signal of the CPU via a first resistor, the source of which is grounded, and the drain of which is connected to the power supply via a first pull-up resistor and to the control pin of the signal switching switch. When the control pin of the signal switching switch is low, the uplink signal pin is selected to the first downlink signal pin; when the control pin of the signal switching switch is high, the uplink signal pin is selected to the second downlink signal pin. The PCIe slot switching circuit of this utility model is less expensive than using a PCIe hub chip for switching.

Description

Technical Field

[0001] This utility model relates to the field of electronic computer technology, and in particular to a switching circuit for a PCIe slot. Background Technology

[0002] In this era of diversified information technology, as computer equipment is widely used in industrial control, enterprise office, user interaction, entertainment and other purposes, the usage scenarios of user groups are becoming increasingly segmented, and users' demand for personalized customization of computer equipment is growing.

[0003] The motherboard is the core of a computer hardware system. User customization of computer equipment is primarily achieved through adding functional modules via the motherboard's expansion interfaces or upgrading core hardware using the motherboard's compatibility features. Motherboard expansion interfaces include PCIe (PCI Express) expansion slots, M.2 Key E (WiFi / Bluetooth module interface), M.2 interfaces, and SATA interfaces.

[0004] PCIe is a core high-speed serial expansion interface standard in current computer architecture, supporting x1 / x4 / x8 / x16 lane widths. It is suitable for connecting motherboards to various expansion devices, such as graphics cards, sound cards, network cards, SSDs, and RAID cards. A computer's CPU (Central Processing Unit) typically integrates a PCIe controller and provides a limited number of PCIe lanes. For example, a typical computer CPU may only provide 16 or 24 PCIe lanes. These lanes need to be allocated to multiple high-priority devices, such as discrete graphics cards (usually occupying x16 lanes) and M.2 NVMe SSD slots (usually occupying x4 lanes). When users need to connect PCIe devices exceeding the number of available CPU lanes, a resource bottleneck is encountered.

[0005] Since PCIe resources in a computer are limited, some computers add PCIe hub chips. These chips expand a single upstream PCIe lane into multiple downstream PCIe lanes, allowing multiple devices to share the bandwidth of the upstream PCIe lane and thus supporting the expansion of more PCIe devices. However, PCIe hub chips are relatively expensive, and they are typically multi-pin, high-density packages requiring numerous signal lines. This increases the number of PCB layers, wiring complexity, and PCB size, driving up motherboard costs and design complexity. Therefore, using PCIe hub chips to expand PCIe resources is costly. Consequently, a lower-cost alternative is urgently needed. Summary of the Invention

[0006] Therefore, the purpose of this utility model is to provide a PCIe slot switching circuit that can switch one PCIe resource to two different PCIe slots to meet different customer needs, and the cost is lower than that of using a PCIe HUB chip for switching.

[0007] To achieve the above objectives, this utility model provides a switching circuit for a PCIe slot, including a signal switching circuit, a signal switching switch, a CPU, a first slot, and a second slot. The signal switching switch includes an uplink signal pin connected to an uplink PCIe signal, a first downlink signal pin connected to the first slot, a second downlink signal pin connected to the second slot, and a control pin connected to the signal switching circuit. The signal switching circuit includes a first NMOS transistor, the gate of which is connected to the control signal of the CPU via a first resistor, the source of which is grounded, and the drain of which is connected to the power supply via a first pull-up resistor and to the control pin of the signal switching switch. When the control pin of the signal switching switch is low, the uplink signal pin is selected to the first downlink signal pin; when the control pin of the signal switching switch is high, the uplink signal pin is selected to the second downlink signal pin.

[0008] The gate of the first NMOS transistor is connected to the CPU via a first resistor and a second resistor.

[0009] The gate of the first NMOS transistor is also grounded via the first capacitor.

[0010] The first NMOS transistor is model LBSS139WT1G.

[0011] The resistance of the first resistor is 1KΩ.

[0012] The first pull-up resistor has a resistance of 10KΩ.

[0013] The signal switching circuit also includes a second NMOS transistor. The gate of the second NMOS transistor is connected to the power supply via a third resistor and a second pull-up resistor, and another connection is made to the device insertion detection pin of the second slot. The source is grounded, and the drain is connected to the power supply via a first pull-up resistor and another connection is made to the control pin of the signal switching switch. The CPU outputs a low-level signal to the signal switching circuit by default.

[0014] The gate of the second NMOS transistor is also grounded via a second capacitor.

[0015] The second NMOS transistor is model LBSS139WT1G.

[0016] The resistance of the third resistor is 1KΩ.

[0017] The second pull-up resistor has a resistance of 10KΩ.

[0018] The beneficial effects of this invention are as follows: This invention provides a PCIe slot switching circuit. A control signal from the CPU passes through a signal switching circuit to a signal switching switch. The signal switching switch then selects one of the two PCIe slots based on the level signal output by the signal switching circuit. This allows for switching one PCIe resource to two different PCIe slots to meet different customer needs. This enables the same motherboard to meet the diverse needs of various customers, thereby saving costs and time in R&D, production, and inventory management. The PCIe slot switching circuit of this invention has a simple structure, does not require a PCIe hub chip, and is inexpensive. Attached Figure Description

[0019] The technical solution and other beneficial effects of this utility model will become apparent from the following detailed description of specific embodiments, in conjunction with the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of a signal switching circuit according to an embodiment of the PCIe slot switching circuit of this utility model.

[0021] Figure 2 for Figure 1 A schematic diagram of the pin connections of the signal switching switch in an embodiment;

[0022] Figure 3 for Figure 1 A schematic diagram of the pin connections of the first slot in an embodiment;

[0023] Figure 4 for Figure 1 A schematic diagram of the pin connections of the second slot in an embodiment;

[0024] Figure 5 for Figure 1 A schematic diagram of the CPU pin connections in an embodiment. Detailed Implementation

[0025] To further illustrate the technical means and effects of this utility model, the following detailed description is provided in conjunction with the preferred embodiments of this utility model and their accompanying drawings.

[0026] See Figure 1-5This utility model provides a switching circuit for a PCIe slot, including a signal switching circuit 1, a signal switching switch 2, a CPU 3, a first slot 4, and a second slot 5. The signal switching switch 2 includes an uplink signal pin connected to the uplink PCIe signal, a first downlink signal pin connected to the first slot 4, a second downlink signal pin connected to the second slot 5, and a control pin connected to the signal switching circuit 1. The signal switching circuit 1 includes a first NMOS transistor Q41. The gate (pin 1 of the first NMOS transistor Q41) of the first NMOS transistor Q41 is connected to the control signal of the CPU 3 via a first resistor R624. The source (pin 2 of the first NMOS transistor Q41) is grounded. The drain (pin 3 of the first NMOS transistor Q41) is connected to power supply P3V3 via a first pull-up resistor R266, and connected to the control pin of the signal switching switch 2. When the control pin of the signal switching switch 2 is low, the uplink signal pin is selected to the first downlink signal pin. When the control pin of the signal switching switch 2 is high, the uplink signal pin is selected to the second downlink signal pin.

[0027] Specifically, in Figure 1-5 In the illustrated embodiment, the first slot 4 is an M.2 Key E slot, and the second slot 5 is a PCIe x1 slot. The gate of the first NMOS transistor Q41 is connected to pin L6 of the CPU 3 to receive control signals from the CPU. Pins 1-2 and 4-5 of the signal switching switch 2 are uplink signal pins; pins 10-11 and 15-16 of the signal switching switch 2 are first downlink signal pins, used to connect to pins 35, 37, 41, and 43 of the first slot 4 to transmit downlink PCIe signals; pins 8-9 and 13-14 of the signal switching switch 2 are second downlink signal pins, used to connect to pins A16, A17, B14, and B15 of the second slot 5 to transmit downlink PCIe signals; pin 6 of the signal switching switch 2 is a control pin, used to receive level signals from the signal switching circuit 1. When the control pin of the signal switching switch 2 is at a low level, the uplink signal pin is selected to the first downlink signal pin, and the downlink PCIE signal is switched to the first slot 4. When the control pin of the signal switching switch 2 is at a high level, the uplink signal pin is selected to the second downlink signal pin, and the downlink PCIE signal is switched to the second slot 5.

[0028] The PCIe slot switching circuit of this invention uses a control signal from the CPU, which passes through a signal switching circuit to a signal switching switch. The signal switching switch then selects one of the two PCIe slots based on the level signal output by the signal switching circuit. This allows for switching one PCIe resource to two different PCIe slots to meet different customer needs, enabling the same motherboard to satisfy various customer requirements and saving costs and time in R&D, production, and inventory management. The PCIe slot switching circuit of this invention has a simple structure, does not require a PCIe hub chip, and is inexpensive.

[0029] Specifically, the gate of the first NMOS transistor Q41 is connected to the CPU3 via a first resistor R624 and a second resistor R105.

[0030] Preferably, the gate of the first NMOS transistor Q41 is also grounded via the first capacitor C531.

[0031] Preferably, the first NMOS transistor Q41 is of model LBSS139WT1G.

[0032] Preferably, the resistance of the first resistor R624 is 1KΩ.

[0033] Preferably, the first pull-up resistor R266 has a resistance of 10KΩ.

[0034] Preferably, the signal switching circuit 1 further includes a second NMOS transistor Q45. The gate of the second NMOS transistor Q45 (pin 1 of the second NMOS transistor Q45) is connected to the power supply P3V3 via a third resistor R962 and a second pull-up resistor R960, and another connection is made to the device insertion detection pin of the second slot 5. The source (pin 2 of the second NMOS transistor Q45) is grounded, and the drain (pin 3 of the second NMOS transistor Q45) is connected to the power supply P3V3 via a first pull-up resistor R266 and another connection is made to the control pin of the signal switching switch 2. The CPU 3 outputs a low-level signal to the signal switching circuit 1 by default.

[0035] Specifically, the device insertion detection pin for the second slot 5 is B17 (PRSNT2#). When no device is inserted into the second slot 5, the gate of the second NMOS transistor Q45 is pulled high due to the second pull-up resistor R960, and the second NMOS transistor Q45 is turned on. When a device is inserted into the second slot 5, the gate of the second NMOS transistor Q45 is pulled low by the device insertion detection pin of the second slot 5, and the second NMOS transistor Q45 is turned off. Since CPU3 outputs a low-level signal by default, the first NMOS transistor Q41 is turned off by default. When no device is inserted into the second slot 5, because the second NMOS transistor Q45 is turned on, the control pin of the signal switching switch 2 is at a low level, the uplink signal pin is selected to the first downlink signal pin, and the downlink PCIE signal is switched to the first slot 4. When a device is inserted into the second slot 5, the second NMOS transistor Q45 is turned off, the control pin of the signal switching switch 2 is at a high level, the uplink signal pin is selected to the second downlink signal pin, and the downlink PCIE signal is switched to the second slot 5. Therefore, the PCIe slot switching circuit of this invention can automatically detect the insertion of a device into the second slot 5 and switch the signal, simplifying the operation. Simultaneously, if a device is inserted into the second slot 5 and it is necessary to switch the downstream PCIe signal to the first slot 4, this can be achieved by the CPU 3 issuing a high-level signal to turn on the first NMOS transistor Q41, which in turn pulls down the control pin of the signal switching switch 2, without needing to remove the device from the second slot 5.

[0036] Preferably, the gate of the second NMOS transistor Q45 is also grounded via the second capacitor C703.

[0037] Preferably, the second NMOS transistor Q45 is of model LBSS139WT1G.

[0038] Preferably, the resistance of the third resistor R962 is 1KΩ.

[0039] Preferably, the second pull-up resistor R960 has a resistance of 10KΩ.

[0040] It is understood that the specific component models and values ​​in the circuit of this utility model can be selected according to the motherboard type of the specific applicable electronic device or smart device.

[0041] In summary, this invention provides a PCIe slot switching circuit. A control signal from the CPU passes through a signal switching circuit to a signal switching switch. The signal switching switch then selects one of the two PCIe slots based on the output level signal from the signal switching circuit. This allows for switching one PCIe resource to two different PCIe slots to meet diverse customer needs. This enables the same motherboard to satisfy various customer requirements, saving costs and time in R&D, production, and inventory management. The PCIe slot switching circuit of this invention has a simple structure, does not require a PCIe hub chip, and is inexpensive.

[0042] As described above, those skilled in the art can make various other corresponding changes and modifications based on the technical solution and concept of this utility model, and all such changes and modifications should fall within the protection scope of the appended claims of this utility model.

Claims

1. A switching circuit for a PCIe slot, characterized in that, include: The signal switching circuit (1), signal switching switch (2), CPU (3), first slot (4), and second slot (5) are included. The signal switching switch (2) includes an uplink signal pin connected to the uplink PCIE signal, a first downlink signal pin connected to the first slot (4), a second downlink signal pin connected to the second slot (5), and a control pin connected to the signal switching circuit (1). The signal switching circuit (1) includes a first NMOS transistor (Q41). The gate of the first NMOS transistor (Q41) is connected to the control signal of the CPU (3) through a first resistor (R624). The source is grounded, and the drain is connected to the power supply (P3V3) through a first pull-up resistor (R266) and connected to the control pin of the signal switching switch (2). When the control pin of the signal switching switch (2) is low, the uplink signal pin is selected to the first downlink signal pin. When the control pin of the signal switching switch (2) is high, the uplink signal pin is selected to the second downlink signal pin.

2. The PCIe slot switching circuit as described in claim 1, characterized in that, The gate of the first NMOS transistor (Q41) is also grounded via the first capacitor (C531).

3. The PCIe slot switching circuit as described in claim 1, characterized in that, The first NMOS transistor (Q41) is model LBSS139WT1G.

4. The PCIe slot switching circuit as described in claim 1, characterized in that, The resistance of the first resistor (R624) is 1KΩ.

5. The PCIe slot switching circuit as described in claim 1, characterized in that, The first pull-up resistor (R266) has a resistance of 10KΩ.

6. The switching circuit for the PCIe slot as described in claim 1, characterized in that, The signal switching circuit (1) further includes a second NMOS transistor (Q45). The gate of the second NMOS transistor (Q45) is connected to the power supply (P3V3) via a third resistor (R962) and a second pull-up resistor (R960), and another connection is made to the device insertion detection pin of the second slot (5). The source is grounded, and the drain is connected to the power supply (P3V3) via a first pull-up resistor (R266) and another connection is made to the control pin of the signal switching switch (2). The CPU (3) outputs a low-level signal to the signal switching circuit (1) by default.

7. The PCIe slot switching circuit as described in claim 6, characterized in that, The gate of the second NMOS transistor (Q45) is also grounded via the second capacitor (C703).

8. The PCIe slot switching circuit as described in claim 6, characterized in that, The second NMOS transistor (Q45) is model LBSS139WT1G.

9. The switching circuit for a PCIe slot as described in claim 6, characterized in that, The resistance of the third resistor (R962) is 1KΩ.

10. The PCIe slot switching circuit as described in claim 6, characterized in that, The second pull-up resistor (R960) has a resistance of 10KΩ.

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