Adaptive circuit of PCIE slot

Abstract

The utility model relates to a kind of self-adapting circuit of PCIE slot, including signal switch, signal switching circuit, first slot, and second slot;The signal switch includes the uplink signal pin of connection uplink PCIE signal, the first downlink signal pin of connection first slot, the second downlink signal pin of connection second slot, and the control pin of connection signal switching circuit;The signal switching circuit includes NMOS tube, the gate electrode of the NMOS tube is connected with the device insertion detection pin of the second slot through first resistance in one way, is connected with power supply through first pull-up resistance in one way, source electrode is grounded, drain electrode is connected with power supply through second pull-up resistance in one way, one way is connected with the control pin of the signal switch;When the control pin of the signal switch is low level, uplink signal pin is gated to first downlink signal pin, when the control pin of the signal switch is high level, uplink signal pin is gated to second downlink signal pin.

Description

Technical Field

[0001] This utility model relates to the field of electronic computer technology, and in particular to an adaptive circuit for a PCIe slot. Background Technology

[0002] In this era of diversified information technology, as computer equipment is widely used in industrial control, enterprise office, user interaction, entertainment and other purposes, the usage scenarios of user groups are becoming increasingly segmented, and users' demand for personalized customization of computer equipment is growing.

[0003] The motherboard is the core of a computer hardware system. User customization of computer equipment is primarily achieved through adding functional modules via the motherboard's expansion interfaces or upgrading core hardware using the motherboard's compatibility features. Motherboard expansion interfaces include PCIe (PCI Express) expansion slots, M.2 Key E (WiFi / Bluetooth module interface), M.2 interfaces, and SATA interfaces.

[0004] PCIe is a core high-speed serial expansion interface standard in current computer architecture, supporting x1 / x4 / x8 / x16 lane widths. It can be used to connect motherboards to various expansion devices, such as graphics cards, sound cards, network cards, SSDs, and RAID cards. PCIe resources are the most important expansion resources for motherboards. Professional audio users can expand with independent sound cards through PCIe x1 slots to achieve high-fidelity audio processing; storage-intensive users can add NVMe SSDs through PCIe x4 slots to expand high-speed storage; office workers can upgrade WiFi 7 modules, 10 Gigabit Ethernet cards, etc. through PCIe x1 / x4 slots to optimize network experience; and professional creators can connect video capture cards and AI accelerator cards through PCIe x16 slots to enhance professional computing power.

[0005] Since the PCIe resources on a motherboard are limited, one solution to meet the diverse needs of different customers is to design different customized motherboards. However, this increases the cost and time of motherboard R&D, production, and inventory management. Therefore, it is necessary to design an adaptive circuit for the PCIe slot to meet the different needs of various customers on the same motherboard, thereby saving costs and time in R&D, production, and inventory management. Summary of the Invention

[0006] Therefore, the purpose of this invention is to provide an adaptive circuit for a PCIe slot that can switch one PCIe resource to two different PCIe slots to meet different customer needs.

[0007] To achieve the above objectives, this utility model provides an adaptive circuit for a PCIe slot, including a signal switching switch, a signal switching circuit, a first slot, and a second slot. The signal switching switch includes an uplink signal pin connected to an uplink PCIe signal, a first downlink signal pin connected to the first slot, a second downlink signal pin connected to the second slot, and a control pin connected to the signal switching circuit. The signal switching circuit includes an NMOS transistor, the gate of which is connected to the device insertion detection pin of the second slot via a first resistor and to the power supply via a first pull-up resistor, with its source grounded. The drain of the NMOS transistor is connected to the power supply via a second pull-up resistor and to the control pin of the signal switching switch. When the control pin of the signal switching switch is low, the uplink signal pin is selected to the first downlink signal pin; when the control pin of the signal switching switch is high, the uplink signal pin is selected to the second downlink signal pin.

[0008] The first slot is an M.2 Key E slot for connecting a WIFI module, and the second slot is a PCIe x1 slot, which can be used to connect various PCIe devices.

[0009] The gate of the NMOS transistor is also grounded via a capacitor.

[0010] The gate of the NMOS transistor is also connected to the ground pin of the second slot via a second resistor.

[0011] The NMOS transistor is model LBSS139WT1G.

[0012] The signal switching switch is model GMA340.

[0013] The resistance of the first resistor is 1KΩ.

[0014] The first pull-up resistor has a resistance of 10KΩ.

[0015] The second pull-up resistor has a resistance of 10KΩ.

[0016] The resistance of the second resistor is 1KΩ.

[0017] The beneficial effects of this invention are as follows: This invention provides an adaptive circuit for a PCIe slot. A signal switching circuit connects one slot to a signal switching switch. The signal switching circuit detects whether a device is connected to the slot. When no device is connected, it outputs a low-level signal to the signal switching switch, switching the PCIe signal to another slot. When a device is connected, it outputs a high-level signal to the signal switching switch, switching the downstream PCIe signal to that slot. This allows for switching one PCIe resource to two different PCIe slots to meet different customer needs, enabling the same motherboard to satisfy various customer requirements, thus saving costs and time in R&D, production, and inventory management. The adaptive circuit structure of this PCIe slot is simple and inexpensive. Attached Figure Description

[0018] The technical solution and other beneficial effects of this utility model will become apparent from the following detailed description of specific embodiments, in conjunction with the accompanying drawings.

[0019] Figure 1 This is a schematic diagram of a signal switching circuit according to an embodiment of the adaptive circuit for a PCIe slot of the present invention.

[0020] Figure 2 for Figure 1 A schematic diagram of the pin connections of the signal switching switch in an embodiment;

[0021] Figure 3 for Figure 1 A schematic diagram of the pin connections of the first slot in an embodiment;

[0022] Figure 4 for Figure 1 A schematic diagram of the pin connections of the second slot in an embodiment. Detailed Implementation

[0023] To further illustrate the technical means and effects of this utility model, the following detailed description is provided in conjunction with the preferred embodiments of this utility model and their accompanying drawings.

[0024] See Figure 1-4This utility model provides an adaptive circuit for a PCIe slot, including a signal switching switch 1, a signal switching circuit 2, a first slot 3, and a second slot 4; the signal switching switch 1 includes an uplink signal pin connected to the uplink PCIe signal, a first downlink signal pin connected to the first slot 3, a second downlink signal pin connected to the second slot 4, and a control pin connected to the signal switching circuit 2; the signal switching circuit 2 includes an NMOS transistor Q13, and the gate of the NMOS transistor Q13 (pin 1 of the NMOS transistor Q13) is connected to a first resistor R37. 1. The device insertion detection pin connected to the second slot 4 is connected to the power supply P3V3 via the first pull-up resistor R392. The source (pin 2 of NMOS transistor Q13) is grounded, and the drain (pin 3 of NMOS transistor Q13) is connected to the power supply P3V3 via the second pull-up resistor R224. The other pin is connected to the control pin of the signal switching switch 1. When the control pin of the signal switching switch 1 is low, the uplink signal pin is selected to the first downlink signal pin. When the control pin of the signal switching switch 1 is high, the uplink signal pin is selected to the second downlink signal pin.

[0025] When no device is connected to the second slot 4, the gate of NMOS transistor Q13 is pulled up to power supply P3V3 by the first pull-up resistor R392, the gate of NMOS transistor Q13 is at a high level, NMOS transistor Q13 is turned on, the drain of NMOS transistor Q13 is pulled down to ground (low level), the uplink signal pin is selected to the first downlink signal pin, and the downlink PCIE signal is selected to the first slot 3; when a device is connected to the second slot 4, the gate of NMOS transistor Q13 is pulled low, NMOS transistor Q13 is turned off, the drain of NMOS transistor Q13 is pulled up to power supply P3V3 (high level) by the second pull-up resistor R224, the uplink signal pin is selected to the second downlink signal pin, and the downlink PCIE signal is switched to the second slot 4.

[0026] The adaptive circuit of this PCIe slot connects one slot and a signal switching switch via a signal switching circuit. The signal switching circuit detects whether a device is connected to the slot. When no device is connected, it outputs a low-level signal to the signal switching switch, switching the PCIe signal to another slot. When a device is connected, it outputs a high-level signal to the signal switching switch, switching the downstream PCIe signal to that slot. This allows for switching one PCIe resource to two different PCIe slots to meet different customer needs, enabling the same motherboard to satisfy various customer requirements, thus saving costs and time in R&D, production, and inventory management. The adaptive circuit of this PCIe slot has a simple structure and low cost.

[0027] Figure 1-4In one embodiment, the first slot 3 is an M.2 Key E slot for connecting a WIFI module, and the second slot 4 is a PCIe X1 slot for connecting various PCIe devices.

[0028] Specifically, in this embodiment, pins 1-2 and 4-5 of signal switch 1 are uplink signal pins; pins 10-11 and 15-16 of signal switch 1 are first downlink signal pins, used to connect pins 35, 37, 41, and 43 of the first slot 3 to transmit downlink PCIe signals; pins 8-9 and 13-14 of signal switch 1 are second downlink signal pins, used to connect pins A16, A17, B14, and B15 of the second slot 4 to transmit downlink PCIe signals; pin 6 of signal switch 1 is a control pin, used to receive level signals from signal switching circuit 2. The device insertion detection pin of the second slot 4 is B17 (PRSNT2#).

[0029] Preferably, the gate of the NMOS transistor Q13 is also grounded via capacitor C347 to make the circuit more stable.

[0030] Preferably, the gate of the NMOS transistor Q13 is also connected to the ground pin of the second slot 4 via a second resistor R370. Specifically, the gate of the NMOS transistor Q13 is connected to pin B7 (GND#) of the second slot 4 via a second resistor R370, so that device insertion detection of the second slot 4 can still be realized when the device insertion detection pin (PRSNT2#) fails.

[0031] It is understood that the specific component models and values ​​in the circuit of this utility model can be selected according to the motherboard type of the specific applicable electronic device or smart device.

[0032] Specifically, Figure 1-4 In this embodiment, the NMOS transistor Q13 is model LBSS139WT1G.

[0033] Specifically, Figure 1-4 In this embodiment, the signal switching switch 1 is a GMA340.

[0034] Specifically, Figure 1-4 In one embodiment, the resistance of the first resistor R371 is 1KΩ.

[0035] Specifically, Figure 1-4 In one embodiment, the resistance of the first pull-up resistor R392 is 10KΩ.

[0036] Specifically, Figure 1-4 In this embodiment, the resistance of the second pull-up resistor R224 is 10KΩ.

[0037] Specifically, Figure 1-4 In one embodiment, the resistance of the second resistor R370 is 1KΩ.

[0038] In summary, this invention provides an adaptive circuit for a PCIe slot. A signal switching circuit connects one slot to a signal switching switch. The signal switching circuit detects whether a device is connected to the slot. When no device is connected, it outputs a low-level signal to the signal switching switch, switching the PCIe signal to another slot. When a device is connected, it outputs a high-level signal to the signal switching switch, switching the downstream PCIe signal to that slot. This allows for switching one PCIe resource to two different PCIe slots to meet different customer needs, enabling the same motherboard to satisfy various customer requirements, thus saving costs and time in R&D, production, and inventory management. The adaptive circuit for the PCIe slot of this invention has a simple structure and low cost.

[0039] As described above, those skilled in the art can make various other corresponding changes and modifications based on the technical solution and concept of this utility model, and all such changes and modifications should fall within the protection scope of the appended claims of this utility model.

Claims

1. An adaptive circuit for a PCIe slot, characterized in that, include: The signal switching switch (1), signal switching circuit (2), first slot (3), and second slot (4) are provided. The signal switching switch (1) includes an uplink signal pin connected to the uplink PCIE signal, a first downlink signal pin connected to the first slot (3), a second downlink signal pin connected to the second slot (4), and a control pin connected to the signal switching circuit (2). The signal switching circuit (2) includes an NMOS transistor (Q13). The gate of the NMOS transistor (Q13) is connected to the device insertion detection pin of the second slot (4) through a first resistor (R371) and to the power supply (P3V3) through a first pull-up resistor (R392). The source is grounded. The drain is connected to the power supply (P3V3) through a second pull-up resistor (R224) and to the control pin of the signal switching switch (1). When the control pin of the signal switching switch (1) is low, the uplink signal pin is selected to the first downlink signal pin. When the control pin of the signal switching switch (1) is high, the uplink signal pin is selected to the second downlink signal pin.

2. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The first slot (3) is an M.2 Key E slot, and the second slot (4) is a PCIE X1 slot.

3. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The gate of the NMOS transistor (Q13) is also grounded via a capacitor (C347).

4. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The gate of the NMOS transistor (Q13) is also connected to the ground pin of the second slot (4) via a second resistor (R370).

5. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The NMOS transistor (Q13) is model LBSS139WT1G.

6. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The signal switching switch (1) is model GMA340.

7. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The resistance of the first resistor (R371) is 1KΩ.

8. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The first pull-up resistor (R392) has a resistance of 10KΩ.

9. The adaptive circuit for a PCIe slot as described in claim 1, characterized in that, The second pull-up resistor (R224) has a resistance of 10KΩ.

10. The adaptive circuit for a PCIe slot as described in claim 4, characterized in that, The resistance of the second resistor (R370) is 1KΩ.

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