memory circuit

Abstract

A memory circuit includes a memory cell; a bit line; a complementary bit line; a pass gate transistor coupled to the memory cell and the bit line; a sense amplifier coupled to the bit line, the complementary bit line, and the pass gate transistor; and a precharge circuit coupled to a first node and to precharge the first node to a precharge voltage in response to a precharge control signal. The sense amplifier includes a first path between the bit line and the complementary bit line. The first path includes a first isolation transistor to receive an isolation control signal and coupled between the bit line and the first node; and a second inverter to receive a sense amplifier enable signal and coupled between a second node and a third node.

Description

Technical Field

[0001] This disclosure relates to a memory circuit, and more particularly to a memory circuit capable of pre-charging. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured to store data. As ICs become smaller and more complex, the resistance of the conductive lines within these digital devices changes, thus affecting the operating voltage of these digital devices and the overall performance of the IC. Utility Model Content

[0003] This disclosure provides a memory circuit. The memory circuit includes: a memory cell, a bit line, a complementary bit line, a channel gate transistor, a sense amplifier, and a precharge circuit. The channel gate transistor is coupled to the memory cell and the bit line. The sense amplifier is coupled to the bit line, the complementary bit line, and the channel gate transistor. The sense amplifier includes: a first path. The first path is between the bit line and the complementary bit line, and the first path includes: a first isolation transistor for receiving an isolation control signal and coupled between the bit line and a first node; and a first inverter for receiving a sense amplifier enable signal and coupled between a second node and a third node. The precharge circuit is coupled to the first node and is used to precharge the first node to a precharge voltage in response to the precharge control signal.

[0004] This disclosure provides another memory circuit. The memory circuit includes: memory cells, bit lines, complementary bit lines, word lines, channel gate transistors, a sense amplifier, and precharge and equalization circuitry. The channel gate transistors receive word line signals and are coupled to the word lines, memory cells, and bit lines. The sense amplifier is coupled to the bit lines, complementary bit lines, and channel gate transistors. The sense amplifier includes: a first path between the bit lines and the complementary bit lines, the first path including: a first isolation transistor for receiving an isolation control signal and coupled between the bit lines and a first node; and a first inverter for receiving a sense amplifier enable signal and coupled between a second node and a third node; and a second path between the first node and the complementary bit lines, the second path including: a first transistor for receiving a control signal and coupled between the first node and the complementary bit lines. The precharge and equalization circuit is coupled to the bit line and the complementary bit line, and is used to precharge a voltage of the bit line and the complementary bit line to the precharge voltage in response to the precharge / equalization control signal.

[0005] This disclosure provides another memory circuit. The memory circuit includes: a memory cell, a bit line, a complementary bit line, a word line, a channel gate transistor, a sense amplifier, and a precharge circuit. The channel gate transistor is coupled to the word line, the memory cell, and the bit line to receive a word line signal, thereby reading data stored in the memory cell to the bit line, thus increasing the voltage of the bit line by a signal voltage corresponding to the data stored in the memory cell. The sense amplifier is coupled to the bit line, the complementary bit line, and the channel gate transistor. The sense amplifier includes: a first path, a second path, a first transistor, and a second transistor. The first path is between the bit line and the complementary bit line. The first path includes: a first isolation transistor for receiving an isolation control signal and coupled between the bit line and a first node, and for decoupling or electrically coupling the sense amplifier to the bit line according to the isolation control signal; and a first inverter for receiving a sense amplifier enable signal and coupled between a second node and a third node. The voltage of the second node is set to a first threshold voltage of the first inverter. The second path is between the first node and the complementary bit line. The second path includes: a second isolation transistor for receiving an isolation control signal and coupled between the complementary bit line and the fourth node, and for electrically decoupling or coupling the sense amplifier to the complementary bit line according to the isolation control signal; and a second inverter for receiving a sense amplifier enable signal and coupled between the fifth and sixth nodes. The voltage of the fifth node is set to a second threshold voltage of the second inverter. A first transistor for receiving a control signal is coupled in parallel with the first inverter. A second transistor for receiving a control signal is coupled in parallel with the second inverter. A precharge circuit is coupled to the bit line and the complementary bit line and, in response to the precharge control signal, precharges the voltages of the bit line and the complementary bit line to a precharge voltage. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying items. Figure 1 The best way to understand this text is by referring to the detailed description below. Note that, according to industry standards, the features are not drawn to scale. In practice, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a block diagram of a memory circuit according to some embodiments.

[0008] Figure 2 This is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 3 It is a memory circuit according to some embodiments (such as Figure 2 The waveform timing diagram of the memory circuit in the memory.

[0010] Figure 4 It is a memory circuit according to some embodiments (such as Figure 2 The waveform timing diagram of the memory circuit in the memory.

[0011] Figure 5 This is a circuit diagram of a memory circuit according to some embodiments.

[0012] Figure 6 It is a memory circuit according to some embodiments (such as Figure 5 The waveform timing diagram of the memory circuit in the memory.

[0013] Figure 7 It is a memory circuit according to some embodiments (such as Figure 5 The waveform timing diagram of the memory circuit in the memory.

[0014] Figure 8 According to some embodiments Figure 1 , Figure 2 ,and Figure 5 The circuit diagram of the circuit that can be used in the circuit.

[0015] Figures 9A to 9B This is a flowchart of the operation method of the operating circuit according to some embodiments.

[0016] Figures 10A to 10B This is a flowchart of the operation method of the operating circuit according to some embodiments.

[0017] [Symbol Explanation]

[0018] 100, 200, 500: Memory circuit

[0019] 100BL: GIO Circuit

[0020] 100GC: Global Control Circuit

[0021] 102: Memory Cell Array

[0022] 102A~102D: Memory partitions

[0023] 110AC:WL driver circuit

[0024] 110AR: Memory Cell Array

[0025] 110BS: LIO circuit

[0026] 110L: Memory Bank

[0027] 110LC: Area Control Circuit

[0028] 110U: Memory Bank

[0029] 112: Memory Unit

[0030] 114: Circuit

[0031] 202: Sensing Amplifier Circuit

[0032] 204: Pre-charging and equalization circuit

[0033] 250: First Path

[0034] 252: Second Path

[0035] 300, 400, 600, 700: Timing Diagram

[0036] 502: Sensing Amplifier Circuit

[0037] 504: Pre-charge and equalization circuit

[0038] 560: Third Path

[0039] 562: Fourth Path

[0040] 800: Circuit

[0041] 802: Transistor

[0042] 900: Operating Instructions

[0043] 902~928: Steps

[0044] 910a: Steps

[0045] 922a~922b: Steps

[0046] 1000: Operating Instructions

[0047] 1002~1018: Steps

[0048] 1026: Steps

[0049] BL: Bitline

[0050] BL_IN: signal

[0051] BL_IN', BLB_IN': Inverted signals

[0052] BLB, BL2: Complementary bit lines

[0053] BLB_IN: Signal

[0054] BL': Bit line voltage

[0055] BLB': Complementary bit line voltage

[0056] BL2_IN,VBLEQ: Voltage

[0057] BLEQ, BLEQ1, BLEQ2: signal

[0058] C1, C2: Capacitors

[0059] D1: Leakage End Pole

[0060] G1: Gate terminal

[0061] S1: source terminal

[0062] I1, I2: Inverters

[0063] ISO: Isolation control signal

[0064] Nd1, Nd2, Nd3, Nd4, Nd5, Nd6: Nodes

[0065] OC: Control signal

[0066] SAEN: Sensing amplifier enable signal

[0067] SC: Memory Unit

[0068] t0, t1, t2, t3a, t3b, t4, t5, t6: Time

[0069] T1, T10, T11, T12, T2, T3, T4, T5, T6, T7, T8, T9: Transistors

[0070] VDD: Supply voltage

[0071] VSS: Reference supply voltage

[0072] Vth1, Vth2: Threshold voltages

[0073] WL: Character Line

[0074] WL': Character line signal

[0075] X: First direction

[0076] Y: Second direction Detailed Implementation

[0077] The following disclosure provides different embodiments or instances for implementing the features of the provided subject matter. Specific instances of components, materials, values, steps, configurations, or the like are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, configurations, or the like are contemplated. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0078] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0079] According to some embodiments, the memory circuit includes memory cells, bit lines, and complementary bit lines.

[0080] In some embodiments, the memory circuitry further includes a channel gate transistor coupled to the memory cell and the bit line.

[0081] In some embodiments, the memory circuitry further includes a sense amplifier. In some embodiments, the sense amplifier is coupled to a bit line, a complementary bit line, and a channel gate transistor.

[0082] In some embodiments, the sensing amplifier includes a first path. In some embodiments, the first path is between a bit line and a complementary bit line.

[0083] In some embodiments, the first path includes a first isolation transistor. In some embodiments, the first isolation transistor is used to receive an isolation control signal. In some embodiments, the first isolation transistor is coupled between a bit line and a first node.

[0084] In some embodiments, the first path further includes a first inverter. In some embodiments, the first inverter is used to receive a sense amplifier enable signal. In some embodiments, the first inverter is coupled between a second node and a third node.

[0085] In some embodiments, the first path further includes a first capacitor. In some embodiments, the first capacitor is coupled between the second node and one of the first node or the first isolation transistor.

[0086] In some embodiments, the first path further includes a second isolation transistor. In some embodiments, the second isolation transistor is used to receive an isolation control signal. In some embodiments, the second isolation transistor is coupled between the third node and the complementary bit line.

[0087] In some embodiments, the memory circuitry further includes a precharge circuit coupled to the first node. In some embodiments, the precharge circuitry is configured to precharge the first node to a precharge voltage in response to a precharge control signal.

[0088] In some embodiments, the random input offset voltage is a large noise component of the bit-line sense amplifier, thereby affecting the accuracy of one or more read operations of the memory cell. In some embodiments, the random input offset voltage is caused by process variations.

[0089] In some embodiments, by including a first isolation transistor between the first capacitor and the first bit line, random offsets in the input voltage of the memory circuit can be eliminated compared to other methods, while improving the accuracy and speed of one or more read operations performed by the memory circuit and / or the sensing amplifier.

[0090] Offset elimination does not incur a time penalty. Read latency is not reduced.

[0091] The input signal amplitude (Vsin) is increased to twice the normal value.

[0092] Figure 1 This is a block diagram of a memory circuit 100 according to some embodiments.

[0093] Figure 1 Simplified for illustrative purposes. In some embodiments, the memory circuitry 100 includes, except... Figure 1 Various elements other than those depicted herein, or otherwise configured to perform the operations described below.

[0094] The memory circuit 100 is an IC that includes memory partitions 102A to 102D, a global control circuit 100GC, and a global input / output (GIO) circuit 100BL.

[0095] Each memory partition 102A to 102D includes memory banks 110U and 110L adjacent to the word line (WL) driver circuit 110AC and the region control circuit 110LC. Each memory bank 110U and 110L includes a memory cell array 110AR and a local input output (LIO) circuit 110BS.

[0096] Memory partitions, such as memory partitions 102A to 102D, are part of memory circuitry 100 and include subsets of memory devices. Figure 1 (Not shown in the image) and adjacent circuitry for selectively accessing subsets of the memory device during programming and read operations. Figure 1 In the illustrated embodiment, the memory circuit 100 includes a total of four partitions. In some embodiments, the memory circuit 100 includes a total of more or less than four partitions.

[0097] GIO circuit 100BL is a circuit used to control access to one or more electrical paths (e.g., bit lines) of memory devices in corresponding memory banks 110U or 110L in each memory partition 102A-102D, for example, by generating one or more bit line signals. In some embodiments, GIO circuit 100BL includes global bit line driver circuitry. In some embodiments, GIO circuit 100BL is coupled to each memory bank 110U and 110L via corresponding global bit lines (not shown).

[0098] The global control circuit 100GC is a circuit used to control some or all of the programming and reading operations of each memory partition 102A to 102D, for example, by generating and / or outputting one or more control and / or enable signals.

[0099] In some embodiments, the global control circuit 100GC includes one or more analog circuits for interfacing with memory partitions 102A to 102D to program data into one or more memory devices and / or use data received from one or more memory devices in one or more circuit operations. In some embodiments, the global control circuit 100GC includes one or more global address decoding or pre-decoder circuits for outputting one or more address signals to the WL driver circuits 110AC in each memory partition 102A to 102D.

[0100] Each WL driver circuit 110AC is used to generate a character line signal on the corresponding character line WL. In some embodiments, each WL driver circuit 110AC is used to output the character line signal on the corresponding character line WL to the adjacent memory banks 110U and 110L of the corresponding memory partitions 102A to 102D.

[0101] Each region control circuit 110LC is an electronic circuit used to receive one or more address signals. Each region control circuit 110LC is used to generate signals corresponding to adjacent subsets of the memory device identified by the one or more address signals. In some embodiments, the adjacent subsets of the memory device correspond to rows in the memory device. In some embodiments, each region control circuit 110LC is used to generate complementary signal pairs. In some embodiments, each region control circuit 110LC is used to output signals to corresponding character line driver circuits within adjacent WL driver circuits 110AC in corresponding memory partitions 102A-102D. In some embodiments, the region control circuit 110LC includes a library decoder circuit.

[0102] Each LIO circuit 110BS is used to respond to the GIO circuit 100BL, for example, selectively accessing one or more bit lines (e.g., based on one or more BL control signals) of an adjacent subset of the memory device coupled to the corresponding memory cell array 110AR. Figure 2 (as shown in the diagram). In some embodiments, adjacent subsets of the memory device correspond to columns in the memory device. In some embodiments, the LIO circuit 110BS includes bit line selection circuitry.

[0103] Each LIO circuit 110BS includes one or more circuits 114. In some embodiments, each circuit 114 includes circuitry configured as a sense amplifier circuit. For example, according to some embodiments, during a read operation, circuitry 114 is a sense amplifier circuitry used to read data from at least one memory cell 112 in a corresponding row of memory cells in the corresponding memory cell array 110AR, and / or restore data thereto. In some embodiments, each circuit 114 includes circuitry configured as a write latch. For example, according to some embodiments, during a write operation, circuitry 114 is a write latch circuitry used to write data to at least one memory cell 112 in a corresponding row of memory cells in the corresponding memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a corresponding row of memory devices 112 in the memory cell array 110AR. In some embodiments, GIO circuit 100BL includes one or more circuits 114 (not shown).

[0104] Each memory bank 110U and 110L includes a corresponding memory cell array 110AR, which includes memory cells or memory devices 112 for access by adjacent LIO circuits 110BS and adjacent WL driver circuits 110AC during programming / writing and reading operations.

[0105] Each memory cell array 110AR includes an array of memory devices 112 having N columns and M rows, where M and N are positive integers. The columns of cells in the memory cell array 102 are arranged in a first direction X. The rows of cells in the memory cell array 102 are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, each row of memory devices 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0106] The memory device 112 is shown in memory banks 110U and 110L in memory partition 102A. For ease of explanation, the memory device 112 is not shown in memory banks 110U and 110L in memory partitions 102B, 102C, and 102D.

[0107] Memory device 112 is an electrical, electromechanical, electromagnetic, or other means for storing bit data represented by logical states. At least one logical state of memory device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, the logical state corresponds to a voltage level of charge stored in a given memory device 112. In some embodiments, the logical state corresponds to a physical property of a component of a given memory device 112, such as voltage, current, resistance, or magnetic orientation.

[0108] In some embodiments, memory device 112 includes one or more dynamic random access memory (DRAM) cells. Different types of memory cells in memory device 112 are within the scope of this disclosure. In some embodiments, memory device 112 includes one or more single-port (SP) static random access memory (SRAM) cells. In some embodiments, memory device 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, memory device 112 includes one or more multi-port SRAM cells. In some embodiments, memory device 112 includes one or more one-time programmable (OTP) memory devices, such as electronic fuse or antifuse devices, flash memory devices, random-access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, or the like. In some embodiments, memory device 112 is an OTP memory device including one or more OTP memory cells.

[0109] Other configurations of the memory circuit 100 are also within the scope of this disclosure.

[0110] Figure 2 This is a circuit diagram of a memory circuit 200 according to some embodiments.

[0111] Memory circuit 200 is Figure 1 The embodiments of a row and a column of memory cells in the memory cell array 110AR and circuit 114 are shown, therefore a similar detailed description is omitted. For example, the memory circuit 200 is illustrated in a non-limiting example, wherein the memory cell SC in the memory circuit 200 is... Figure 1 An embodiment of a row and a column of memory cells in the memory cell array 110AR, and the sense amplifier circuit 202 of the memory circuit 200 corresponds to... Figure 1 Circuit 114, therefore a similar detailed description is omitted. In some embodiments, the memory cell SC in memory circuit 200 corresponds to Figure 1The memory cell 112, therefore a similar detailed description is omitted. In some embodiments, transistor T10 corresponds to... Figure 1 The circuit 114, WL driver circuit 110AC, or zone control circuit 110LC are one or more of these, and therefore a similar detailed description is omitted. In some embodiments, the sense amplifier circuit 202 of the memory circuit 200 may be similar to circuit 114 of the LIO circuit 110BS. Figure 1 The GIO circuit 100BL is used in this, so a similar detailed description is omitted.

[0112] The memory circuit 200 includes a memory cell SC, a sense amplifier circuit 202, a bit line BL, a complementary bit line BLB, and a precharge and equalization circuit 204.

[0113] Memory cell SC is coupled to sense amplifier circuit 202. In some embodiments, memory cell SC is coupled to bit line BL via transistor T10. In some embodiments, memory cell SC is coupled to complementary bit line BLB via a transistor similar to transistor T10.

[0114] The memory cell SC is a DRAM cell. Other types or numbers of memory cells within the memory cell SC are also within the scope of this disclosure.

[0115] The first terminal of the memory cell SC is coupled to a reference voltage supply VSS. The second terminal of the memory cell SC is coupled to the drain / source of the transistor T10. In some embodiments, the memory cell SC is used to store at least one data bit represented by one or more logic states (e.g., logic low (e.g., logic 0) or logic high (e.g., logic 1)). In some embodiments, the first terminal of the memory cell SC is the anode of a capacitor, and the second terminal of the memory cell SC is the cathode of a capacitor. In some embodiments, the first terminal of the memory cell SC is the cathode of a capacitor, and the second terminal of the memory cell SC is the anode of a capacitor.

[0116] Other configurations of the memory cell SC are also within the scope of this disclosure.

[0117] The sense amplifier circuit 202 is coupled to the memory cell SC, bit line BL, complementary bit line BLB, and precharge and equalization circuit 204.

[0118] According to some embodiments, during a read operation of the memory cell SC, the sensing amplifier circuit 202 is used to sense or read data from the memory cell SC and to output a data signal Q. In some embodiments, the data signal Q corresponds to data read from the memory cell SC. In some embodiments, the data signal Q corresponds to data stored in the memory cell SC. In some embodiments, during a read operation of the memory cell SC, after the sensing amplifier circuit 202 senses or reads data from the memory cell SC, the sensing amplifier circuit 202 is further used to write back the data previously read from the memory cell SC during the read operation by applying a voltage to the memory cell SC, thereby recharging the capacitor during a memory restart operation.

[0119] In some embodiments, by including fewer transistors or logic devices than other methods, the sense amplifier circuit 202 has less standby leakage than other methods because fewer transistors or logic devices in the sense amplifier circuit 202 result in a lower total gate count than other methods.

[0120] The sensing amplifier circuit 202 includes transistors T4, T5, T6, T7, T8, T9, and T10, capacitors C1 and C2, inverter I1, and inverter I2.

[0121] In some embodiments, transistor T10 is not part of the sense amplifier circuit 202, but rather part of the memory circuit 200 or 500. In some embodiments, transistor T10 is a channel gate transistor.

[0122] In some embodiments, at least one or more of transistors T4, T5, T6, T7, T8, T9, or T10 are N-type transistors. In some embodiments, at least one or more of transistors T4, T5, T6, T7, T8, T9, or T10 are N-type field-effect transistors (NFETs). In some embodiments, at least one or more of transistors T4, T5, T6, T7, T8, T9, or T10 are N-type metal-oxide-semiconductor (NMOS) transistors.

[0123] The gate of transistor T10 is used to receive the word line signal WL'. In some embodiments, the gate of transistor T10 is coupled to the word line WL. The drain / source of transistor T10 is coupled to the memory cell SC. In some embodiments, transistor T10 is enabled or disabled in response to the word line signal WL'. In some embodiments, when enabled, transistor T10 electrically couples the memory cell SC to the bit line BL.

[0124] The source / drain of transistor T10, the drain / source of transistor T4, the drain / source of transistor T7, the drain / source of transistor T1, and each of the bit lines BL are coupled to each other.

[0125] The gate of transistor T4 is used to receive the isolation control signal ISO. In some embodiments, the gate of transistor T4 is coupled to the source of the isolation control signal ISO.

[0126] Node Nd1, the source / drain of transistor T4, the drain / source of transistor T2, and the first terminal of capacitor C1 are all coupled to each other.

[0127] Node Nd2, the source / drain of transistor T6, the second terminal of capacitor C1, and the input terminal of inverter I1 are all coupled to each other. In some embodiments, signal BL_IN is the signal of node Nd2.

[0128] Transistor T6 and inverter I1 are connected in parallel and coupled to each other. The gate of transistor T6 is used to receive the control signal OC. In some embodiments, the gate of transistor T6 is coupled to the source of the control signal OC.

[0129] Inverter I1 is enabled or disabled by the sense amplifier enable signal SAEN. In some embodiments, when inverter I1 is enabled by the sense amplifier enable signal SAEN, inverter I1 generates an inverted signal BL_IN' in response to the signal BL_IN. In some embodiments, the signal BL_IN is the inverse of the inverted signal BL_IN', and vice versa. In some embodiments, the inverted signal BL_IN' is the signal of node Nd3. In some embodiments, when inverter I1 is disabled by the sense amplifier enable signal SAEN, inverter I1 does not generate the inverted signal BL_IN'.

[0130] The input terminal of inverter I1 is used to receive the signal BL_IN. The output terminal of inverter I1 is used to output the inverted signal BL_IN'.

[0131] Node Nd3, the drain / source of transistor T6, the output terminal of inverter I1, and the source / drain of transistor T5 are all coupled to each other.

[0132] The gate of transistor T5 is used to receive the isolation control signal ISO. In some embodiments, the gate of transistor T5 is coupled to the source of the isolation control signal ISO.

[0133] The drain / source of transistor T5, the drain / source of transistor T8, the source / drain of crystal T1, and the complementary bit line BLB are all coupled to each other.

[0134] The gate of transistor T8 is used to receive the isolation control signal ISO. In some embodiments, the gate of transistor T8 is coupled to the source of the isolation control signal ISO.

[0135] Node Nd4, the source / drain of transistor T8, the drain / source of transistor T3, and the first terminal of capacitor C2 are all coupled to each other.

[0136] Node Nd5, the source / drain of transistor T9, the second terminal of capacitor C2, and the input terminal of inverter I2 are each coupled to each other. In some embodiments, the signal BLB_IN is the signal of node Nd5.

[0137] Transistor T9 and inverter I2 are connected in parallel and coupled to each other. The gate of transistor T9 is used to receive the control signal OC. In some embodiments, the gate of transistor T9 is coupled to the source of the control signal OC.

[0138] Inverter I2 is enabled or disabled by the sense amplifier enable signal SAEN. In some embodiments, when inverter I2 is enabled by the sense amplifier enable signal SAEN, inverter I2 generates an inverted signal BLB_IN' in response to the signal BLB_IN. In some embodiments, the inverted signal BLB_IN' is the signal of node Nd6. In some embodiments, when inverter I2 is disabled by the sense amplifier enable signal SAEN, inverter I2 does not generate the inverted signal BLB_IN'.

[0139] The input terminal of inverter I2 is used to receive the signal BLB_IN. The output terminal of inverter I2 is used to output the inverted signal BLB_IN'.

[0140] Node Nd6, the drain / source of transistor T9, the output terminal of inverter I2, and the source / drain of transistor T7 are all coupled to each other.

[0141] The gate of transistor T7 is used to receive the isolation control signal ISO. In some embodiments, the gate of transistor T7 is coupled to the source of the isolation control signal ISO.

[0142] In some embodiments, transistors T4 and T5, capacitor C1, inverter I1, and nodes Nd1, Nd2, and Nd3 form part of a first path 250. The first path 250 is coupled between bit line BL and complementary bit line BLB. In some embodiments, the first path 250 further includes transistor T6.

[0143] In some embodiments, transistors T7 and T8, capacitor C2, inverter I2, and nodes Nd4, Nd5, and Nd6 form part of the second path 252. The second path 252 is coupled between bit line BL and complementary bit line BLB. In some embodiments, the second path 252 further includes transistor T9.

[0144] The precharge and equalization circuit 204 is coupled to bit line BL, complementary bit line BLB, memory cell SC, and sense amplifier 202.

[0145] The pre-charge and equalization circuit 204 is used to respond to at least one of the signals BLEQ1 or BLEQ2 by pre-charging and equalizing the voltage of bit line BL and the voltage of complementary bit line BLB to voltage VVBLEQ.

[0146] In some embodiments, the precharge and equalization circuit 204 is used to precharge and equalize the voltage of bit line BL and complementary bit line BLB to voltage VBLEQ before a read operation of memory cell SC. In some embodiments, the precharge and equalization circuit 204 is used to equalize the voltage of bit line BL and complementary bit line BLB to voltage VBLEQ in response to signal BLEQ1.

[0147] In some embodiments, the voltage VBLEQ is equal to the voltage between the supply voltage VDD and the supply reference voltage VSS. In some embodiments, the voltage VBLEQ is equal to the supply voltage VDD / 2. In some embodiments, the voltage VBLEQ is equal to the supply voltage VDD. In some embodiments, the voltage VBLEQ is equal to the supply reference voltage VSS. Other values ​​for the voltage VBLEQ are also within the scope of the various embodiments.

[0148] The pre-charging and equalization circuit 204 includes transistors T1, T2, and T3.

[0149] In some embodiments, at least one or more of transistors T1, T2, or T3 are P-type transistors. In some embodiments, at least one or more of transistors T1, T2, or T3 are P-type field-effect transistors (PFETs). In some embodiments, at least one or more of transistors T1, T2, or T3 are P-type metal-oxide-semiconductor (PMOS).

[0150] Transistors T2 and T3 form a pre-charge circuit. Transistors T2 and T3 are used to pre-charge bit line BL and complementary bit line BLB to voltage VBLEQ in response to signal BLEQ2. PMOS transistor T1 is an equalization circuit. Transistor T1 is used to equalize the voltage of bit line BL and complementary bit line BLB in response to signal BLEQ1. In some embodiments, transistor T1 is used to equalize the voltage of bit line BL and complementary bit line BLB to voltage VBLEQ in response to signal BLEQ1.

[0151] The gates of transistors T2 and T3 are coupled together and used to receive the signal BLEQ2. In some embodiments, the signal BLEQ2 is a precharge signal.

[0152] The drain / source of transistors T2 and T3 are coupled to bit line BL and complementary bit line BLB, respectively. The source / drain of transistors T2 and T3 are coupled together to receive voltage VBLEQ. In some embodiments, voltage VBLEQ is the supply voltage.

[0153] In some embodiments, when a low logic value is applied to signal BLEQ2, transistors T2 and T3 are turned on, pulling the corresponding bit line BL and complementary bit line BLB to the supply voltage VBLEQ. As a result, bit line BL and complementary bit line BLB are pre-charged to the supply voltage VBLEQ.

[0154] Transistor T1 is coupled between bit line BL and complementary bit line BLB. The gate of transistor T1 is used to receive signal BLEQ1. In some embodiments, signal BLEQ1 is an equalization signal.

[0155] The drain / source of transistor T1 is coupled to bit line BL. The source / drain of transistor T1 is coupled to complementary bit line BLB. In some embodiments, when a low logic value is applied to signal BLEQ1, transistor T1 is turned on, electrically coupling bit line BL to complementary bit line BL2. As a result, the voltage of bit line BL and the voltage of complementary bit line BLB are balanced. In some embodiments, the voltage of bit line BL and the voltage of complementary bit line BLB are balanced to the supply voltage VBLEQ. In some embodiments, the source / drain of one or more transistors in this disclosure can be used interchangeably with the drain / source.

[0156] Other configurations, the number of transistors, or the type of transistors in the pre-charge and equalization circuit 204 are also within the scope of this disclosure. For example, using other circuits and / or other types of transistors or a certain number of transistors to pre-charge and / or equalize bit line BL and complementary bit line BLB is also within the scope of various embodiments.

[0157] In some embodiments, the random input offset voltage is a large noise component of the bit-line sense amplifier, thereby affecting the accuracy of one or more read operations of the memory cell. In some embodiments, the random input offset voltage is caused by process variations and / or asymmetry (e.g., random mismatch).

[0158] In some embodiments, by including an isolation transistor T4 between capacitor C1 and bit line BL, or by including an isolation transistor T8 between capacitor C2 and complementary bit line BLB, random offsets to the input voltage of memory circuit 200 can be reduced and / or eliminated compared to other methods, while improving the accuracy and speed of one or more read operations performed by memory circuit 200 and / or sense amplifier 202.

[0159] In some embodiments, during a read operation of memory cell SC, by including an isolation transistor T4 between capacitor C1 and bit line BL, or an isolation transistor T8 between capacitor C2 and complementary bit line BLB, the voltage of node Nd2 (signal BL_IN) is boosted by voltage Vsig, thereby reducing and / or eliminating random offsets in the input voltage of memory circuit 200, while improving the accuracy and speed of one or more read operations performed by memory circuit 200 and / or sense amplifier 202 compared to other methods.

[0160] Other configurations of the memory circuit 200 are also within the scope of this disclosure.

[0161] Figure 3 It is a memory circuit according to some embodiments (such as Figure 2 The waveform timing diagram of the memory circuit 200 in the middle is shown in Figure 300.

[0162] In some embodiments, Figure 3 According to some embodiments Figure 1 Timing diagram 300 for memory circuit 100.

[0163] In some embodiments, at least one of memory partitions 102A, 102B, 102C, or 102D is applied. Figure 1 One or more read and / or write operations of the memory bank in at least memory circuit 100, the timing diagram 300 corresponding to the waveforms during the read and write operations of at least one of memory partitions 102A, 102B, 102C, or 102D.

[0164] In some embodiments, for Figure 2 At least one memory cell SC in the memory circuit 200 is subjected to one or more read operations and / or write operations, and the timing diagram 300 corresponds to Figure 2 The waveform during read and / or write operations of the memory cell SC in the memory circuit 200.

[0165] Timing diagram 300 includes the waveforms of signals BLEQ2, BLEQ1, word line signal WL', control signal OC, sense amplifier enable signal SAEN, isolation control signal ISO, bit line voltage BL', complementary bit line voltage BLB', signal BL_IN, and signal BLB_IN.

[0166] At time t0, signal BLEQ2 is logic low, signal BLEQ1 is logic low, word line signal WL' is logic low, control signal OC is logic high, sense amplifier enable signal SAEN is logic low, isolation control signal ISO is logic high, bit line voltage BL' is equal to voltage VBLEQ, complementary bit line voltage BLB' is equal to voltage VBLEQ, signal BL_IN is equal to voltage VBLEQ, and signal BLB_IN is equal to voltage VBLEQ.

[0167] At time t0, in response to signal BLEQ2 being logic low, transistors T2 and T3 are turned on.

[0168] At time t0, in response to the isolation control signal ISO being logic high, transistors T4, T5, T7, and T8 are turned on.

[0169] For example, at time t0, in response to transistor T4 turning on, node Nd1 is coupled to bit line BL. For example, at time t0, in response to transistor T2 turning on and node Nd1 being coupled to bit line BL, transistor T2 is used to precharge bit line voltage BL' to voltage VBLEQ.

[0170] For example, at time t0, in response to transistor T8 turning on, node Nd4 is coupled to the complementary bit line BLB. In response to transistor T3 turning on and node Nd4 being coupled to the complementary bit line BLB, transistor T3 is used to precharge the complementary bit line voltage BLB' to voltage VVBLEQ.

[0171] At time t0, in response to signal BLEQ1 being logic low, transistor T1 is turned on and used to equalize the voltage of bit line BL and complementary bit line BLB to voltage VVBLEQ.

[0172] At time t0, in response to the word line signal WL' being logic low, transistor T10 is turned off, and memory cell SC is decoupled from bit line BL.

[0173] At time t0, in response to the control signal OC being logic low, transistor T6 is turned on, thereby electrically coupling nodes Nd2 and Nd3 to each other; transistor T9 is turned on, thereby electrically coupling nodes Nd5 and Nd6 to each other.

[0174] For example, at time t0, in response to nodes Nd2 and Nd3 being coupled to each other and transistor T5 being turned on, node Nd2 (signal BL_IN) is electrically coupled to the complementary bit line BLB and precharged to voltage VBLEQ.

[0175] For example, at time t0, in response to nodes Nd5 and Nd6 being coupled to each other and transistor T7 being turned on, node Nd5 (signal BLB_IN) is electrically coupled to bit line BL and precharged to voltage VBLEQ.

[0176] At time t0, in response to the sense amplifier enable signal SAEN being low, the inverters I1 and I2 of the sense amplifier 202 are turned off.

[0177] Between time t1 and time t6, a read operation is performed on memory cell SC.

[0178] The period between time t1 and time t3a is called the offset elimination phase of memory circuit 200.

[0179] The period between time t1 and time t3b is called the bit line development stage of memory circuit 200.

[0180] The period between time t3b and time t4 is called the recovery phase of memory circuit 200.

[0181] At time t1, the signal BLEQ1, the word line signal WL', and the sense amplifier enable signal SAEN transition from logic low to logic high.

[0182] For example, at time t1, in response to the signal BLEQ1 transitioning from logic low to logic high, transistor T1 is turned off, thereby decoupling bit line BL from complementary bit line BLB.

[0183] For example, at time t1, in response to at least the word line signal WL' transitioning from logic low to logic high, transistor T10 turns on, thereby coupling bit line BL to memory cell SC. In some embodiments, at time t1, by coupling bit line BL to memory cell SC, data stored in memory cell SC (e.g., Vsig) is transferred to bit line BL, thereby increasing bit line voltage BL' by voltage Vsig. In some embodiments, the data stored in memory cell SC is voltage Vsig. In this example, the data stored in memory cell SC (e.g., Vsig) is logic 1. In some embodiments, the data stored in memory cell SC (e.g., Vsig) is logic 0.

[0184] For example, at time t1, in response to the sense amplifier enable signal SAEN transitioning from logic low to logic high, inverters I1 and I2 are turned on. At time t1, in response to inverter I1 turning on, the signal BL_IN is made equal to the threshold voltage Vth1 of inverter I1. At time t1, in response to inverter I2 turning on, the signal BLB_IN is made equal to the threshold voltage Vth2 of inverter I2.

[0185] At time t1, the isolation control signal ISO transitions from logic high to logic low. At least in response to the transition of the isolation control signal ISO from logic high to logic low, transistors T4, T5, T7, and T8 are turned off. For example, at time t1, in response to the turn-off of transistors T4 and T7, the corresponding nodes Nd1 and Nd6 are electrically decoupled from bit line BL. In some embodiments, at time t1, in response to the turn-off of transistors T5 and T8, the corresponding nodes Nd3 and Nd4 are electrically decoupled from complementary bit line BLB. In some embodiments, at time t1, due to the turn-off of transistors T4, T5, T7, and T8, inverters I1 and I2 are electrically isolated from bit line BL and complementary bit line BLB.

[0186] At time t2, the control signal OC and the sense amplifier enable signal SAEN change from logic high to logic low.

[0187] For example, at time t2, at least in response to the sense amplifier enable signal SAEN transitioning from logic high to logic low, inverters I1 and I2 are turned off.

[0188] For example, at time t2, in response to the control signal OC transitioning from logic high to logic low, transistor T6 is turned off, thereby electrically decoupling nodes Nd2 and Nd3 from each other; transistor T9 is turned off, thereby electrically decoupling nodes Nd5 and Nd6 from each other.

[0189] In some embodiments, at time t2, signals BL_IN and BLB_IN can be stabilized by electrical isolation from bit line BL and complementary bit line BLB, thereby allowing the offset elimination process to be implemented by memory circuit 200.

[0190] In some embodiments, between times t1 and t3a, capacitor C1 is used to store the offset of inverter I1 and capacitor C2 is used to store the offset of inverter I2, thereby allowing memory circuit 200 to take the offset into account and thus implement the offset cancellation process.

[0191] In some embodiments, the offset of memory circuitry 200 or 500 is caused by manufacturing process variations and asymmetry (e.g., random mismatch). In some embodiments, the offset is reduced and / or eliminated by memory circuitry 200 or 500.

[0192] At time t2, signal BLEQ2 transitions from logic low to logic high.

[0193] For example, at time t2, in response to the signal BLEQ2 transitioning from logic low to logic high, transistors t2 and T3 are turned off, thereby decoupling voltage VVBLEQ from nodes Nd1 and Nd4.

[0194] At time t3a, the isolation control signal ISO transitions from logic low to logic high. At least in response to the transition of the isolation control signal ISO from logic low to logic high, transistors T4, T5, T7, and T8 are turned on. For example, at time t3a, in response to the turning on of transistors T4 and T7, the corresponding nodes Nd1 and Nd6 are electrically coupled to bit line BL. In some embodiments, at time t3a, by electrically coupling node Nd1 to bit line BL, the voltage of node Nd1 is equal to the bit line voltage BL'. In some embodiments, at time t3a, the bit line voltage BL' is equal to the sum of voltage VBLEQ and voltage Vsig, thereby boosting the signal BL_IN (which is equal to the threshold voltage Vth1 of inverter I1 at time T2) to voltage Vsig through capacitor C1. In some embodiments, at time t3a, the signal BL_IN is equal to the sum of voltage Vsig and the threshold voltage Vth1 of inverter I1.

[0195] For example, at time t3a, transistors T5 and T8 are turned on, thereby electrically coupling the corresponding nodes Nd3 and Nd4 to the complementary bit line BLB. In some embodiments, at time t3a, due to the turn-on of transistors T4, T5, T7, and T8, inverters I1 and I2 are no longer electrically isolated from bit line BL and the complementary bit line BLB.

[0196] At time t3a, inverters I1 and I2 are disabled, transistors T6 and T9 are turned off, and the offset elimination process ends.

[0197] Between times t3a and t3b, signals BL_IN and BLB_IN are stable, and inverters I1 and I2 are disabled.

[0198] Between times t3a and t3b, transistors T4, T5, T7, and T8 are turned on, and the sensing amplifier 202 is ready to sense bit line BL.

[0199] At time t3b, the sense amplifier enable signal SAEN transitions from logic low to logic high.

[0200] For example, at time t3b, at least in response to the sense amplifier enable signal SAEN transitioning from logic low to logic high, inverters I1 and I2 are turned on.

[0201] At time t3b, in response to the conduction of inverters I1 and I2, which are used to sense the voltage difference between the bit line voltage BL' and the complementary bit line voltage BLB', the signal BL_IN and the bit line voltage BL' are pulled towards the supply voltage VDD, and the signal BLB_IN and the complementary bit line voltage BLB' are pulled towards the supply voltage VSS.

[0202] Between times t3b and t4, the bit line voltage BL' is equal to the supply voltage VDD, and during the write-back operation, the bit line voltage BL' is stored as data (e.g., logic 1) into memory cell SC. Figure 3 (Marked as "Restore" in the middle).

[0203] At time t4, the word line signal WL' transitions from logic high to logic low.

[0204] For example, at time t4, at least in response to the word line signal WL' transitioning from logic high to logic low, transistor T10 is turned off, thus decoupling the bit line BL from the memory cell SC.

[0205] At time t5, the sense amplifier enable signal SAEN transitions from logic high to logic low.

[0206] For example, at time t5, at least in response to the sense amplifier enable signal SAEN changing from logic high to logic low, inverters I1 and I2 are turned off.

[0207] At time t5, the control signal OC changes from logic low to logic high.

[0208] For example, at time t5, in response to the control signal OC transitioning from logic low to logic high, transistor T6 turns on, thereby electrically coupling nodes Nd2 and Nd3 to each other; transistor T9 turns on, thereby electrically coupling nodes Nd5 and Nd6 to each other.

[0209] In some embodiments, at time t5, by electrically coupling nodes Nd2 and Nd3 to each other, node Nd2 is electrically coupled to the complementary bit line BLB, thus pulling the signal BL_IN to the complementary bit line voltage BLB' (e.g., VSS).

[0210] In some embodiments, at time t5, node Nd5 is electrically coupled to bit line BL by electrically coupling nodes Nd5 and Nd6 to each other, thus pulling the signal BLB_IN to bit line voltage BL' (e.g., VDD).

[0211] At time t6, signals BLEQ1 and BLEQ2 transition from logic high to logic low.

[0212] For example, at time t6, in response to the signal BLEQ1 transitioning from logic high to logic low, transistor T1 turns on, thereby coupling bit line BL to its complementary bit line BLB.

[0213] At time t6, signal BLEQ2 transitions from logic high to logic low.

[0214] For example, at time t6, in response to the signal BLEQ2 transitioning from logic high to logic low, transistors T2 and T3 turn on, thereby coupling the voltage VVBLEQ to nodes Nd1 and Nd4.

[0215] At time t6, transistor T2 is used to precharge the bit line voltage BL' to voltage VBLEQ, thereby pulling the bit line voltage BL' towards voltage VBLEQ.

[0216] At time t6, transistor T3 is used to precharge the complementary bit line voltage BLB' to voltage VBLEQ, thereby pulling the bit line voltage BL' towards voltage VBLEQ.

[0217] In some embodiments, the transition of the control signal OC from logic low to logic high at time t5 occurs at different times. For example, in some embodiments, the transition of the control signal OC from logic low to logic high may occur at time t6 or after time t6.

[0218] In some embodiments, timing diagram 300 enables memory circuitry 200 to achieve one or more benefits described herein, including the details discussed herein.

[0219] Other configurations of timing diagram 300 are also within the scope of this disclosure.

[0220] Figure 4 It is a memory circuit according to some embodiments (such as Figure 2 The waveform timing diagram of the memory circuit 200 in the middle is shown in Figure 400.

[0221] Timing diagram 400 is Figure 3 A variation of timing diagram 300 is shown, therefore a similar detailed description is omitted. For example, timing diagram 400 illustrates a non-limiting instance, where... Figure 4 The sensing amplifier enable signal SAEN in the middle has a single pulse, while Figure 3 The sensing amplification enable signal SAEN has multiple pulses, so a similar detailed description is omitted.

[0222] In some embodiments, Figure 4 According to some embodiments Figure 1 Timing diagram 400 for memory circuit 100.

[0223] In some embodiments, at least one of memory partitions 102A, 102B, 102C, or 102D is applied. Figure 1 One or more read and / or write operations of the memory bank in at least memory circuit 100, the timing diagram 400 corresponding to the waveforms during the read and write operations of at least one of memory partitions 102A, 102B, 102C or 102D.

[0224] In some embodiments, for Figure 2 At least the memory cell SC in the memory circuit 200 is subjected to one or more read operations and / or write operations, and the timing diagram 400 corresponds to Figure 2 The waveform during read and / or write operations of the memory cell SC in the memory circuit 200.

[0225] Timing diagram 400 includes the waveforms of signals BLEQ2, BLEQ1, word line signal WL', control signal OC, sense amplifier enable signal SAEN, isolation control signal ISO, bit line voltage BL', complementary bit line voltage BLB', signal BL_IN, and signal BLB_IN.

[0226] At time t0, signal BLEQ2 is logic low, signal BLEQ1 is logic low, word line signal WL' is logic low, control signal OC is logic high, sense amplifier enable signal SAEN is logic low, isolation control signal ISO is logic high, bit line voltage BL' is equal to voltage VBLEQ, complementary bit line voltage BLB' is equal to voltage VBLEQ, signal BL_IN is equal to voltage VBLEQ, and signal BLB_IN is equal to voltage VBLEQ.

[0227] exist Figures 3 to 4 In the diagram, from time t0 to time t1, the operation of memory circuit 200 in response to timing diagram 400 is the same as the operation of memory circuit 200 in response to timing diagram 300, therefore a similar detailed description is omitted.

[0228] exist Figure 4 During the period between time t1 and time t6, a read operation is performed on memory cell SC.

[0229] exist Figure 4 In this context, the period between time t2 and time t3a is referred to as the offset elimination phase of memory circuit 200.

[0230] exist Figure 4 In this context, the period between time t1 and time t3a is referred to as the bit line development stage of memory circuit 200.

[0231] exist Figure 4 In this context, the period between time t3a and time t4 is referred to as the recovery phase of memory circuit 200.

[0232] exist Figure 4 At time t1, signals BLEQ1, BLEQ2, and word line signal WL' transition from logic low to logic high.

[0233] For example, at time t1, in response to the signal BLEQ1 transitioning from logic low to logic high, transistor T1 is turned off, thereby decoupling bit line BL from complementary bit line BLB.

[0234] For example, at time t1, in response to the signal BLEQ2 transitioning from logic low to logic high, transistors T2 and T3 are turned off, thereby decoupling voltage VVBLEQ from nodes Nd1 and Nd4.

[0235] For example, at time t1, in response to the word line signal WL' transitioning from logic low to logic high, transistor T10 turns on, thereby coupling bit line BL to memory cell SC. In some embodiments, at time t1, by coupling bit line BL to memory cell SC, data stored in memory cell SC (e.g., Vsig) is transferred to bit line BL, thereby increasing bit line voltage BL' by voltage Vsig. In this example, the data stored in memory cell SC (e.g., Vsig) is logic 1. In some embodiments, the data stored in memory cell SC (e.g., Vsig) is logic 0.

[0236] exist Figure 4 At time t1, the isolation control signal ISO transitions from logic high to logic low. At least in response to the transition of the isolation control signal ISO from logic high to logic low, transistors T4, T5, T7, and T8 are turned off. For example, at time t1, in response to the turn-off of transistors T4 and T7, the corresponding nodes Nd1 and Nd6 are electrically decoupled from bit line BL. For example, at time t1, in response to the turn-off of transistors T5 and T8, the corresponding nodes Nd3 and Nd4 are electrically decoupled from complementary bit line BLB.

[0237] exist Figure 4 At time t2, the sense amplifier enable signal SAEN changes from logic low to logic high.

[0238] For example, in Figure 4 At time t2, at least in response to the sense amplifier enable signal SAEN transitioning from logic low to logic high, inverters I1 and I2 are turned on. Figure 4 At time t2, in response to the inverter I1 turning on, the signal BL_IN equals the threshold voltage Vth1 of inverter I1. Figure 4 At time t2, in response to the inverter I2 turning on, the signal BLB_IN is made equal to the threshold voltage Vth2 of inverter I2. In some embodiments, in response to the inverters I1 and I2 turning on, the offset cancellation process implemented by the memory circuit 200 begins at time t2 and ends at time t3a. Figure 4 Between time t2 and t3a, capacitor C1 is used to store the offset of inverter I1, and capacitor C2 is used to store the offset of inverter I2, thus allowing memory circuit 200 to take the offset into account and implement the offset cancellation process.

[0239] exist Figure 4During the interval between time t2 and t3a, signals BL_IN and BLB_IN can be stabilized by being electrically isolated from bit line BL and complementary bit line BLB, thereby allowing the offset elimination process to be implemented through memory circuit 200.

[0240] In some embodiments, Figure 4 At time t2, due to the turn-off of transistors T4, T5, T7, and T8, inverters I1 and I2 are electrically isolated from bit line BL and complementary bit line BLB.

[0241] exist Figure 4 At time t3a, the control signal OC changes from logic high to logic low.

[0242] For example, at time t2, in response to the control signal OC transitioning from logic high to logic low, transistor T6 is turned off, thereby electrically decoupling nodes Nd2 and Nd3 from each other; transistor T9 is turned off, thereby electrically decoupling nodes Nd5 and Nd6 from each other.

[0243] exist Figure 4 At time t3a, the isolation control signal ISO transitions from logic low to logic high. At least in response to the transition of the isolation control signal ISO from logic low to logic high, transistors T4, T5, T7, and T8 are turned on. In some embodiments, in Figure 4 At time t3a, due to the conduction of transistors T4, T5, T7, and T8, inverters I1 and I2 are no longer electrically isolated from bit line BL and complementary bit line BLB.

[0244] For example, in Figure 4 At time t3a, transistors T5 and T8 are turned on, thereby electrically coupling the corresponding nodes Nd3 and Nd4 to the complementary bit line BLB.

[0245] For example, in Figure 4 At time t3a, transistors T4 and T7 are turned on, thereby electrically coupling the corresponding nodes Nd1 and Nd6 to bit line BL. In some embodiments, at Figure 4 At time t3a, by electrically coupling node Nd1 to bit line BL, the voltage of node Nd1 is equal to the bit line voltage BL'. In some embodiments, in Figure 4 At time t3a, the bit line voltage BL' is equal to the sum of voltage VBLEQ and voltage Vsig, therefore initially the signal BL_IN is boosted to voltage Vsig through capacitor C1. However, due to the inverters I1 and I2 in... Figure 4At time t3a, the circuit is already turned on. Therefore, once inverters I1 and I2 are no longer electrically isolated from the bit line BL and complementary bit line BLB through the isolation control signal ISO, inverters I1 and I2 are used to sense the voltage difference between the bit line voltage BL' and the complementary bit line voltage BLB'. Figure 4 At time t3a, since inverters I1 and I2 are already turned on, the signal BL_IN and the bit line voltage BL' are pulled to the voltage supply VDD, and the signal BLB_IN and the complementary bit line voltage BLB' are pulled to the voltage supply VSS.

[0246] In some embodiments, Figure 4 The time series diagram 400 from time t3a to time t4 is shown in Figure 400. Figure 3 The timing diagram 300 from time t3b to time t4 is the same, therefore a similar detailed description is omitted. In some embodiments, Figure 4 The time series diagram 400 from time t4 to time t6 is shown in Figure 400. Figure 3 The timing diagram 300 from time t4 to time t6 is the same, therefore a similar detailed description is omitted. In some embodiments, Figure 4 Timing plot 400 after time t6 Figure 3 The timing diagram 300 after time t6 is the same, so a similar detailed description is omitted.

[0247] In some embodiments, Figure 4 and Figure 3 The same timing diagram for the duration causes memory circuit 200 to... Figure 4 and Figure 3 Similar operations within the same duration, where the timing diagram is identical, are omitted in a detailed description.

[0248] In some embodiments, the transition of the control signal OC from logic low to logic high at time t5 occurs at different times. For example, in some embodiments, the transition of the control signal OC from logic low to logic high may occur at time t6 or after time t6.

[0249] In some embodiments, timing diagram 400 enables memory circuitry 200 to achieve one or more benefits described herein, including the details discussed herein.

[0250] Other configurations of timing diagram 400 are also within the scope of this disclosure.

[0251] Figure 5 This is a circuit diagram of a memory circuit 500 according to some embodiments.

[0252] Memory circuit 500 is Figure 2Variations of memory circuit 200 are shown, therefore a similar detailed description is omitted. For example, memory circuit 500 is illustrated in a non-limiting example, wherein node Nd1 and the first terminal of capacitor C1 are connected via... Figure 5 Transistor T11 is coupled to complementary bit line BLB, and node Nd4 and the first terminal of capacitor C2 are connected via Figure 5 Transistor T12 is coupled to bit line BL, so a similar detailed description is omitted.

[0253] The memory circuit 500 includes a memory cell SC, a sense amplifier circuit 502, a bit line BL, a complementary bit line BLB, and a precharge and equalization circuit 504.

[0254] and Figure 2 Compared to the memory circuit 200, Figure 5 The sensing amplifier circuit 502 replaces the sensing amplifier circuit 202, therefore a similar detailed description is omitted. Figure 2 Compared to the memory circuit 200, Figure 5 The pre-charging and equalization circuit 504 replaces the pre-charging and equalization circuit 204, therefore a similar detailed description is omitted.

[0255] The sensing amplifier circuit 502 includes transistors T4, T5, T6, T7, T8, T9, T10, T11, and T12, capacitors C1 and C2, inverter I1, and inverter I2.

[0256] In some embodiments, at least one or more of transistors T11 or T12 are N-type transistors. In some embodiments, at least one or more of transistors T11 or T12 are NFETs. In some embodiments, at least one or more of transistors T11 or T12 are NMOS transistors.

[0257] The gate of transistor T11 is used to receive a control signal OC. In some embodiments, the gate of transistor T11 is coupled to the source of the control signal OC. Transistor T11 is enabled or disabled in response to the control signal OC. In some embodiments, when enabled, transistor T11 electrically couples the complementary bit line BLB to at least one of node Nd1, the source / drain of transistor T4, or the first terminal of capacitor C1.

[0258] The source / drain of transistor T11 is connected to the complementary bit line BLB.

[0259] exist Figure 5 In the process, the drain / source of transistor T11, node Nd1, the source / drain of transistor T4, and the first terminal of capacitor C1 are all coupled to each other.

[0260] exist Figure 5 In this configuration, the source / drain of transistor T11, the complementary bit line BLB, the drain / source of transistor T5, the drain / source of transistor T8, and the source / drain of transistor T1 are all coupled to each other.

[0261] The gate of transistor T12 is used to receive a control signal OC. In some embodiments, the gate of transistor T12 is coupled to the source of the control signal OC. Transistor T12 is enabled or disabled in response to the control signal OC. In some embodiments, when enabled, transistor T12 electrically couples bit line BL to at least one of node ND4, the source / drain of transistor T8, or the first terminal of capacitor C2.

[0262] The source / drain of transistor T12 is coupled to bit line BL.

[0263] exist Figure 5 In this configuration, the drain / source of transistor T12, node ND4, the source / drain of transistor T8, and the first terminal of capacitor C2 are all coupled to each other.

[0264] exist Figure 5 In the transistor T12, the source / drain and bit line BL of transistor T4, the drain / source of transistor T7, and the drain / source of transistor T1 are all coupled to each other.

[0265] In some embodiments, transistors T4 and T5, capacitor C1, inverter I1, and nodes Nd1, Nd2, and Nd3 form part of a first path 250. The first path 250 is coupled between bit line BL and complementary bit line BLB. In some embodiments, the first path 250 further includes transistor T6.

[0266] In some embodiments, transistors T7 and T8, capacitor C2, inverter I2, and nodes Nd4, Nd5, and Nd6 form part of the second path 252. The second path 252 is coupled between bit line BL and complementary bit line BLB. In some embodiments, the second path 252 further includes transistor T9.

[0267] In some embodiments, transistor T11 is a portion of a third path 560. The third path 560 is coupled between node Nd1 and complementary bit line BLB. In some embodiments, the third path 560 includes transistor T11.

[0268] In some embodiments, transistor T12 is a portion of fourth path 562. Fourth path 562 is coupled between node Nd4 and bit line BL. In some embodiments, fourth path 560 includes transistor T12.

[0269] The pre-charge and equalization circuit 504 includes transistors T1, T2, and T3.

[0270] and Figure 2 Compared to the pre-charging and equalization circuit 204, Figure 5 BLEQ signal replaced Figure 2 The signals BLEQ1 and BLEQ2 are omitted, so a similar detailed description is omitted.

[0271] The gates of transistors T1, T2, and T3 are coupled together and used to receive the signal BLEQ. In some embodiments, the signal BLEQ is a precharge signal and an equalization signal.

[0272] In some embodiments, when a low logic value is applied to the signal BLEQ, transistors T1, T2, and T3 are turned on, pulling bit line BL and complementary bit line BLB to the supply voltage VBLEQ. As a result, bit line BL and complementary bit line BLB are pre-charged and equalized to the supply voltage VBLEQ.

[0273] exist Figure 5 In this configuration, the drain / source of transistor T2 is not directly coupled to node Nd1. Figure 5 In the middle, the drain / source of transistor T2 is directly coupled to bit line BL.

[0274] exist Figure 5 In the transistor T2, the source / drain of transistor T10, the drain / drain of transistor T4, the drain / drain of transistor T7, the drain / drain of transistor T1, and each of the bits in BL are coupled to each other.

[0275] exist Figure 5 In this configuration, the drain / source of transistor T3 is not directly coupled to node Nd4. Figure 5 In the process, the drain / source of transistor T3 is directly coupled to the complementary bit line BLB.

[0276] exist Figure 5 In the process, the drain / source of transistor T3, the drain / source of transistor T5, the drain / source of transistor T8, the source / drain of transistor T1, and the complementary bit line BLB are all coupled to each other.

[0277] In some embodiments, by utilizing memory circuitry 500, after time t3a (e.g. Figure 6 The waveform shown in 600 causes the voltage at node Nd5 (e.g., the signal BLB_IN) to be boosted toward the reference voltage VSS to the voltage Vsig.

[0278] In some embodiments, by utilizing memory circuitry 500, after time t3a (e.g. Figure 6As shown in waveform 600, the signal BLB_IN is oriented towards the reference voltage VSS and the boost voltage Vsig, thus increasing the difference between the signal BLB_IN and the signal BL_IN. This improves the accuracy and speed of the read operation performed by the memory circuit 500 and the sense amplifier 502 compared to other methods.

[0279] In some embodiments, the memory circuit 500 is used to perform offset elimination during the bit line development phase, thereby avoiding time penalties due to offset elimination performed by the memory circuit 500, thus improving the speed and accuracy of read operations performed by the memory circuit 500 and the sense amplifier 502 compared to other methods.

[0280] In some embodiments, memory circuitry 500 is used to achieve one or more benefits described herein, including the details discussed herein.

[0281] In some embodiments, by including an isolation transistor T4 between capacitor C1 and bit line BL, by including an isolation transistor T8 between capacitor C2 and complementary bit line BLB, by including a transistor T11 between node Nd1 and complementary bit line BLB, or by including a transistor T12 between node Nd4 and bit line BL, random offsets of the input voltage to memory circuit 500 can be reduced and / or eliminated, while improving the accuracy and speed of one or more read operations performed by memory circuit 500 and / or sense amplifier 502 compared to other methods.

[0282] In some embodiments, by including an isolation transistor T4 between capacitor C1 and bit line BL, or by including an isolation transistor T8 between capacitor C2 and complementary bit line BLB, during a read operation of memory cell SC, the voltage of node Nd2 (signal BL_IN) is boosted to a voltage Vsig, and the voltage of node Nd5 (signal BLB_IN) is negatively boosted to a voltage Vsig, thereby reducing and / or eliminating random offsets in the input voltage of memory circuit 500, while improving the accuracy and speed of one or more read operations performed by memory circuit 500 and / or sense amplifier 502 compared to other methods.

[0283] Other configurations of the memory circuit 500 are also within the scope of this disclosure.

[0284] Figure 6 It is a memory circuit according to some embodiments (such as Figure 5 The waveform timing diagram of the memory circuit 500 in the memory is shown in Figure 600.

[0285] In some embodiments, Figure 6 According to some embodiments Figure 1Timing diagram 600 for memory circuit 100.

[0286] In some embodiments, at least one of memory partitions 102A, 102B, 102C, or 102D is applied. Figure 1 One or more read and / or write operations of the memory bank in at least memory circuit 100, the timing diagram 600 corresponding to the waveforms during the read and write operations in at least one of memory partitions 102A, 102B, 102C, or 102D.

[0287] In some embodiments, for Figure 5 At least one memory cell SC in memory circuit 500 is subjected to one or more read and / or write operations, and timing diagram 600 corresponds to Figure 5 The waveforms during read and / or write operations of the memory cell SC in the memory circuit 500.

[0288] Timing diagram 600 includes the signal BLEQ, word line signal WL', control signal OC, sense amplifier enable signal SAEN, isolation control signal ISO, bit line voltage BL', complementary bit line voltage BLB', signal BL_IN, and the waveform of signal BLB_IN.

[0289] At time t0, signal BLEQ is logic low, word line signal WL' is logic low, control signal OC is logic high, sense amplifier enable signal SAEN is logic low, isolation control signal ISO is logic high, bit line voltage BL' is equal to voltage VBLEQ, complementary bit line voltage BLB' is equal to voltage VBLEQ, signal BL_IN is equal to voltage VBLEQ, and signal BLB_IN is equal to voltage VBLEQ.

[0290] At time t0, in response to the signal BLEQ being logic low, transistors T1, T2, and T3 are turned on.

[0291] At time t0, in response, transistor T1 is turned on. Transistor T1 is used to equalize the voltage of bit line BL and complementary bit line BLB to voltage VVBLEQ.

[0292] At time t0, in response to the isolation control signal ISO being logic high, transistors T4, T5, T7, and T8 are turned on.

[0293] For example, at time t0, in response to transistor T4 turning on, node Nd1 is coupled to bit line BL. For example, at time t0, in response to transistor T2 turning on and node Nd1 being coupled to bit line BL, transistor T2 is used to precharge bit line voltage BL' to voltage VBLEQ.

[0294] For example, at time t0, in response to transistor T8 turning on, node Nd4 is coupled to the complementary bit line BLB. In response to transistor T3 turning on and node Nd4 being coupled to the complementary bit line BLB, transistor T3 is used to precharge the complementary bit line voltage BLB' to voltage VVBLEQ.

[0295] At time t0, in response to the word line signal WL' being logic low, transistor T10 is turned off, and memory cell SC is decoupled from bit line BL.

[0296] At time t0, in response to the control signal OC being logic low, transistor T6 is turned on, thereby electrically coupling nodes Nd2 and Nd3 to each other; transistor T9 is turned on, thereby electrically coupling nodes Nd5 and Nd6 to each other; transistor T11 is turned on, thereby electrically coupling node Nd1 to the complementary bit line BLB to each other; and transistor T12 is turned on, thereby electrically coupling node Nd4 to the bit line BL to each other.

[0297] For example, at time t0, in response to nodes Nd2 and Nd3 being coupled to each other and transistor T5 being turned on, node Nd2 (signal BL_IN) is electrically coupled to the complementary bit line BLB and precharged to voltage VBLEQ.

[0298] For example, at time t0, in response to nodes Nd5 and Nd6 being coupled to each other and transistor T7 being turned on, node Nd5 (signal BLB_IN) is electrically coupled to bit line BL and precharged to voltage VBLEQ.

[0299] At time t0, in response to the sense amplifier enable signal SAEN being low, the inverters I1 and I2 in sense amplifier 202 are turned off.

[0300] exist Figure 6 During the period between time t1 and time t6, a read operation is performed on memory cell SC.

[0301] exist Figure 6 In this context, the period between time t1 and time t3a is called the offset elimination phase of memory circuit 500.

[0302] exist Figure 6 In this context, the period between time t1 and time t3b is referred to as the bit line development stage of memory circuit 500.

[0303] exist Figure 6 In this context, the period between time t3b and time t4 is referred to as the recovery phase of memory circuit 500.

[0304] At time t1, the signal BLEQ, the word line signal WL', and the sense amplifier enable signal SAEN transition from logic low to logic high.

[0305] For example, at time t1, at least in response to the signal BLEQ transitioning from logic low to logic high, transistor T1 is turned off.

[0306] For example, at time t1, at least in response to the signal BLEQ transitioning from logic low to logic high, transistors T2 and T3 are turned off.

[0307] For example, at time t1, at least in response to the word line signal WL' transitioning from logic low to logic high, transistor T10 turns on, thereby coupling bit line BL to memory cell SC. In some embodiments, at time t1, by coupling bit line BL to memory cell SC, data stored in memory cell SC (e.g., Vsig) is transferred to bit line BL, causing bit line voltage BL' to increase by voltage Vsig. In some embodiments, at least between times t1 and t2, bit line voltage BL' is equal to the sum of VBLEQ and Vsig (e.g., VBLEQ + Vsig). In this example, the data stored in memory cell SC (e.g., Vsig) is logic 1. In some embodiments, the data stored in memory cell SC (e.g., Vsig) is logic 0.

[0308] For example, at time t1, in response to the sense amplifier enable signal SAEN transitioning from logic low to logic high, inverters I1 and I2 are turned on. At time t1, in response to inverter I1 being turned on, the signal BL_IN is made equal to the threshold voltage Vth1 of inverter I1. At time t1, in response to inverter I2 being turned on, the signal BLB_IN is made equal to the threshold voltage Vth2 of inverter I2.

[0309] At time t1, the isolation control signal ISO transitions from logic high to logic low. At least in response to the transition of the isolation control signal ISO from logic high to logic low, transistors T4, T5, T7, and T8 are turned off. For example, at time t1, in response to the turn-off of transistors T4 and T7, the corresponding nodes Nd1 and Nd6 are electrically decoupled from bit line BL. For example, at time t1, in response to the turn-off of transistors T5 and T8, the corresponding nodes Nd3 and Nd4 are electrically decoupled from complementary bit line BLB. In some embodiments, at time t1, due to the turn-off of transistors T4, T5, T7, and T8, inverters I1 and I2 are electrically isolated from bit line BL and complementary bit line BLB.

[0310] At time t1, in response to transistor T4 being turned off, node Nd1 is electrically decoupled from bit line BL, but node Nd1 is still electrically coupled to complementary bit line BLB through transistor T11, so that the voltage of node Nd1 is equal to the complementary bit line voltage BLB' (e.g., VBLEQ).

[0311] At time t1, in response to transistor T8 being turned off, node Nd4 is electrically decoupled from the complementary bit line BLB, but node Nd4 is still electrically coupled to bit line BL through transistor T12, so that the voltage of node Nd4 is equal to the bit line voltage BL' (e.g., VBLEQ + Vsig).

[0312] At time t2, the control signal OC and the sense amplifier enable signal SAEN change from logic high to logic low.

[0313] For example, at time t2, at least in response to the sense amplifier enable signal SAEN transitioning from logic high to logic low, inverters I1 and I2 are turned off.

[0314] For example, at time t2, in response to the control signal OC transitioning from logic high to logic low, transistor T6 is turned off, thereby electrically decoupling nodes Nd2 and Nd3 from each other; transistor T9 is turned off, thereby electrically decoupling nodes Nd5 and Nd6 from each other; transistor T11 is turned off, thereby electrically decoupling node Nd1 from complementary bit line BLB from each other; and transistor T12 is turned off, thereby electrically decoupling node Nd4 from bit line BL from each other.

[0315] In some embodiments, at time t2, signals BL_IN and BLB_IN can be stabilized by being electrically isolated from bit line BL and complementary bit line BLB, thus allowing the offset elimination process to be implemented by memory circuit 500.

[0316] In some embodiments, between times t1 and t3a, capacitor C1 is used to store the offset of inverter I1 and capacitor C2 is used to store the offset of inverter I2, thereby allowing memory circuit 500 to take the offset into account and implement the offset elimination process.

[0317] At time t3a, the isolation control signal ISO transitions from logic low to logic high. At least in response to the transition of the isolation control signal ISO from logic low to logic high, transistors T4, T5, T7, and T8 are turned on.

[0318] For example, at time t3a, in response to the conduction of transistors T4 and T7, the corresponding nodes Nd1 and Nd6 are electrically coupled to bit line BL. In some embodiments, at time t3a, by electrically coupling node Nd1 to bit line BL, the voltage of node Nd1 is equal to the bit line voltage BL' (e.g., VBLEQ + Vsig). In some embodiments, at time t3a, the bit line voltage BL' is equal to the sum of voltage VBLEQ and voltage Vsig (VBLEQ + Vsig). Therefore, at time t3a, the voltage of node Nd1 increases by Vsig, thus boosting the signal BL_IN voltage Vsig through capacitor C1. In some embodiments, at time t3a, the signal BL_IN is equal to the sum of voltage Vsig and the threshold voltage Vth1 of inverter I1. In some embodiments, at time t3a, the signal BL_IN is equal to Vth1 + Vsig.

[0319] For example, at time t3a, in response to the conduction of transistors T5 and T8, the corresponding nodes Nd3 and Nd4 are electrically coupled to the complementary bit line BLB. In some embodiments, at time t3a, by electrically coupling node Nd4 to the complementary bit line BLB, the voltage of node Nd4 becomes equal to the complementary bit line voltage BLB'. In some embodiments, at time t3a, the complementary bit line voltage BLB' is equal to the voltage VBLEQ. Between times t2 and t3a, the voltage of node Nd4 is equal to the sum of voltage VBLEQ and voltage Vsig (VBLEQ + Vsig). However, at time t3a, the voltage of node Nd4 decreases by Vsig, thus causing the signal BLB_IN to negatively boost the voltage Vsig through capacitor C2. In some embodiments, at time t3a, the signal BLB_IN is equal to the difference between the threshold voltage Vth2 of inverter I2 and the voltage Vsig. In some embodiments, at time t3a, the signal BLB_IN is equal to Vth2 - Vsig.

[0320] In some embodiments, such as Figure 6 As shown, between at least time t3a and t3b, the differential voltage between signals BLB_IN and BLB_IN is twice the product of voltage Vsig, thereby improving the accuracy and speed of the read operation performed by memory circuit 500 and sense amplifier 502 compared to other methods.

[0321] In some embodiments, with Figure 3 Compared to waveform 300, at least between times t3a and t3b, the differential voltage between signal BLB_IN and signal BLB_IN increases by at least voltage Vsig.

[0322] In some embodiments, at time t3a, due to the conduction of transistors T4, T5, T7, and T8, inverters I1 and I2 are no longer electrically isolated from bit line BL and complementary bit line BLB.

[0323] At time t3a, inverters I1 and I2 are disabled, transistors T6 and T9 are turned off, and the offset elimination process ends.

[0324] Between times t3a and t3b, signals BL_IN and BLB_IN are stable, and inverters I1 and I2 are disabled.

[0325] Between times t3a and t3b, transistors T4, T5, T7, and T8 are turned on, and the sensing amplifier 202 is ready to sense bit line BL.

[0326] At time t3b, the sense amplifier enable signal SAEN transitions from logic low to logic high.

[0327] For example, at time t3b, at least in response to the sense amplifier enable signal SAEN transitioning from logic low to logic high, inverters I1 and I2 are turned on.

[0328] At time t3b, in response to the conduction of inverters I1 and I2, which are used to sense the voltage difference between the bit line voltage BL' and the complementary bit line voltage BLB', the signal BL_IN and the bit line voltage BL' are pulled to the voltage supply VDD, and the signal BLB_IN and the complementary bit line voltage BLB' are pulled to the voltage supply VSS.

[0329] Between times t3b and t4, the bit line voltage BL' is equal to the voltage supply VDD, and during the write-back operation, the bit line voltage BL' is stored as data (e.g., logic 1) into memory cell SC. Figure 6 (Marked as "Restore" in the middle).

[0330] At time t4, the word line signal WL' transitions from logic high to logic low.

[0331] For example, at time t4, at least in response to the word line signal WL' transitioning from logic high to logic low, transistor T10 is turned off, thus decoupling the bit line BL from the memory cell SC.

[0332] At time t5, the sense amplifier enable signal SAEN transitions from logic high to logic low.

[0333] For example, at time t5, in response to the sense amplifier enable signal SAEN transitioning from logic high to logic low, inverters I1 and I2 are turned off.

[0334] At time t5, the control signal OC changes from logic low to logic high.

[0335] For example, at time t5, in response to the control signal OC transitioning from logic low to logic high, transistor T6 turns on, thereby electrically coupling nodes Nd2 and Nd3 to each other; transistor T9 turns on, thereby electrically coupling nodes Nd5 and Nd6 to each other; transistor T11 turns on, thereby electrically coupling node Nd1 to the complementary bit line BLB to each other; and transistor T12 turns on, thereby electrically coupling node Nd4 to the bit line BL to each other.

[0336] In some embodiments, at time t5, by electrically coupling nodes Nd2 and Nd3 to each other, node Nd2 is electrically coupled to the complementary bit line BLB, thereby pulling the signal BL_IN to the complementary bit line voltage BLB' (e.g., VSS).

[0337] In some embodiments, at time t5, node Nd5 is electrically coupled to bit line BL by electrically coupling nodes Nd5 and Nd6 to each other, thus pulling the signal BLB_IN toward bit line voltage BL' (e.g., VDD).

[0338] At time t6, the signal BLEQ changes from logic high to logic low.

[0339] For example, at time t6, in response to the signal BLEQ transitioning from logic high to logic low, transistor T1 turns on, thereby coupling bit line BL to its complementary bit line BLB.

[0340] For example, at time t6, in response to the signal BLEQ transitioning from logic high to logic low, transistors T2 and T3 turn on, thereby coupling the voltage VVBLEQ to nodes Nd1 and Nd4.

[0341] At time t6, transistor T2 is used to precharge the bit line voltage BL' to voltage VBLEQ, thereby pulling the bit line voltage BL' towards voltage VBLEQ.

[0342] At time t6, transistor T3 is used to precharge the complementary bit line voltage BLB' to voltage VBLEQ, thereby pulling the bit line voltage BL' towards voltage VBLEQ.

[0343] In some embodiments, the transition of the control signal OC from logic low to logic high at time t5 occurs at different times. For example, in some embodiments, the transition of the control signal OC from logic low to logic high may occur at time t6 or after time t6.

[0344] In some embodiments, timing diagram 600 enables memory circuitry 500 to achieve one or more benefits described herein, including the details discussed herein.

[0345] Other configurations of timing diagram 600 are also within the scope of this disclosure.

[0346] Figure 7 It is a memory circuit according to some embodiments (such as) Figure 5 The waveform timing diagram of the memory circuit 500 in the memory circuit is shown in Figure 700.

[0347] Timing diagram 700 is Figure 6 A variation of timing diagram 600 is shown, therefore a similar detailed description is omitted. For example, timing diagram 700 illustrates a non-limiting instance, where... Figure 7 The sensing amplifier enable signal SAEN in the middle has a single pulse, while Figure 6 The sensing amplification enable signal SAEN has multiple pulses, so a similar detailed description is omitted.

[0348] In some embodiments, Figure 7 According to some embodiments Figure 1 The timing diagram 700 for the memory circuit 100.

[0349] In some embodiments, at least one of memory partitions 102A, 102B, 102C, or 102D is applied. Figure 1 One or more read and / or write operations of the memory bank in at least memory circuit 100, the timing diagram 700 corresponding to the waveforms during the read and write operations of at least one of memory partitions 102A, 102B, 102C, or 102D.

[0350] In some embodiments, for Figure 5 At least one memory cell SC in the memory circuit 500 is subjected to one or more read operations and / or write operations, and the timing diagram 700 corresponds to Figure 5 The waveforms during read and / or write operations of the memory cell SC in the memory circuit 500.

[0351] Timing diagram 700 includes the waveforms of signal BLEQ, word line signal WL', control signal OC, sense amplifier enable signal SAEN, isolation control signal ISO, bit line voltage BL', complementary bit line voltage BLB', signal BL_IN, and signal BLB_IN.

[0352] At time t0, signal BLEQ is logic low, word line signal WL' is logic low, control signal OC is logic high, sense amplifier enable signal SAEN is logic low, isolation control signal ISO is logic high, bit line voltage BL' is equal to voltage VBLEQ, complementary bit line voltage BLB' is equal to voltage VBLEQ, signal BL_IN is equal to voltage VBLEQ, and signal BLB_IN is equal to voltage VBLEQ.

[0353] exist Figures 6 to 7 In the diagram, from time t0 to time t1, the operation of memory circuit 500 in response to timing diagram 700 is the same as the operation of memory circuit 500 in response to timing diagram 600, therefore a similar detailed description is omitted.

[0354] exist Figure 7 During the period between time t1 and time t6, a read operation is performed on memory cell SC.

[0355] exist Figure 7 In this context, the period between time t2 and time t3b is referred to as the offset elimination phase of memory circuit 500.

[0356] exist Figure 7 In this context, the period between time t1 and time t3b is referred to as the bit line development stage of memory circuit 500.

[0357] exist Figure 7 In this context, the period between time t3b and time t4 is referred to as the recovery phase of memory circuit 500.

[0358] exist Figure 7 At time t1, the signal BLEQ and the word line signal WL' transition from logic low to logic high.

[0359] For example, at time t1, at least in response to the signal BLEQ1 transitioning from logic low to logic high, transistor T1 is turned off.

[0360] For example, at time t1, at least in response to the signal BLEQ transitioning from logic low to logic high, transistors T2 and T3 are turned off.

[0361] For example, at time t1, at least in response to the word line signal WL' transitioning from logic low to logic high, transistor T10 turns on, thereby coupling bit line BL to memory cell SC. In some embodiments, at time t1, by coupling bit line BL to memory cell SC, data stored in memory cell SC (e.g., Vsig) is transferred to bit line BL, causing bit line voltage BL' to increase by voltage Vsig. In some embodiments, at least between times t1 and t2, bit line voltage BL' is equal to the sum of VBLEQ and Vsig (e.g., VBLEQ + Vsig). In this example, the data stored in memory cell SC (e.g., Vsig) is logic 1. In some embodiments, the data stored in memory cell SC (e.g., Vsig) is logic 0.

[0362] exist Figure 7 At time t1, the isolation control signal ISO transitions from logic high to logic low. At least in response to the transition of the isolation control signal ISO from logic high to logic low, transistors T4, T5, T7, and T8 are turned off. For example, at time t1, in response to the turn-off of transistors T4 and T7, the corresponding nodes Nd1 and Nd6 are electrically decoupled from bit line BL. For example, at time t1, in response to the turn-off of transistors T5 and T8, the corresponding nodes Nd3 and Nd4 are electrically decoupled from complementary bit line BLB. For example, at time t1, in response to the turn-off of transistors T4, T5, T7, and T8, inverters I1 and I2 are electrically isolated from bit line BL and complementary bit line BLB.

[0363] At time t1, in response to transistor T4 being turned off, node Nd1 is electrically decoupled from bit line BL, but node Nd1 is still electrically coupled to complementary bit line BLB through transistor T11, so that the voltage of node Nd1 is equal to the complementary bit line voltage BLB' (e.g., VBLEQ).

[0364] At time t1, in response to transistor T8 being turned off, node Nd4 is electrically decoupled from the complementary bit line BLB, but node Nd4 is still electrically coupled to bit line BL through transistor T12, so that the voltage of node Nd4 is equal to the bit line voltage BL' (e.g., VBLEQ + Vsig).

[0365] exist Figure 7 At time t2, the sense amplifier enable signal SAEN changes from logic low to logic high.

[0366] For example, at time t2, in response to the sense amplifier enable signal SAEN transitioning from logic low to logic high, inverters I1 and I2 are turned on. At time t1, in response to inverter I1 turning on, the signal BL_IN is made equal to the threshold voltage Vth1 of inverter I1. At time t1, in response to inverter I2 turning on, the signal BLB_IN is made equal to the threshold voltage Vth2 of inverter I2.

[0367] In some embodiments, in response to the conduction of inverters I1 and I2, the offset cancellation process implemented by memory circuit 200 begins at time t2 and ends at time t3b. In some embodiments, in Figure 7 Between time t2 and t3b, capacitor C1 is used to store the offset of inverter I1, and capacitor C2 is used to store the offset of inverter I2, thus allowing memory circuit 500 to take the offset into account and implement the offset cancellation process.

[0368] exist Figure 7 During the interval between time t2 and t3b, signals BL_IN and BLB_IN can be stabilized by being electrically isolated from bit line BL and complementary bit line BLB, thus allowing the offset elimination process to be implemented through memory circuit 500.

[0369] In some embodiments, Figure 7 At time t2, due to the turn-off of transistors T4, T5, T7, and T8, inverters I1 and I2 are electrically isolated from bit line BL and complementary bit line BLB.

[0370] exist Figure 7 At time t3b, the control signal OC changes from logic high to logic low.

[0371] For example, at time t3b, in response to the control signal OC transitioning from logic high to logic low, transistor T6 is turned off, thereby electrically decoupling nodes Nd2 and Nd3 from each other; and transistor T9 is turned off, thereby electrically decoupling nodes Nd5 and Nd6 from each other; transistor T11 is turned off, thereby electrically decoupling node Nd1 from complementary bit line BLB from each other; and transistor T12 is turned off, thereby electrically decoupling node Nd4 from bit line BL from each other.

[0372] exist Figure 7 At time t3b, the isolation control signal ISO transitions from logic low to logic high. At least in response to the transition of the isolation control signal ISO from logic low to logic high, transistors T4, T5, T7, and T8 are turned on. In some embodiments, in Figure 7 At time t3b, due to the conduction of transistors T4, T5, T7, and T8, inverters I1 and I2 are no longer electrically isolated from bit line BL and complementary bit line BLB.

[0373] For example, in Figure 7 At time t3b, transistors T4 and T7 are turned on, thereby electrically coupling the corresponding nodes Nd1 and Nd6 to bit line BL.

[0374] In some embodiments, Figure 7 At time t3b, by electrically coupling node Nd1 to bit line BL, the voltage of node Nd1 is equal to the bit line voltage BL' (e.g., VBLEQ + Vsig). In some embodiments, in Figure 7 At time t3b, the bit line voltage BL' is equal to the sum of voltage VBLEQ and voltage Vsig (VBLEQ + Vsig). Therefore, at Figure 7 At time t3b, the voltage at node Nd1 increases by Vsig, thus boosting the signal BL_IN through capacitor C1. In some embodiments, at time t3a, the signal BL_IN is equal to the sum of voltage Vsig and the threshold voltage Vth1 of inverter I1. In some embodiments, at... Figure 7 At time t3b, the signal BL_IN is equal to Vth1+Vsig.

[0375] For example, in Figure 7 At time t3b, transistors T5 and T8 are turned on, thereby electrically coupling the corresponding nodes Nd3 and Nd4 to the complementary bit line BLB. In some embodiments, at Figure 7 At time t3b, by electrically coupling node Nd4 to the complementary bit line BLB, the voltage of node Nd4 becomes equal to the complementary bit line voltage BLB'. In some embodiments, in Figure 7 At time t3b, the complementary bit line voltage BLB' equals the voltage VBLEQ. Between times t2 and t3a, the voltage at node Nd4 equals the sum of voltage VBLEQ and voltage Vsig (VBLEQ + Vsig). However, at... Figure 7 At time t3b, the voltage Vsig at node Nd4 decreases, thus causing the signal BLB_IN to be negatively boosted by capacitor C2. In some embodiments, in Figure 7 At time t3b, the signal BLB_IN is equal to the difference between the threshold voltage Vth2 of inverter I2 and the voltage Vsig. In some embodiments, at time t3a, the signal BLB_IN is equal to Vth2 - Vsig.

[0376] However, due to Figure 7At time t3b, inverters I1 and I2 are already turned on. Therefore, once inverters I1 and I2 are no longer electrically isolated from bit line BL and complementary bit line BLB through the isolation control signal ISO, inverters I1 and I2 are used to sense the voltage difference between bit line voltage BL' and complementary bit line voltage BLB'. Figure 7 At time t3b, since inverters I1 and I2 are already turned on, the signal BL_IN and the bit line voltage BL' are pulled to the voltage supply VDD, and the signal BLB_IN and the complementary bit line voltage BLB' are pulled to the voltage supply VSS.

[0377] In some embodiments, such as Figure 7 As shown, between at least time t3a and t3b, the differential voltage between signals BLB_IN and BLB_IN is twice the product of voltage Vsig, thereby improving the accuracy and speed of the read operation performed by memory circuit 500 and sense amplifier 502 compared to other methods.

[0378] In some embodiments, with Figure 3 Compared to waveform 300, at least between times t3a and t3b, the differential voltage between signal BLB_IN and signal BLB_IN increases by at least voltage Vsig.

[0379] In some embodiments, at time t3b, due to the conduction of transistors T4, T5, T7, and T8, inverters I1 and I2 are no longer electrically isolated from bit line BL and complementary bit line BLB.

[0380] At time t3b, inverters I1 and I2 are enabled, transistors T6 and T9 are turned off, and the offset elimination process ends.

[0381] At time t3b, transistors T4, T5, T7, and T8 are turned on, and the sensing amplifier 202 is ready to sense bit line BL.

[0382] Between times t3b and t4, the bit line voltage BL' is equal to the voltage supply VDD, and during the write-back operation, the bit line voltage BL' is stored as data (e.g., logic 1) into memory cell SC. Figure 7 (Marked as "Restore" in the middle).

[0383] In some embodiments, Figure 7 The timing diagram 700 from time t3b to time t4 is shown in Figure 700. Figure 6 The timing diagram 600 from time t3b to time t4 is the same, therefore a similar detailed description is omitted. In some embodiments, Figure 7 The time series diagram 700 from time t4 to time t6 is shown in Figure 700. Figure 6The timing diagram 600 from time t4 to time t6 is the same, therefore a similar detailed description is omitted. In some embodiments, Figure 7 Timing plot 700 after time t6 Figure 6 The timing diagram 600 after time t6 is the same, so a similar detailed description is omitted.

[0384] In some embodiments, Figure 7 and Figure 6 The same timing diagram for the duration causes memory circuit 500 to... Figure 7 and Figure 6 Similar operations within the same duration, with identical timing diagrams, are omitted hereafter in a detailed description.

[0385] In some embodiments, the transition of the control signal OC from logic low to logic high at time t5 occurs at different times. For example, in some embodiments, the transition of the control signal OC from logic low to logic high may occur at time t6 or after time t6.

[0386] In some embodiments, timing diagram 700 enables memory circuitry 200 to achieve one or more benefits described herein, including the details discussed herein.

[0387] Other configurations of timing diagram 700 are also within the scope of this disclosure.

[0388] Figure 8 It is available according to some embodiments. Figure 1 , Figure 2 ,and Figure 5 The circuit diagram of circuit 800.

[0389] In some embodiments, circuit 800 can be used as Figure 2 or Figure 5 At least one of capacitors C1 or C2, therefore a similar detailed description is omitted. In some embodiments, circuit 800 can be used as Figure 2 or Figure 5 The memory cell SC is used, therefore a similar detailed description is omitted. In some embodiments, circuit 800 can be used as... Figure 1 One or more memory units 112 in the memory, therefore a similar detailed description is omitted.

[0390] Circuit 800 includes transistor 802. In some embodiments, transistor 802 is an N-type transistor. In some embodiments, transistor 802 is an NFET. In some embodiments, transistor 802 is an NMOS transistor. Other transistor types or numbers in transistor 802 are also within the scope of this disclosure.

[0391] Transistor 802 is a capacitor-coupled transistor. In some embodiments, transistor 802 is referred to as MOSCAP.

[0392] The source terminal S1 and the drain terminal D1 of transistor 802 are coupled to each other.

[0393] In some embodiments, the source terminal S1 and drain terminal D1 of transistor 802 correspond to at least one of the first terminal of capacitor C1, the first terminal of capacitor C2, or the first terminal of memory cell SC, and the gate terminal G1 of transistor 802 corresponds to at least one of the second terminal of capacitor C1, the second terminal of capacitor C2, or the second terminal of memory cell SC; therefore, similar detailed descriptions are omitted.

[0394] In some embodiments, the source terminal S1 and drain terminal D1 of transistor 802 correspond to at least one of the second terminal of capacitor C1, the second terminal of capacitor C2, or the second terminal of memory cell SC, and the gate terminal G1 of transistor 802 corresponds to at least one of the first terminal of capacitor C1, the first terminal of capacitor C2, or the first terminal of memory cell SC; therefore, similar detailed descriptions are omitted.

[0395] Other configurations of circuit 800 are also within the scope of this disclosure.

[0396] Figures 9A to 9B This is a flowchart of an operation method 900 for an operating circuit according to some embodiments.

[0397] In some embodiments, Figures 9A to 9B It is an operation Figure 1 Memory circuit 100, Figure 2 Memory circuit 200, or Figure 8 The flowchart of the operation method 900 of at least one of the circuits 800 is omitted for simplicity.

[0398] In some embodiments, Figures 9A to 9B This is a flowchart of an operation method 900 for operating the memory circuit. The operation method 900 includes... Figure 3 Timing diagram 300 and Figure 4 The characteristics of timing diagram 400 are omitted for simplicity.

[0399] It should be understood that... Figures 9A to 9B Additional operations are performed before, during, and / or after the operation method 900 shown herein, and only a few of these other operations may be briefly described herein. It should be understood that operation method 900 utilizes… Figure 1 Memory circuit 100, Figure 2 Memory circuit 200, or Figure 8The characteristics of at least one of the circuits 800 are described, and similar detailed descriptions are omitted for simplicity.

[0400] In some embodiments, other orders of operation of the operating method 900 are also within the scope of this disclosure. The operating method 900 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, reordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more of the operations of the operating method 900 are not performed.

[0401] In some embodiments, optionally perform Figures 9A to 9B One or more steps are indicated by the dashed line in the middle.

[0402] In step 902 of operation method 900, the set of signals is received.

[0403] In some embodiments, the set of signals for the operation method 900 includes at least one of the following: word line signal WL', sense amplifier enable signal SAEN, isolation control signal ISO, control signal OC, precharge control signal BLEQ2, or equalization control signal BLEQ1.

[0404] In some embodiments, the character line signal WL' is received by transistor T10.

[0405] In some embodiments, the sense amplifier enable signal SAEN is received by inverters I1 and I2.

[0406] In some embodiments, the isolation control signal ISO is received by transistors T4, T5, T7, and T8.

[0407] In some embodiments, the control signal OC is received by transistors T6 and T9.

[0408] In some embodiments, the precharge control signal BLEQ2 is received by transistors T2 and T3.

[0409] In some embodiments, the equalization control signal BLEQ1 is received by transistor T1.

[0410] In step 904 of operation method 900, in response to the precharge control signal BLEQ2, the voltage of bit line BL and the voltage of complementary bit line BLB are precharged to the precharge voltage by the precharge circuit.

[0411] In some embodiments, the voltage of bit line BL in operating method 900 or 1000 includes at least bit line voltage BL'. In some embodiments, the voltage of complementary bit line BLB in operating method 900 includes at least complementary bit line voltage BLB'. In some embodiments, the pre-charge voltage of operating method 900 or 1000 includes at least voltage VBLEQ.

[0412] In some embodiments, the pre-charge circuit of the operation method 900 includes at least a pre-charge and equalization circuit 204. In some embodiments, the pre-charge circuit of the operation method 900 includes at least one of transistors T2 or T3.

[0413] In some embodiments, the pre-charge circuit of the operation method 900 is used to charge the battery. Figure 2 Nodes Nd1 and Nd4 are precharged to the precharge voltage.

[0414] In step 906 of operation method 900, in response to the equalization control signal BLEQ1, the voltage of the bit line and the voltage of the complementary bit line are equalized by the equalization circuit.

[0415] In some embodiments, the equalization circuit of the operating method 900 includes at least a pre-charge and equalization circuit 204. In some embodiments, the equalization circuit of the operating method 900 includes at least one of transistors T1. In some embodiments, the equalization circuit is coupled between a bit line and a complementary bit line.

[0416] In step 908 of operation method 900, in response to word line signal WL', memory cell SC is coupled to bit line via channel gate transistor.

[0417] In some embodiments, step 908 of the operating method 900 or 1000 further includes reading data stored in the memory cell to a bit line, thereby increasing or adjusting the voltage of the bit line to correspond to the signal voltage of the data stored in the memory cell.

[0418] In some embodiments, the channel gate transistor of operating method 900 or 1000 includes at least transistor T10.

[0419] In some embodiments, the signal voltage of operating method 900 or 1000 includes at least voltage Vsig.

[0420] In step 910 of the operation method 900, the set of isolation transistors is disabled in response to the isolation control signal ISO, thereby electrically isolating / decoupling the sense amplifier from the bit line and complementary bit line.

[0421] In some embodiments, the set of isolation transistors in operating method 900 or 1000 includes at least one of transistors T4, T5, T7, or T8.

[0422] In some embodiments, the sensing amplifier of the operating method 900 includes at least a sensing amplifier 202.

[0423] In some embodiments, the sensing amplifier of operating method 900 or 1000 includes a first path 250 and a second path 252. In some embodiments, the first path 250 includes a first node (e.g., node Nd1), a second node (e.g., node Nd2), and a third node (e.g., node Nd3). In some embodiments, the second path 252 includes a fourth node (e.g., node Nd4), a fifth node (e.g., node Nd5), and a sixth node (e.g., node Nd6).

[0424] In some embodiments, step 910 includes step 910a.

[0425] In step 910a of the operation method 900, the set of isolation transistors is disabled in response to the isolation control signal ISO, thereby decoupling the first node (e.g., node Nd1) and the sixth node (e.g., node Nd6) from the bit line, and thereby decoupling the third node (e.g., node Nd3) and the fourth node (e.g., node Nd4) from the complementary bit line.

[0426] In step 912 of the operation method 900, the first inverter and the second inverter are enabled in response to the sense amplifier enable signal, thereby setting the voltage BL_IN of the second node (e.g., node Nd2) to the first threshold voltage of the first inverter and setting the voltage BLB_IN of the fifth node (e.g., node Nd5) to the second threshold voltage of the second inverter.

[0427] In some embodiments, the first inverter in operation method 900 or 1000 includes one of inverters I1 or I2, and the second inverter in operation method 900 or 1000 includes the other of inverters I2 or I1.

[0428] In some embodiments, the first threshold voltage of the first inverter in operating method 900 or 1000 includes one of the threshold voltages Vth1 or Vth2, and the second threshold voltage of the second inverter in operating methods 900 and 1000 includes the other of the threshold voltages Vth2 or Vth1.

[0429] In some embodiments, the first inverter and the second inverter in the operation method 900 are part of the sensing amplifier 202.

[0430] In some embodiments, step 912 occurs Figure 3 At time t1 or Figure 4 At time t2 in the middle.

[0431] In step 914 of operation method 900, the first transistor and the second transistor are disabled in response to the control signal OC.

[0432] In some embodiments, the first transistor is coupled in parallel with the first inverter, and the second transistor is coupled in parallel with the second inverter.

[0433] In some embodiments, the first transistor in operation method 900 or 1000 includes transistor T6.

[0434] In some embodiments, the second transistor in operation method 900 or 1000 includes transistor T9.

[0435] In step 916 of operation method 900, the first inverter and the second inverter are disabled in response to the sense amplifier enable signal SAEN.

[0436] In some embodiments, step 916 occurs Figure 3 At time t2 in the middle.

[0437] In step 918 of the operation method 900, the set of isolation transistors is enabled in response to the isolation control signal ISO, thereby electrically coupling the sense amplifier to the bit line and the complementary bit line, and thereby increasing the voltage BL_IN of the second node (e.g., node Nd2) by the signal voltage.

[0438] In step 920 of operation method 900, the difference between the voltage of the bit line and the voltage of the complementary bit line is sensed by a sensing amplifier.

[0439] In some embodiments, step 920 of operating method 900 or 1000 further includes step 922a or 922b.

[0440] In some embodiments, when the memory circuit 200 is used to utilize Figure 3 When the timing diagram is 300, step 920 of operation method 900 further includes step 922a, therefore a similar detailed description is omitted.

[0441] In some embodiments, when the memory circuit 200 is used to utilize Figure 4 When the timing diagram is 400, step 920 of operation method 900 further includes step 922b, therefore a similar detailed description is omitted.

[0442] In step 922a of operation method 900, the first inverter and the second inverter are activated in response to the sense amplifier enable signal SAEN, thereby pulling the voltage BL_IN of the second node (e.g., node Nd2) and the voltage of the bit line to the first supply voltage (e.g., supply voltage VDD), and thereby pulling the voltage BL2_IN of the fifth node (e.g., node Nd5) and the voltage of the complementary bit line to the reference supply voltage (e.g., reference supply voltage VSS).

[0443] In some embodiments, step 922a occurs Figure 3 At time t3b in the middle.

[0444] In step 922b of operation method 900, the voltage BL_IN of the second node (e.g., node Nd2) and the voltage of the bit line are pulled to the first supply voltage (e.g., supply voltage VDD), and the voltage BL2_IN of the fifth node (e.g., node Nd5) and the voltage of the complementary bit line are pulled to the reference supply voltage (e.g., reference supply voltage VSS).

[0445] In some embodiments, step 922b occurs Figure 4 At time t3a.

[0446] In step 924 of operation method 900, a recovery operation of memory cell SC is performed in response to word line signal WL'.

[0447] In some embodiments, the recovery operation of memory cell SC in operation method 900 or 1000 includes a write-back operation between time t3b and T4 (in Figure 3 , Figure 6 ,and Figure 7 In the process marked "Restore", the voltage supply VDD is written back to the memory cell SC.

[0448] In some embodiments, the recovery operation of memory cell SC in operation method 900 or 1000 includes a write-back operation between time t3a and T4 (in Figure 4 In the process marked "Restore", the voltage supply VDD is written back to the memory cell SC.

[0449] In step 926 of operation method 900, the first transistor and the second transistor are enabled in response to the control signal OC.

[0450] In step 928 of operation method 900, the first inverter and the second inverter are disabled in response to the sense amplifier enable signal SAEN.

[0451] In some embodiments, after step 928, operation method 900 returns to steps 904 and / or 906.

[0452] In some embodiments, although operation method 900 is described with respect to timing diagram 300 applied to memory circuit 200, operation method 900 also utilizes timing diagram 400 applied to memory circuit 200 in a similar manner (details omitted for simplicity), but does not perform one or more of the operations in operation method 900. For example, in these embodiments, when operation method 900 utilizes timing diagram 400 applied to memory circuit 200, operation method 900 includes one or more of steps 902, 904, 906, 908, 910, 910a, 912, 914, 918, 920, 922b, 924, 926, or 928, and similar detailed descriptions are omitted for simplicity.

[0453] Figures 10A to 10B This is a flowchart of an operation method 1000 for an operating circuit according to some embodiments.

[0454] In some embodiments, Figures 10A to 10B It is an operation Figure 1 Memory circuit 100, Figure 5 Memory circuit 500, or Figure 8 The flowchart of the operation method 1000 of at least one of the circuits 800 is omitted for simplicity.

[0455] In some embodiments, Figures 10A to 10B This is a flowchart of an operation method 1000 for operating the memory circuit. The operation method 1000 includes... Figure 6 Timing diagram 600 and Figure 7 The characteristics of timing diagram 700 are omitted for simplicity.

[0456] It should be understood that, Figures 10A to 10B Additional operations may be performed before, during, and / or after the operation method 1000 shown herein, and only a few of these additional operations may be briefly described herein. It should be understood that operation method 1000 utilizes… Figure 1 Memory circuit 100, Figure 5 Memory circuit 500, or Figure 8 The characteristics of at least one of the circuits 800 are described, and similar detailed descriptions are omitted for simplicity.

[0457] In some embodiments, other orders of operation of operating method 1000 are also within the scope of this disclosure. Operating method 1000 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, reordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more of the operations of operating method 1000 are not performed.

[0458] In some embodiments, optionally perform Figures 10A to 10B One or more operations are indicated by the dashed line.

[0459] In some embodiments, one or more operations in operation method 1000 include one or more operations from operation method 900, and similar detailed descriptions are omitted for simplicity.

[0460] In step 1002 of operation method 1000, the set of signals is received.

[0461] In some embodiments, the set of signals for operating method 1000 includes at least one of the following: word line signal WL', sense amplifier enable signal SAEN, isolation control signal ISO, control signal OC, or precharge and equalization control signal BLEQ.

[0462] In some embodiments, the character line signal WL' is received by transistor T10.

[0463] In some embodiments, the sense amplifier enable signal SAEN is received by inverters I1 and I2.

[0464] In some embodiments, the isolation control signal ISO is received by transistors T4, T5, T7, and T8.

[0465] In some embodiments, the control signal OC is received by transistors T6, T9, T11, and T12.

[0466] In some embodiments, the precharge and equalization control signal BLEQ1 is received by transistors T1, T2, and T3.

[0467] In step 1004 of operation method 1000, in response to the precharge and equalization control signal BLEQ, the voltage of bit line BL and the voltage of complementary bit line BLB are precharged to the precharge voltage by the precharge circuit.

[0468] In some embodiments, the voltage of bit line BL in operating method 900 or 1000 includes at least bit line voltage BL'. In some embodiments, the voltage of complementary bit line BLB in operating method 900 includes at least complementary bit line voltage BLB'. In some embodiments, the pre-charge voltage of operating method 900 or 1000 includes at least voltage VBLEQ.

[0469] In some embodiments, the pre-charge circuit of the operating method 1000 includes at least a pre-charge and equalization circuit 504. In some embodiments, the pre-charge circuit of the operating method 1000 includes at least one of transistors T2 or T3.

[0470] In step 1006 of operation method 1000, in response to the pre-charge and equalization control signal BLEQ, the voltage of the bit line and the voltage of the complementary bit line are equalized by the equalization circuit.

[0471] In some embodiments, the equalization circuit of the operating method 1000 includes at least a pre-charging and equalization circuit 504. In some embodiments, the equalization circuit of the operating method 1000 includes at least one of transistors T1.

[0472] In step 908 of operation method 1000, in response to the word line signal WL', the memory cell SC is coupled to the bit line through a channel gate transistor.

[0473] In step 910 of operation method 1000, the set of isolation transistors is disabled in response to the isolation control signal ISO, thereby electrically isolating / decoupling the sense amplifier from the bit line and complementary bit line.

[0474] In some embodiments, the sensing amplifier of the operating method 1000 includes at least a sensing amplifier 502.

[0475] In some embodiments, step 910 includes step 910a.

[0476] In step 910a of operation method 1000, the set of isolation transistors is disabled in response to the isolation control signal ISO, thereby decoupling the first node (e.g., node Nd1) and the sixth node (e.g., node Nd6) from the bit line, and thereby decoupling the third node (e.g., node Nd3) and the fourth node (e.g., node Nd4) from the complementary bit line.

[0477] In step 912 of operation method 1000, the first inverter and the second inverter are enabled in response to the sense amplifier enable signal, thereby setting the voltage BL_IN of the second node (e.g., node Nd2) to the first threshold voltage of the first inverter, and thereby setting the voltage BL2_IN of the fifth node (e.g., node Nd5) to the second threshold voltage of the second inverter.

[0478] In some embodiments, the first inverter and the second inverter of the operation method 1000 are part of the sensing amplifier 502.

[0479] In some embodiments, step 912 occurs Figure 6 At time t1 or Figure 7 At time t2 in the middle.

[0480] In step 914 of operation method 1000, the first transistor and the second transistor are disabled in response to the control signal OC.

[0481] In some embodiments, the first transistor is coupled in parallel with the first inverter, and the second transistor is coupled in parallel with the second inverter.

[0482] In some embodiments, the first transistor in operation method 900 or 1000 includes transistor T6.

[0483] In some embodiments, the second transistor in operation method 900 or 1000 includes transistor T9.

[0484] In step 1014 of operation method 1000, the third transistor and the fourth transistor are disabled in response to the control signal OC.

[0485] In some embodiments, step 1014 further includes decoupling the first node from the complementary bit line and decoupling the fourth node from the bit line. In some embodiments, the third transistor is coupled between the first node and the complementary bit line. In some embodiments, the fourth transistor is coupled between the fourth node and the bit line.

[0486] In some embodiments, the third transistor in the operation method 1000 includes transistor T11.

[0487] In some embodiments, the fourth transistor in the operation method 1000 includes transistor T12.

[0488] In some embodiments, step 1014 occurs Figure 6 At time t2 or Figure 7 At time t3b in the middle.

[0489] In step 916 of operation method 1000, the first inverter and the second inverter are disabled in response to the sense amplifier enable signal SAEN.

[0490] In some embodiments, step 916 occurs Figure 6 At time t2 in the middle.

[0491] In step 918 of operation method 1000, the set of isolation transistors is enabled in response to the isolation control signal ISO, thereby electrically coupling the sense amplifier to the bit line and the complementary bit line, thereby increasing the voltage BL_IN of the second node (e.g., node Nd2) to the signal voltage and thereby decreasing the voltage BL2_IN of the fifth node (e.g., node Nd5) to the signal voltage.

[0492] In step 920 of operation method 1000, the difference between the voltage of the bit line and the voltage of the complementary bit line is sensed by a sensing amplifier.

[0493] In some embodiments, step 920 of the operation method 1000 further includes step 922a or 922b.

[0494] In some embodiments, when the memory circuit 500 is used to utilize Figure 6 When the timing diagram is 600, step 920 of operation method 1000 further includes step 922a, therefore a similar detailed description is omitted.

[0495] In some embodiments, when the memory circuit 500 is used to utilize Figure 7 In timing diagram 700, step 920 of operation method 1000 further includes step 922b, therefore a similar detailed description is omitted.

[0496] In step 922a of operation method 1000, the first inverter and the second inverter are enabled in response to the sense amplifier enable signal SAEN, thereby pulling the voltage BL_IN of the second node (e.g., node Nd2) and the voltage of the bit line to the first supply voltage (e.g., supply voltage VDD), and thereby pulling the voltage BL2_IN of the fifth node (e.g., node Nd5) and the voltage of the complementary bit line to the reference supply voltage (e.g., reference supply voltage VSS).

[0497] In some embodiments, step 922a occurs Figure 6 At time t3b in the middle.

[0498] In step 922b of operation method 1000, the voltage BL_IN of the second node (e.g., node Nd2) and the voltage of the bit line are pulled to the first supply voltage (e.g., supply voltage VDD), and the voltage BL2_IN of the fifth node (e.g., node Nd5) and the voltage of the complementary bit line are pulled to the reference supply voltage (e.g., reference supply voltage VSS).

[0499] In some embodiments, step 922b occurs Figure 7 At time t3a.

[0500] In step 924 of operation method 1000, a recovery operation of memory cell SC is performed in response to word line signal WL'.

[0501] In some embodiments, the recovery operation of memory cell SC in operation method 900 or 1000 includes a write-back operation between time t3b and T4 (in Figure 3 , Figure 6 ,and Figure 7 In the process marked "Restore", the voltage supply VDD is written back to the memory cell SC.

[0502] In some embodiments, the recovery operation of memory cell SC in operation method 900 or 1000 includes a write-back operation between time t3a and T4 (in Figure 4In the process marked "Restore", the voltage supply VDD is written back to the memory cell SC.

[0503] In step 926 of operation method 1000, the first transistor and the second transistor are enabled in response to the control signal OC.

[0504] In step 1026 of operation method 1000, the third transistor and the fourth transistor are enabled in response to the control signal OC.

[0505] In some embodiments, step 1026 further includes coupling the first node to the complementary bit line and coupling the fourth node to the bit line.

[0506] In step 928 of operation method 1000, the first inverter and the second inverter are disabled in response to the sense amplifier enable signal SAEN.

[0507] In some embodiments, after step 928, operation method 1000 returns to steps 1004 and / or 1006.

[0508] In some embodiments, although operation method 1000 is described with respect to timing diagram 600 applied to memory circuit 500, operation method 1000 also utilizes timing diagram 700 applied to memory circuit 500 in a similar manner (not described further for simplicity), but does not perform one or more operations of operation method 1000. For example, in these embodiments, when operation method 1000 utilizes timing diagram 700 applied to memory circuit 500, operation method 1000 includes one or more of steps 1002, 1004, 1006, 908, 910, 910a, 912, 914, 1014, 1018, 920, 922b, 924, 926, 1026, or 928, and similar detailed descriptions are omitted for simplicity.

[0509] By operating method 900 or 1000, memory circuits 100, 200, or 500 are used to achieve one or more of the benefits discussed herein.

[0510] In some embodiments, one or more of the operations in operation methods 900 or 1000 are not performed. Furthermore, for illustrative purposes, Figure 2 , Figure 5 ,and Figure 8 The various PMOS or NMOS transistors shown have specific dopant types (e.g., N-type or P-type). The embodiments disclosed herein are not limited to specific transistor types. Figure 2 , Figure 5 ,and Figure 8One or more of the PMOS or NMOS transistors shown can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. The embodiments disclosed herein are not limited to specific logic values ​​when signals are enabled and / or disabled. Choosing different logic values ​​is also within the scope of the various embodiments. Figure 2 , Figure 5 ,and Figure 8 Choosing different numbers of inverters is also within the scope of various embodiments. Figure 2 , Figure 5 ,and Figure 8 Different numbers of transistors are also within the scope of various embodiments.

[0511] Those skilled in the art will readily see that one or more of the disclosed embodiments satisfy one or more of the advantages set forth above. After reading the foregoing specification, those skilled in the art will be able to influence the various variations, equivalent substitutions, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only to the definitions contained in the appended claims and their equivalents.

[0512] One aspect of this specification relates to a memory circuit. In some embodiments, the memory circuit includes memory cells, bit lines, complementary bit lines, and channel gate transistors coupled to the memory cells and bit lines. In some embodiments, the memory circuit further includes a sense amplifier coupled to the bit lines, complementary bit lines, and channel gate transistors. In some embodiments, the sense amplifier includes a first path between the bit lines and the complementary bit lines. In some embodiments, the first path includes a first isolation transistor for receiving an isolation control signal and coupled between the bit lines and a first node. In some embodiments, the first path further includes a first inverter for receiving a sense amplifier enable signal and coupled between a second node and a third node. In some embodiments, the memory circuit further includes a precharge circuit coupled to the first node and for precharging the first node to a precharge voltage in response to a precharge control signal.

[0513] In some embodiments, the first path further includes: a first capacitor coupled between the first node and the second node; and a second isolation transistor for receiving the isolation control signal and coupled between the third node and the complementary bit line.

[0514] In some embodiments, the sense amplifier further includes: a second path between the bit line and the complementary bit line, the second path including: a third isolation transistor for receiving the isolation control signal and coupled between the complementary bit line and a fourth node; and a second inverter for receiving the sense amplifier enable signal and coupled between a fifth node and a sixth node, wherein the precharge circuit is further coupled to the fourth node and further configured to precharge the fourth node to the precharge voltage in response to the precharge control signal.

[0515] In some embodiments, the second path further includes: a second capacitor coupled between the fourth node and the fifth node; and a fourth isolation transistor for receiving the isolation control signal and coupled between the sixth node and the bit line.

[0516] In some embodiments, the sensing amplifier further includes: a first transistor for receiving a control signal, coupled in parallel with the first inverter, and located between the second node and the third node; and a second transistor for receiving the control signal, coupled in parallel with the second inverter, and located between the fifth node and the sixth node.

[0517] In some embodiments, the pre-charge circuit includes: a first P-type transistor comprising: a first terminal of the first P-type transistor for receiving the pre-charge control signal; a second terminal of the first P-type transistor coupled to the first node, the first isolation transistor, and the first capacitor; and a third terminal of the first P-type transistor coupled to the pre-charge voltage; and a second P-type transistor comprising: a first terminal of the second P-type transistor for receiving the pre-charge control signal; a second terminal of the second P-type transistor coupled to the fourth node, the third isolation transistor, and the second capacitor; and a third terminal of the second P-type transistor coupled to the pre-charge voltage and the third terminal of the first P-type transistor.

[0518] In some embodiments, the memory circuit further includes: an equalization circuit for equalizing a voltage of the bit line and a voltage of the complementary bit line in response to an equalization control signal, the equalization circuit being coupled between the bit line and the complementary bit line.

[0519] In some embodiments, the equalization circuit includes: a first P-type transistor, comprising: a first terminal of the first P-type transistor for receiving the equalization control signal; a second terminal of the first P-type transistor coupled to the bit line; and a third terminal of the first P-type transistor coupled to the complementary bit line.

[0520] In some embodiments, the memory cell includes a capacitor coupled between the channel gate transistor and a reference voltage supply.

[0521] Another aspect of this specification relates to memory circuitry. In some embodiments, the memory circuitry includes memory cells, bit lines, complementary bit lines, word lines, and channel gate transistors (GMTs) for receiving word line signals and coupled to the word lines, memory cells, and bit lines. In some embodiments, the memory circuitry further includes a sense amplifier coupled to the bit lines, complementary bit lines, and the GMTs. In some embodiments, the sense amplifier includes a first path between the bit lines and the complementary bit lines. In some embodiments, the first path includes a first isolation transistor for receiving an isolation control signal and coupled between the bit lines and a first node. In some embodiments, the first path further includes a first inverter for receiving a sense amplifier enable signal and coupled between a second node and a third node. In some embodiments, the sense amplifier further includes a second path between the first node and the complementary bit lines. In some embodiments, the second path includes a first transistor for receiving a control signal and coupled between the first node and the complementary bit lines. In some embodiments, the memory circuitry further includes a precharge and equalization circuitry coupled to the bit lines and complementary bit lines, and configured to precharge the voltages of the bit lines and complementary bit lines to a precharge voltage in response to a precharge / equalization control signal.

[0522] In some embodiments, the first path further includes: a first capacitor coupled between the first node and the second node; and a second isolation transistor for receiving the isolation control signal and coupled between the third node and the complementary bit line.

[0523] In some embodiments, the sense amplifier further includes: a third path between the bit line and the complementary bit line, the third path including: a third isolation transistor for receiving the isolation control signal and coupled between the complementary bit line and a fourth node; a second inverter for receiving the sense amplifier enable signal and coupled between a fifth node and a sixth node; a second capacitor coupled between the fourth node and the fifth node; and a fourth isolation transistor for receiving the isolation control signal and coupled between the sixth node and the bit line.

[0524] In some embodiments, the sense amplifier further includes a fourth path between the fourth node and the bit line, the fourth path including a second transistor for receiving the control signal and coupled between the fourth node and the bit line.

[0525] In some embodiments, the sensing amplifier further includes: a third transistor for receiving the control signal, coupled in parallel with the first inverter, and located between the second node and the third node; and a fourth transistor for receiving the control signal, coupled in parallel with the second inverter, and located between the fifth node and the sixth node.

[0526] In some embodiments, the precharge and equalization circuit includes: a first P-type transistor comprising: a first terminal of the first P-type transistor for receiving the precharge / equalization control signal; a second terminal of the first P-type transistor coupled to the bit line; and a third terminal of the first P-type transistor coupled to the precharge voltage; and a second P-type transistor comprising: a first terminal of the second P-type transistor for receiving the precharge / equalization control signal; a second terminal of the second P-type transistor coupled to the complementary bit line; and a third terminal of the second P-type transistor coupled to the precharge voltage and the third terminal of the first P-type transistor.

[0527] In some embodiments, the precharge and equalization circuit is further configured to equalize the voltage of the bit line and the complementary bit line in response to the precharge / equalization control signal.

[0528] In some embodiments, the precharge and equalization circuit further includes: a third P-type transistor, comprising: a first terminal of the third P-type transistor for receiving the precharge / equalization control signal; a second terminal of the third P-type transistor coupled to the bit line; and a third terminal of the third P-type transistor coupled to the complementary bit line.

[0529] Another aspect of this specification relates to a method of operating a memory circuit. In some embodiments, the method of operation includes precharging the voltages of a bit line and a complementary bit line to a precharge voltage via a precharge circuit in response to a precharge control signal. In some embodiments, the method of operation further includes coupling a memory cell to a bit line via a channel gate transistor in response to a word line signal, thereby reading data stored in the memory cell to the bit line, thus increasing the voltage of the bit line by a signal voltage corresponding to the data stored in the memory cell. In some embodiments, the method of operation further includes disabling a set of isolation transistors in response to an isolation control signal, thereby electrically decoupling a sense amplifier from the bit line and the complementary bit line, the sense amplifier including a first path and a second path, the first path including a first node, a second node, and a third node, and the second path including a fourth node, a fifth node, and a sixth node. In some embodiments, the operation method further includes activating a first inverter and a second inverter in response to a sense amplifier enable signal, thereby setting the voltage of the second node to a first threshold voltage of the first inverter and thereby setting the voltage of the fifth node to a second threshold voltage of the second inverter, wherein the first inverter and the second inverter are part of the sense amplifier. In some embodiments, the operation method further includes disabling a first transistor and a second transistor in response to a control signal, wherein the first transistor is coupled in parallel with the first inverter and the second transistor is coupled in parallel with the second inverter. In some embodiments, the operation method further includes disabling the first inverter and the second inverter in response to a sense amplifier enable signal. In some embodiments, the operation method further includes activating a set of isolation transistors in response to an isolation control signal, thereby electrically coupling the sense amplifier to a bit line and a complementary bit line, thereby increasing the voltage of the second node by a signal voltage. In some embodiments, the operation method further includes the difference between the voltage of the sense bit line and the voltage of the complementary bit line.

[0530] In some embodiments, the step of disabling the set of multiple isolation transistors in response to the isolation control signal to electrically decouple the sense amplifier from the bit line and the complementary bit line includes the steps of: electrically decoupling the first node and the sixth node from the bit line, and electrically decoupling the third node and the fourth node from the complementary bit line; the step of sensing the difference between the voltage of the bit line and the voltage of the complementary bit line includes the steps of: activating the first inverter and the second inverter in response to the sense amplifier enable signal to pull the voltage of the second node and the voltage of the bit line to a first supply voltage, and to pull the voltage of the fifth node and the voltage of the complementary bit line to a reference supply voltage.

[0531] In some embodiments, the operation method further includes the following steps: performing a recovery operation of the memory cell in response to the word line signal; enabling the first transistor and the second transistor in response to the control signal; and disabling the first inverter and the second inverter in response to the sense amplifier enable signal.

[0532] Another aspect of this specification relates to a memory circuit. This memory circuit includes: memory cells, bit lines, complementary bit lines, word lines, channel gate transistors, a sense amplifier, and a precharge circuit. The channel gate transistor is coupled to the word lines, memory cells, and bit lines to receive word line signals, thereby reading data stored in the memory cells to the bit lines, thus increasing the voltage of the bit lines by a signal voltage corresponding to the data stored in the memory cells. The sense amplifier is coupled to the bit lines, complementary bit lines, and the channel gate transistor. The sense amplifier includes: a first path, a second path, a first transistor, and a second transistor. The first path is between the bit lines and the complementary bit lines. The first path includes: a first isolation transistor for receiving an isolation control signal and coupled between the bit lines and a first node, and for decoupling the sense amplifier from the bit lines or electrically coupling the sense amplifier to the bit lines according to the isolation control signal; and a first inverter for receiving a sense amplifier enable signal and coupled between a second node and a third node. The voltage of the second node is set to the first threshold voltage of the first inverter. A second path is established between the first node and the complementary bit line. The second path includes: a second isolation transistor for receiving an isolation control signal and coupled between the complementary bit line and the fourth node, and for electrically decoupling or coupling the sense amplifier to the complementary bit line according to the isolation control signal; and a second inverter for receiving a sense amplifier enable signal and coupled between the fifth and sixth nodes. The voltage of the fifth node is set to the second threshold voltage of the second inverter. A first transistor for receiving a control signal is coupled in parallel with the first inverter. A second transistor for receiving a control signal is coupled in parallel with the second inverter. A precharge circuit is coupled to the bit line and the complementary bit line and, in response to the precharge control signal, precharges the voltages of the bit line and the complementary bit line to a precharge voltage.

[0533] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory circuit, characterized in that, Include: One memory unit; One-yuan line; One complementary bit line; A gate transistor is coupled to the memory cell and the bit line; A sense amplifier coupled to the bit line, the complementary bit line, and the channel gate transistor, the sense amplifier comprising: A first path, between the bit line and the complementary bit line, the first path comprising: A first isolation transistor, which receives an isolation control signal and is coupled between the bit line and a first node; and A first inverter, which receives a sense amplifier enable signal and is coupled between a second node and a third node; as well as A pre-charge circuit is coupled to the first node and is used to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal.

2. The memory circuit as described in claim 1, characterized in that, This first path further includes: A first capacitor, coupled between the first node and the second node; and A second isolation transistor is used to receive the isolation control signal and is coupled between the third node and the complementary bit line.

3. The memory circuit as described in claim 2, characterized in that, The sensing amplifier further includes: A second path, between the bit line and the complementary bit line, the second path comprising: A third isolation transistor, which receives the isolation control signal and is coupled between the complementary bit line and a fourth node; and A second inverter, which receives the enable signal of the sense amplifier, is coupled between a fifth node and a sixth node. The pre-charge circuit is further coupled to the fourth node and is used to pre-charge the fourth node to the pre-charge voltage in response to the pre-charge control signal.

4. The memory circuit as described in claim 3, characterized in that, The second path further includes: A second capacitor, coupled between the fourth node and the fifth node; and A fourth isolation transistor is used to receive the isolation control signal and is coupled between the sixth node and the bit line.

5. The memory circuit as described in claim 4, characterized in that, The sensing amplifier further includes: A first transistor, used to receive a control signal, is coupled in parallel with the first inverter and is located between the second node and the third node; and A second transistor, which receives the control signal, is coupled in parallel with the second inverter and is located between the fifth node and the sixth node.

6. The memory circuit as described in claim 4, characterized in that, The pre-charge circuit includes: A first P-type transistor, comprising: A first terminal of the first P-type transistor is used to receive the precharge control signal; A second terminal of the first P-type transistor is coupled to the first node, the first isolation transistor, and the first capacitor; as well as A third terminal of the first P-type transistor is coupled to the pre-charge voltage; as well as A second P-type transistor, comprising: A first terminal of the second P-type transistor is used to receive the precharge control signal; A second terminal of the second P-type transistor is coupled to the fourth node, the third isolation transistor, and the second capacitor; as well as A third terminal of the second P-type transistor is coupled to the precharge voltage and the third terminal of the first P-type transistor.

7. The memory circuit as described in claim 1, characterized in that, The memory circuitry further includes: An equalization circuit is used to equalize a voltage of the bit line and a voltage of the complementary bit line in response to an equalization control signal. The equalization circuit is coupled between the bit line and the complementary bit line.

8. The memory circuit as described in claim 7, characterized in that, The equalization circuit includes: A first P-type transistor, comprising: A first terminal of the first P-type transistor is used to receive the equalization control signal; A second terminal of the first P-type transistor is coupled to the bit line; as well as A third terminal of the first P-type transistor is coupled to the complementary bit line.

9. A memory circuit, characterized in that, Include: One memory unit; One-yuan line; One complementary bit line; One-character line; A gate transistor is used to receive a word line signal and is coupled to the word line, the memory cell, and the bit line. A sense amplifier coupled to the bit line, the complementary bit line, and the channel gate transistor, the sense amplifier comprising: A first path, between the bit line and the complementary bit line, the first path comprising: A first isolation transistor, which receives an isolation control signal and is coupled between the bit line and a first node; and A first inverter, which receives a sense amplifier enable signal and is coupled between a second node and a third node; and A second path, between the first node and the complementary bit line, the second path comprising: A first transistor for receiving a control signal and coupled between the first node and the complementary bit line; and A pre-charge and equalization circuit is coupled to the bit line and the complementary bit line and is used to pre-charge a voltage of the bit line and the complementary bit line to a pre-charge voltage in response to a pre-charge / equalization control signal.

10. A memory circuit, characterized in that, Include: One memory unit; One-yuan line; One complementary bit line; One-character line; A gate transistor is coupled to the word line, the memory cell and the bit line to receive a word line signal, thereby reading a data stored in the memory cell to the bit line, and thus increasing the voltage of the bit line by a signal voltage corresponding to the data stored in the memory cell. A sense amplifier coupled to the bit line, the complementary bit line, and the channel gate transistor, the sense amplifier comprising: A first path, between the bit line and the complementary bit line, the first path comprising: A first isolation transistor is used to receive an isolation control signal and is coupled between the bit line and a first node, and is used to decouple the sense amplifier from the bit line or electrically couple the sense amplifier to the bit line according to the isolation control signal. as well as A first inverter for receiving a sense amplifier enable signal and coupled between a second node and a third node, wherein a voltage of the second node is set as a first threshold voltage of the first inverter; A second path, between the first node and the complementary bit line, the second path comprising: A second isolation transistor, used to receive the isolation control signal and coupled between the complementary bit line and a fourth node, and used to electrically decouple the sense amplifier from the complementary bit line or electrically couple the sense amplifier to the complementary bit line according to the isolation control signal; and A second inverter, used to receive the enable signal of the sense amplifier, and coupled between a fifth node and a sixth node, wherein a voltage of the fifth node is set as a second threshold voltage of the second inverter; and A first transistor, which receives a control signal, is coupled in parallel with the first inverter; A second transistor, which receives the control signal, is coupled in parallel with the second inverter; and A pre-charge circuit is coupled to the bit line and the complementary bit line and is used to pre-charge the voltage of the bit line and the voltage of the complementary bit line to a pre-charge voltage in response to a pre-charge control signal.

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