A vertical cavity surface emitting laser

Abstract

The utility model belongs to the technical field of semiconductor laser, specifically relates to a vertical cavity surface emitting laser. The laser includes heat sink, bottom emission VCSEL chip and optical microstructure array that are sequentially arranged from bottom to top, bottom emission VCSEL chip is connected through flip -chip bonding with heat sink, optical microstructure array is set in the base below of bottom emission VCSEL chip, bottom emission VCSEL chip includes base and epitaxial layer set up on the base, is provided with etching groove on the epitaxial layer, etching groove sets up in epitaxial layer, and etching groove penetrates part epitaxial layer, forms cylindrical waveguide. The laser of the utility model improves chip output power inversion point through the improvement chip heat dissipation characteristic, and then increases chip output power.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor laser technology, and specifically relates to a vertical cavity surface-emitting laser. Background Technology

[0002] Compared to edge-emitting lasers (EELs), where the laser beam emerges from the cleaved surface of a semiconductor chip, vertical-cavity surface-emitting lasers (VCSELs) emit the laser beam perpendicular to the chip surface. They have extremely short cavity lengths and use distributed Bragg mirrors (DBRs) as top and bottom mirrors. Therefore, VCSELs offer numerous advantages over edge-emitting lasers, such as a circular beam, small divergence angle, low threshold voltage, ease of dual-array integration, and wafer-level fabrication and testing. Based on these advantages, VCSEL chips are gradually becoming the main power devices in 3D sensing, 5G communication, and autonomous driving. With the emergence and development of autonomous driving, LiDAR (Light Detection and Ranging) systems used in autonomous driving require higher photoelectric conversion efficiency, higher power density, lower divergence angle, and higher integration density from their emitters. Therefore, further improvements to existing VCSELs are necessary.

[0003] Currently, the main methods to increase the output power of a single-tube VCSEL chip are to increase the number of active junctions and the lateral area of ​​the active region. However, while this method increases the output power of the VCSEL chip and meets the high power requirements of LiDAR, it also faces problems such as difficult chip heat dissipation and difficult beam quality control. On the one hand, traditional sensor-type VCSEL chips adopt a front-emission structure, that is, the number of P-type DBRs (P-DBR) is less than that of N-type DBRs (N-DBR). The laser is emitted in the P-DBR direction. The heat dissipation path of this structure needs to pass through the N-DBR and the substrate to reach the heat sink for heat dissipation. In order to reduce the risk of chip breakage, the substrate thickness is usually reduced to more than 100um. This means that the heat generated in the active region of the chip needs to go through a long heat dissipation path to reach the heat sink. After increasing the number of active junctions, the thickness of the DBR layer increases, and the difficulty of heat dissipation increases accordingly. On the other hand, increasing the lateral area of ​​the active region to increase the output power is achieved by increasing the emission aperture of the single-tube VCSEL chip. However, increasing the lateral area of ​​the active region makes it difficult to control the emission divergence angle and emission mode.

[0004] Therefore, it is necessary to improve the heat dissipation problem of single-tube VCSEL chips and address the limitations of beam quality imposed by traditional surface-emitting laser structures in order to obtain high-quality single-tube VCSEL chips. Utility Model Content

[0005] To address the shortcomings of existing technologies, this invention provides a vertical cavity surface-emitting laser (VCSEL). This laser improves the chip's output power reversal point by enhancing the chip's heat dissipation characteristics, thereby increasing the chip's output power.

[0006] In a first aspect, the present invention provides a vertical cavity surface-emitting laser, the laser comprising a heat sink, a bottom-emitting VCSEL chip and an optical microstructure array arranged sequentially from bottom to top, the bottom-emitting VCSEL chip being connected to the heat sink by flip-chip bonding, and the optical microstructure array being disposed below the substrate of the bottom-emitting VCSEL chip.

[0007] According to an embodiment of the present invention, the bottom-emitting VCSEL chip includes a substrate and an epitaxial layer disposed on the substrate. An etching trench is disposed on the epitaxial layer, the etching trench is disposed within the epitaxial layer, and the etching trench penetrates a portion of the epitaxial layer to form a cylindrical waveguide.

[0008] According to an embodiment of the present invention, the etched groove is an annular groove formed by etching around the cylindrical waveguide, and the annular groove is concentrically arranged with the cylindrical waveguide.

[0009] According to an embodiment of the present invention, the epitaxial layer includes, from bottom to top, an N-DBR layer, an N-type ohmic contact layer, an active region, an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer.

[0010] According to the embodiments of this utility model, the depth of the etched trench is 7.8-8.2um, and 8um is an example.

[0011] According to an embodiment of the present invention, the etched trench is a ring concentric with the cylindrical waveguide, the inner diameter of the ring is 50-800μm, the width of the ring is 50-200μm, and the etching depth of the etched trench is from the P-type ohmic contact layer to the point where it stops after passing through the active region.

[0012] According to the embodiment of this utility model, the etching trench is etched from the P-type ohmic contact layer through the P-DBR layer, the oxide confinement layer, the active region, the first N-DBR layer, and stops after entering the N-type ohmic contact layer.

[0013] According to an embodiment of this utility model, the heat sink includes a substrate, an electrode area, and a pad area from bottom to top.

[0014] According to an embodiment of the present invention, a first electrode, a second electrode, a third electrode, and a fourth electrode are disposed on the epitaxial layer.

[0015] According to an embodiment of the present invention, the first electrode is circular and is disposed above the cylindrical waveguide; the second electrode is a non-closed annular ring and is disposed at the bottom of the etching trench; the third electrode is led out from the first electrode and the second electrode and extends to the bottom of the epitaxial layer around the etching trench; the fourth electrode is disposed at the top of the third electrode.

[0016] According to an embodiment of the present invention, the first electrode is a circular structure with a diameter 3-6 μm smaller than the inner diameter of the etching trench, for example, 4 μm smaller than the inner diameter of the etching trench.

[0017] According to the embodiments of this utility model, the material of the first electrode is Ti / Pt / Au, and the total thickness is 2500A-5000A, for example Ti / Pt / Au: 500A / 500A / 3000A.

[0018] According to an embodiment of the present invention, the second electrode is a non-closed ring structure and is disposed at the top of the etching trench. The inner diameter of the second electrode is 3-5 μm larger than the inner diameter of the etching trench, for example 4 μm, and the outer diameter of the second electrode is 3-5 μm smaller than the outer diameter of the etching trench, for example 4 μm.

[0019] According to an embodiment of the present invention, the second electrode material is Ni / Ge / Au / Ni / Au or GeAu / Ni / Au, with a thickness of 3000-4000 Å, exemplarily 3500 Å.

[0020] According to the embodiments of this utility model, the third electrode material is TiW / Au or Ti / Au, with a thickness of 4000-6000A, exemplarily 5000A.

[0021] According to an embodiment of this utility model, the material of the fourth electrode is Au, and the thickness is 5000-10000A, for example 8000A.

[0022] According to an embodiment of the present invention, the optical microstructure array is disposed below the substrate of the bottom-emitting VCSEL chip.

[0023] According to the embodiments of this utility model, the N-DBR layer and the P-DBR layer are AlxGa1-xAs and AlyGa1-yAs grown with alternating N-type doping and P-type doping, respectively; the N-type and P-type ohmic contact layers are GaAs with high N-type doping and high P-type doping, respectively; the active region includes multiple quantum wells (MQWs), tunnel junctions (TJs), and spacers; and the oxide confinement layer is P-type doped Al0.98Ga0.02As.

[0024] According to the embodiments of this utility model, the optical thickness of each pair of DBR layers is 0.5 times the center wavelength, the number of the first N-DBR pairs is greater than the number of the second N-DBR pairs, and the sum of the first and second N-DBR pairs is greater than the number of P-DBR pairs. The optical thickness of the P-type ohmic contact layer is 0.25 times the center wavelength, the optical thickness of the N-type ohmic contact layer is an integer multiple of the center wavelength > 5, the optical thickness of the active region is 1 times the center wavelength, and the physical thickness of the oxide confinement layer is 10-15 nm.

[0025] According to the embodiments of this utility model, the substrate material is N-type doped GaAs, undoped or half-doped GaAs.

[0026] According to an embodiment of the present invention, the heat sink includes a substrate, an electrode area, and a pad area from bottom to top, and the pad area has the same shape as the fourth electrode of the bottom-emitting VCSEL chip.

[0027] According to an embodiment of this utility model, the heat sink substrate material is AlN.

[0028] Secondly, this utility model also provides a method for preparing the above-mentioned laser chip, comprising the following steps: S1: Growing an epitaxial layer on the substrate; S2: A first electrode is disposed at a corresponding location on the surface of the epitaxial layer, and an etching trench with a ring structure is formed around the first electrode. The interior of the ring structure is a cylindrical waveguide, and a second electrode is disposed at the bottom of the etching trench. S3: An insulating layer is deposited on the top of the epitaxial layer, the first electrode, the second electrode and the inner wall of the etching trench, and an etching window is made above the first electrode and the second electrode; S4: A third electrode extends from the first electrode and the second electrode, the third electrode passing through the etching trench and extending to the epitaxial layer above the periphery of the etching trench; S5: A fourth electrode is disposed above the third electrode to form an emitting VCSEL chip. A heat sink is connected to the bottom emitting VCSEL chip via flip-chip bonding. The optical microstructure array is disposed on the substrate surface of the bottom emitting VCSEL chip.

[0029] According to the embodiment of this utility model, after step S5, the following step is also included: setting an optical antireflection film above the optical microstructure array on the substrate surface of the bottom-emitting VCSEL chip.

[0030] According to an embodiment of this utility model, the optical antireflective film is a SiNx monolayer film, deposited by PECVD equipment, and its optical thickness is 0.25 times the laser lasing wavelength.

[0031] According to the embodiment of this utility model, in step S1, a first N-DBR layer, an N-type ohmic contact layer, a second N-DBR layer, an active region, an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer are sequentially grown on the substrate using the MOCVD method.

[0032] According to the embodiment of this utility model, the following step is provided between steps S2 and S3: wet oxidation is performed on the oxide confinement layer in the cylindrical waveguide to form oxide holes.

[0033] According to the embodiment of this utility model, the following step is provided between steps S5 and S6: thinning and CMP polishing the emitting VCSEL chip on the substrate surface.

[0034] According to the embodiments of this utility model, the thickness of the thinned chip is 100um-130um, and exemplarily 120um.

[0035] According to an embodiment of this utility model, the roughness Ra of the back surface of the chip after CMP polishing is ≤10nm, and 5nm is an example.

[0036] According to an embodiment of the present invention, the oxidation depth of the oxidation confinement layer is 10um-20um.

[0037] According to the embodiment of this utility model, the etching in step S2 is ICP etching, the etching gas is a Cl2 / Ar2 / N2 mixed gas or a BCl3 / Cl2 mixed gas, and the etching mask is a photoresist mask.

[0038] According to the embodiment of this utility model, in step S3, the material of the insulating layer is SiNx, and the thickness is 2000A-4000A, with 3000A being an example.

[0039] According to the embodiments of this utility model, in step S5, the optical microstructure array includes, but is not limited to, microlens arrays, gratings, photonic crystals, etc., which are fabricated by micro-nano fabrication techniques such as ICP etching or electron beam direct writing.

[0040] Beneficial effects 1) This invention employs a bottom-emitting VCSEL chip. The light emission direction of the bottom-emitting VCSEL chip is perpendicular to the bottom surface of the chip. The bottom-emitting VCSEL chip is connected to the heat sink via flip-chip bonding, thereby optimizing the heat dissipation path. The heat dissipation path of the traditional front-emitting VCSEL is "active region → epitaxial layer → substrate → heat sink", while the heat dissipation path of the bottom-emitting VCSEL chip in this invention is simplified to "active region → epitaxial layer → heat sink". Therefore, compared with the corresponding front-emitting VCSEL, the heat dissipation path of the bottom-emitting VCSEL chip in this invention does not pass through the substrate, and the total thickness of the heat dissipation path is at least 100um, which significantly improves the heat dissipation efficiency of the device. Therefore, this invention effectively shortens the heat conduction path by using the VCSEL chip to emit light from the substrate surface and flip-chip bonding, thereby improving the overall heat dissipation performance of the chip, increasing the roll-over point of the output power, and ultimately enhancing the maximum output power of the VCSEL chip.

[0041] 2) This invention achieves the arrangement of coplanar electrodes in the backlight direction of the VCSEL chip, and sets up a microstructure array in the light-emitting direction of the chip to optimize the far-field characteristics of the laser and improve the beam quality. In addition, the coplanar electrode design of this invention enables the chip and the heat sink to complete electrical connection and thermal contact simultaneously through a single bonding process. This not only simplifies the packaging process, but also leaves sufficient space for the fabrication of the light-emitting surface microstructure, thereby significantly reducing the process complexity and improving the structural integration, and greatly reducing the process difficulty. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the longitudinal cross-section of the vertical cavity surface-emitting laser in an embodiment of this utility model; Figure 2 This is a top view schematic diagram of a vertical cavity surface-emitting laser with different waveguide dimensions in the embodiments of this utility model; Figure 3 The method for fabricating the vertical cavity surface-emitting laser in this embodiment of the present invention Flowchart of the method; Figure 4 This is a top view of the bottom-emitting vertical-cavity surface-emitting laser chip in this embodiment of the present invention; Figure 5 This is a top view of the vertical cavity surface-emitting laser in the embodiment of this utility model; Figure 6 This is a graph showing the power-current-voltage test results of the vertical cavity surface-emitting laser in Embodiment 2 of this utility model; Figure 7 This is a spectral performance diagram of the vertical cavity surface-emitting laser in Embodiment 2 of this utility model; Figure 8 This is a beam quality diagram of the vertical cavity surface-emitting laser in Embodiment 2 of this utility model; Figure 9 This is a schematic diagram of the optical field and heat dissipation of the vertical cavity surface-emitting laser in an embodiment of this utility model.

[0043] In the figure, 1-bottom emission VCSEL chip: 101-substrate, 102-N-DBR layer, 103-N-type ohmic contact layer, 104-active region, 105-oxidation confinement layer, 106-P-DBR layer, 107-P-type ohmic contact layer, 108-etched trench, 109-first electrode, 110-second electrode, 111-third electrode, 112-fourth electrode, 113-insulating layer; 2-Heat sink: 201-Substrate, 202-Electrode area, 203-Pad area; 3-Optical microstructure array: 301-Microstructure array, 302-Optical antireflection film. Detailed Implementation

[0044] The structure of this utility model will be further described in detail below with reference to specific embodiments. It should be understood that the following embodiments are merely illustrative and explanatory of this utility model and should not be construed as limiting the scope of protection of this utility model. All technologies implemented based on the above content of this utility model are covered within the scope of protection intended by this utility model.

[0045] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0046] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0047] Example 1 See Figure 1As shown, the vertical cavity surface-emitting laser provided in this embodiment includes a heat sink 2, a bottom-emitting VCSEL chip 1, and an optical microstructure array 3 arranged sequentially from bottom to top. The bottom-emitting VCSEL chip 1 includes a substrate 101 and an epitaxial layer arranged sequentially from top to bottom. The epitaxial layer includes an N-DBR layer 102, an N-type ohmic contact layer 103, an active region 104, an oxide confinement layer 105, a P-DBR layer 106, and a P-type ohmic contact layer 107 arranged sequentially from bottom to top (the bottom-emitting VCSEL chip 1 is an inverted structure, but it is described as an upright structure in this case). A cylindrical waveguide is formed in the epitaxial layer by etching trenches 108.

[0048] See Figure 2 As shown, the etching trench 108 penetrates the P-type ohmic contact layer 107, the P-DBR layer 106, the oxide confinement layer 105, and the active region 104, stopping after reaching the N-type ohmic contact layer 103, forming a cylindrical waveguide. Specifically, the etching trench 108 is an annular trench etched around the cylindrical waveguide, and the annular trench is concentrically arranged with the cylindrical waveguide. The etching trench 108 is completed using an ICP etching process, and the depth of the etching trench 108 is 7.8-8.2 μm, exemplarily 8 μm. Figure 2 The top view of the etched trench 108 is that of concentric rings, with an inner diameter of 50-800 μm and a width of 50-200 μm. (See [reference]). Figure 2 For example, the inner diameter of the concentric ring is 50 μm and the width of the concentric ring is 50 μm, or the inner diameter of the concentric ring is 400 μm and the width of the concentric ring is 100 μm.

[0049] The heat sink 2 includes a substrate 201, an electrode area 202 and a pad area 203 arranged sequentially from bottom to top. The number of electrode areas 202 is set according to actual needs, and the pad areas 203 are correspondingly arranged in the electrode areas 202.

[0050] The optical microstructure 3 array is disposed beneath the substrate of the bottom-emitting VCSEL chip 1. Figure 1 The bottom-emitting VCSEL chip 1 is inverted and formed by etching or bonded to the substrate of the bottom-emitting VCSEL chip 1. The bottom-emitting VCSEL chip 1 is connected to the heat sink 2 by flip bonding.

[0051] A first electrode 109, a second electrode 110, a third electrode 111, a fourth electrode 112, and an insulating layer 113 are disposed between the epitaxial layer and the heat sink 2.

[0052] The first electrode 109 is disposed on the top of the cylindrical waveguide. The first electrode 109 is circular, and the center of the first electrode 109 overlaps with the center of the cylindrical waveguide. The diameter of the first electrode 109 is 3-6 μm smaller than the inner diameter of the cylindrical waveguide (i.e., the inner diameter of the concentric rings), and is 4 μm smaller than the inner diameter of the cylindrical waveguide. The material of the first electrode 109 is Ti / Pt / Au from bottom to top, and the total thickness is 2500A-5000A, and the example is Ti / Pt / Au: 500A / 500A / 3000A. It is prepared using metal deposition equipment such as electron beam evaporation or magnetron sputtering.

[0053] The second electrode 110 is disposed at the bottom of the etching trench 108, that is, at the top of the exposed N-type ohmic contact layer 103. The second electrode 110 is a non-closed annular ring, and the center of the second electrode 110 overlaps with the center of the etching trench 108. The inner diameter of the second electrode 110 is 3-5 μm larger than the inner diameter of the etching trench 108, for example 4 μm, and the outer diameter is 3-5 μm smaller than the outer diameter of the etching trench 108, for example 4 μm. The material of the second electrode 110 is Ni / Ge / Au / Ni / Au or GeAu / Ni / Au, and the thickness is 3000-4000 Å, for example 3500 Å. It is prepared using metal deposition equipment such as electron beam evaporation or magnetron sputtering.

[0054] The third electrode 111 extends from the first electrode 109 and the second electrode 110 to the epitaxial layer surrounding the etching trench 108. Specifically, one side of the third electrode 111 ( Figure 1 The third electrode 110 extends from the first electrode 109 through the sidewall and bottom of the current side etched trench 108, and extends above the current side epitaxial layer; the other side of the third electrode 110 ( Figure 1 The second electrode 110 (located on the right side) extends from the bottom of the etched trench 108 to the top of the epitaxial layer on the right side. The third electrode 111 is made of TiW / Au or Ti / Au material, with a thickness of 4000-6000 Å, exemplarily 5000 Å, and is fabricated using metal deposition equipment such as electron beam evaporation or magnetron sputtering. An insulating layer 113 is provided between the etched trench 108 and the third electrode 111. The insulating layer 113 is made of SiNx material, with a thickness of 2000 Å-4000 Å, exemplarily 3000 Å, and is deposited using PECVD (Plasma-Enhanced Chemical Vapor Deposition) or ALD (Atomic Layer Deposition) equipment.

[0055] The fourth electrode 112 is disposed between the third electrode 111 and the electrode region 202 at the bottom of the cylindrical waveguide and the bottom of the epitaxial layer. The fourth electrode 112 is equivalent to thickening the third electrode 111. The material of the fourth electrode 112 is Au, and the thickness is 5000-10000A, exemplarily 8000A. It is prepared by electroplating or chemical plating.

[0056] The shape of the fourth electrode 112 is the same as that of the pad area 203. The bottom-emitting VCSEL chip 1 is connected to the heat sink 2 by flip bonding. The optical microstructure array 3 is disposed on the substrate 101 of the bottom-emitting VCSEL chip 2. The optical microstructure array 3 includes a microstructure array 301 and an optical antireflection film 302. The optical antireflection film 302 is disposed on the top of the microstructure array 301.

[0057] The fourth electrode 112 has the same shape and material as the pad area 203, and they are fused together after welding. Therefore, they are not clearly distinguished in the figure.

[0058] The N-DBR layer 102 and P-DBR layer 106 are AlxGa1-xAs and AlyGa1-yAs grown with alternating N-type and P-type doping, respectively, where x = 0.1-0.15, x is 0.12 for example; y = 0.85-0.9, y is 0.88 for example. The optical thickness of each pair of DBR layers is 0.5 times the center wavelength. The number of the first N-DBR pairs is greater than the number of the second N-DBR pairs, and the sum of the first and second N-DBR pairs is greater than the number of P-DBR pairs. The number of N-DBR pairs is 20-25 pairs, 24 pairs for example, and the number of P-DBR pairs is 36-44 pairs, 38 pairs for example.

[0059] The N-type ohmic contact layer 103 and the P-type ohmic contact layer 107 are respectively N-type highly doped and P-type highly doped GaAs. The active region 104 includes multiple quantum wells (MQWs), tunnel junctions (TJs), and spacers: the quantum wells are grown alternately from Inx Ga1-x As and Aly Ga1-y As, where x = 0.1-0.2 and y = 0.2-0.4, and the alternation period of Inx Ga1-x As and Aly Ga1-y As is 3-5 times; the spacer is made of GaAs, and the sum of the optical thicknesses of the quantum wells, tunnel junctions, and resonant cavities is an integer multiple of half the laser lasing wavelength.

[0060] The oxide confinement layer 105 is made of AlxGa1-xAs, where x = 0.96-1.0, with examples of 0.96, 0.98, and 1.0. The thickness of the oxide confinement layer 105 is 10-20 nm, with examples of 10 nm, 12 nm, 15 nm, and 20 nm. The method for preparing the oxide confinement layer 105 includes oxidizing the oxide confinement layer 105 using a wet oxidation technique, thereby oxidizing the AlxGa1-xAs material to Al2O3 to confine the light and electric fields.

[0061] The substrate 101 can be made of N-type doped GaAs, or undoped or half-doped GaAs.

[0062] The substrate 201 is made of high thermal conductivity insulating materials such as AlN, SiC, and diamond; the electrode region 202 is made of Ti / Pt / Au with a thickness of Ti / Pt / Au=500A / 500A / 10000A, and is prepared using electron beam thermal evaporation or magnetron sputtering equipment; the pad region 203 has the same shape as the fourth electrode 112 of the bottom-emitting VCSEL chip 1, is made of AnSe alloy with a thickness of 20000A, and is prepared using a resistive evaporation coating machine.

[0063] Example 2 like Figure 3 As shown, a method for fabricating a vertical-cavity surface-emitting laser includes the following steps: S1: See Figure 3 As shown in (1), an N-type doped GaAs substrate or a half-doped GaAs substrate is selected as substrate 101. On substrate 101, an MOCVD (Metal-organic Chemical Vapor Deposition) or MBE (molecular beam epitaxy) device is used to grow an epitaxial layer, an N-DBR layer 102, an N-type ohmic contact layer 103, an active region 104, an oxide confinement layer 105, a P-DBR layer 106, and a P-type ohmic contact layer 107 on substrate 101.

[0064] The active region 104 serves as the light-emitting region and includes one or more sets of alternatingly grown multiple quantum well layers (MQWs), tunnel junction layers (TJs), and spacers. The N-type ohmic contact layer 103 and the P-type ohmic contact layer 107 form good ohmic contact with the metal electrode through high doping. The oxide confinement layer 105 confines the laser by limiting the electric and optical fields, and the N-DBR layer 102 and the P-DBR layer 106 enable the laser to form a single longitudinal mode output through Bragg reflection.

[0065] S2: See also Figure 3 As shown in (2), a negative photoresist is used to perform the first photolithography pattern on the surface of the epitaxial layer, and a metal evaporation device is used to deposit the first electrode 109. The evaporation material is Ti / Pt / Au, and the thickness is 500A / 500A / 2000A. Then, an organic solvent is used for lift-off, and then annealing is performed at 420℃ for 90s to form an ohmic contact with the P-type ohmic contact layer 107.

[0066] S3: See also Figure 3 As shown in (3), a second photolithography pattern is formed using a photoresist resistant to etching, forming a mask around the first electrode 109 to create an etching trench 108. The PR (photoresist) mask is then cured, followed by ICP etching (inductively coupled plasma etching) to form the etching trench 108 and the cylindrical waveguide surrounding it (process parameters: Cl2 flow rate 4 sccm, Ar flow rate 30 sccm, N2 flow rate 5 sccm, ICP-RF power 330W, Table RF power 70W, temperature 25℃). During the etching process, the etching stop point is monitored by a 670nm laser extreme value monitoring curve.

[0067] S4: See also Figure 3 As shown in (4), the oxide confinement layer 105 is subjected to wet oxidation to form an oxide confinement hole. The diameter of the oxide confinement hole is the same as the diameter of the first electrode 109. The oxidation temperature is 350℃-420℃, and for example, it is 400℃.

[0068] S5: See also Figure 3 As shown in (5), a third photolithography pattern is formed using negative photoresist, and a second electrode 110 is set at the bottom of the etched trench 108 using a metal evaporation device to contact the N-type ohmic contact layer 103. The evaporation material is GeAu / Ni / Au with thicknesses of 500A / 500A / 2000A, respectively. Then, an organic solvent is used for stripping, and annealing is performed at 390℃ for 30s to form an ohmic contact with the N-type ohmic contact layer 103.

[0069] S6: See also Figure 3As shown in (6), an insulating layer is deposited on the front side of the chip using a PECVD (plasma-enhanced chemical vapor deposition) device. The deposited material is SiNx with a thickness of 3000 Å. Then, a fourth photolithography pattern is formed using positive photoresist, and an RIE (reactive ion etching) device is used to etch and open windows above the first electrode 109 and the second electrode 110. Since there is a height difference of about 8 μm between the first electrode 109 and the second electrode 110, the second electrode 110 needs to be aligned and exposed twice.

[0070] S7: See also Figure 3 As shown in (7), a fifth photolithography pattern is formed using negative photoresist, and a third electrode 111 is formed above the first electrode 109 and the second electrode 110 using a magnetron sputtering device, extending through the etching trench 108 to the epitaxial layer surrounding the etching trench 108 (i.e., Figure 1 The bottom of the epitaxial layer in the middle is deposited with Ti / Au material and a thickness of 300A / 4800A, and then stripped with an organic solvent.

[0071] S8: See also Figure 3 As shown in (8), a sixth photolithography pattern is formed using negative photoresist, and a fourth electrode 112 is formed above the third electrode 111 and the epitaxial layer (the top of which the third electrode 111 is not set) using an electroplating machine. The material is Au and the thickness is 10000A.

[0072] S9: The VCSEL chip 1 is thinned and CMP polished (chemical mechanical polishing) on ​​the substrate 101 to a thickness of 120 μm and a surface roughness Ra < 5 nm.

[0073] S10: Heat sink 2 is prepared using photolithography, metal coating, and scratching steps. The pad area 203 in heat sink 2 is aligned with the fourth electrode 112 of bottom-emitting VCSEL chip 1 and flip-chip bonding is performed. The bonding temperature is 320℃ and the bonding force is 100N.

[0074] S11: The substrate 101 of the bottom-emitting VCSEL chip 1 is patterned for the seventh time using a double-sided alignment process, and the optical microstructure array 3 is set on the substrate 101 surface of the bottom-emitting VCSEL chip 1 using an ICP etching process.

[0075] S12: An optical antireflective film is disposed above the optical microstructure array 3. The material is SiNx and the optical thickness is 0.25 times the center wavelength.

[0076] The vertical-cavity surface-emitting laser obtained in this embodiment was subjected to current-voltage-power testing, and participated in... Figure 6-8The present invention demonstrates that the laser, driven by a continuous current (CW) at 25°C, can achieve a P=1.2W@1.5A output. Spectroscopic testing of the vertical-cavity surface-emitting laser obtained in this embodiment revealed that the device exhibits a single longitudinal mode and multiple transverse modes in its output characteristics. Beam quality testing of the vertical-cavity surface-emitting laser obtained in this embodiment showed that the device produces a Gaussian beam with excellent beam quality.

[0077] See Figure 9 The diagram shows the light field and heat dissipation of the vertical cavity surface-emitting laser (VCSEL) of this embodiment. The bottom-emitting VCSEL chip 1 of this invention emits light from the bottom surface. After bonding with the heat sink at the bottom of the chip, the heat dissipation path of a traditional front-emitting VCSEL is active region → epitaxial layer → substrate → heat sink. However, the heat dissipation path of the bottom-emitting VCSEL chip 1 of this invention is active region → epitaxial layer → heat sink. It can be seen that compared with the corresponding surface-emitting VCSEL, the heat dissipation path of the bottom-emitting VCSEL of this invention does not pass through the substrate, and the heat dissipation thickness is reduced by at least 100um. Therefore, it has a better heat dissipation effect.

[0078] In addition, the present invention, through the design of coplanar electrodes, enables the chip to achieve conduction with the heat sink in a one-step bonding process, and leaves space for microstructures to be set on the light-emitting surface of the chip, which greatly reduces the difficulty of the process.

[0079] The specific embodiments of this utility model have been described above by way of example. However, the protection scope of this utility model is not limited to the above exemplary embodiments. Any modifications, equivalent substitutions, improvements, etc., made by those skilled in the art within the spirit and principles of this utility model should be included within the protection scope of the claims of this utility model.

Claims

1. A vertical-cavity surface-emitting laser, characterized in that, The laser includes a heat sink, a bottom-emitting VCSEL chip, and an optical microstructure array arranged sequentially from bottom to top. The bottom-emitting VCSEL chip is connected to the heat sink via flip-chip bonding, and the optical microstructure array is disposed below the substrate of the bottom-emitting VCSEL chip. The bottom-emitting VCSEL chip includes a substrate and an epitaxial layer disposed on the substrate. The epitaxial layer has etched trenches disposed within the epitaxial layer and penetrating a portion of the epitaxial layer to form a cylindrical waveguide.

2. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The epitaxial layer includes, from bottom to top, an N-DBR layer, an N-type ohmic contact layer, an active region, an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer.

3. The vertical-cavity surface-emitting laser according to claim 2, characterized in that, The etching trench is etched from the P-type ohmic contact layer through the P-DBR layer, the oxide confinement layer, the active region, and the first N-DBR layer, and stops after entering the N-type ohmic contact layer; the heat sink includes the substrate, the electrode region, and the pad region from bottom to top.

4. The vertical-cavity surface-emitting laser according to claim 1, characterized in that, The epitaxial layer is provided with a first electrode, a second electrode, a third electrode, and a fourth electrode. The first electrode is circular and is disposed above the cylindrical waveguide. The second electrode is a non-closed annular shape and is disposed at the bottom of the etched trench. The third electrode is led out from the first electrode and the second electrode and extends to the bottom of the epitaxial layer around the etch trench; The fourth electrode is disposed on top of the third electrode.

5. The vertical-cavity surface-emitting laser according to any one of claims 1-4, characterized in that, The optical microstructure array is disposed beneath the substrate of the bottom-emitting VCSEL chip.

6. The vertical-cavity surface-emitting laser according to claim 2, characterized in that, The N-DBR layer and P-DBR layer are AlxGa1-xAs and AlyGa1-yAs grown with alternating N-type and P-type doping, respectively. The N-type and P-type ohmic contact layers are GaAs with high N-type and high P-type doping, respectively. The active region includes multiple quantum wells, a tunnel junction, and a spacer layer.

7. The vertical-cavity surface-emitting laser according to claim 2, characterized in that, The oxide confinement layer is a p-type doped Al. 0.98 Ga 0.02 As.

8. The vertical-cavity surface-emitting laser according to claim 4, characterized in that, Each pair of DBR layers has an optical thickness of 0.5 times the center wavelength. The number of the first N-DBR pairs is greater than the number of the second N-DBR pairs, and the sum of the first and second N-DBR pairs is greater than the number of P-DBR pairs.

9. The vertical-cavity surface-emitting laser according to claim 2, characterized in that, The optical thickness of the P-type ohmic contact layer is 0.25 times the center wavelength, and the optical thickness of the N-type ohmic contact layer is greater than 5 times the center wavelength.

10. The vertical-cavity surface-emitting laser according to claim 2, characterized in that, The optical thickness of the active region is 1 times the center wavelength, and the physical thickness of the oxide confinement layer is 10-15 nm.

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