Standby power timing lock quick discharge circuit and electronic device

Abstract

The utility model provides a kind of standby power time sequence locking quick discharge circuit and electronic equipment, when normal work, voltage dividing circuit controls power supply circuit conduction after standby power voltage is divided, for load normal power supply, while delay discharge circuit is in closed state.When ATX power is disconnected, control signal disappears, voltage dividing circuit loses control reference, power supply circuit is immediately turned off, and the direct connection of standby power and load is cut off, to prevent residual charge from flowing back to ATX power supply.At this time, the delay discharge circuit detects the disappearance of the control signal, and automatically turns on after a preset delay time, discharging the residual charge at the output end of the power supply circuit to the ground through the controlled path.

Description

Technical Field

[0001] This utility model relates to the field of power electronics, and in particular to a standby power supply timing lock fast discharge circuit and electronic device. Background Technology

[0002] With the rapid development of computer technology, motherboard power management technology has become increasingly important. Current computer motherboards use the ATX power standard, which includes a 5V standby power supply (5VSB) to provide standby functionality when the motherboard is powered off. The main purpose of this standby power supply is to detect the power button or to discharge other power sources during standby. However, existing technology has significant shortcomings in handling residual charge discharge after the motherboard is powered off.

[0003] Currently, the discharge section of domestically produced computer motherboards generally does not include a controllable or reliable discharge circuit. When the ATX power connector is unplugged, a large amount of charge still accumulates on the motherboard. If the computer is turned on intermittently within a short period of time, the residual charge will flow back to the normal ATX power supply, causing the fuse to burn out or the TVS diode on the 5VSB line to break down, posing a safety hazard.

[0004] In view of the above, this application is hereby submitted. Utility Model Content

[0005] This utility model discloses a standby power supply timing lock fast discharge circuit and electronic device, which aims to realize delayed automatic discharge of the motherboard standby power supply and avoid residual charge from damaging the circuit.

[0006] The first embodiment of this utility model provides a standby power supply timing lock fast discharge circuit, including: an ATX power supply, a voltage divider circuit, a power supply circuit, and a delayed discharge circuit; The input terminal of the voltage divider circuit is used to connect to the standby power supply, the standby power supply is electrically connected to the input terminal of the power supply circuit, the output terminal of the power supply circuit is used to connect to the load, and the output terminal of the voltage divider circuit is electrically connected to the control terminal of the power supply circuit. The control signal of the ATX power supply is electrically connected to the control terminal of the delayed discharge circuit, the output terminal of the power supply circuit is electrically connected to the input terminal of the delayed discharge circuit, and the output terminal of the delayed discharge circuit is grounded. The delayed discharge circuit is configured to delay grounding the power supply circuit after the control signal of the ATX power supply disappears.

[0007] Preferably, the voltage divider circuit includes a first resistor and a second resistor; The first end of the first resistor is electrically connected to the standby power supply, and the second end of the first resistor is grounded through the second resistor.

[0008] Preferably, the power supply circuit includes a first PMOS transistor; In this configuration, the gate (G) of the first PMOS transistor is electrically connected to the second terminal of the first resistor, the source (S) of the first PMOS transistor is electrically connected to the first terminal of the first resistor, and the drain (D) of the first PMOS transistor is used to connect to the load.

[0009] Preferably, the delayed discharge circuit includes a third resistor, a fourth resistor, a second PMOS transistor, a first capacitor, and a diode; The control signal of the ATX power supply is electrically connected to the gate (G) of the second PMOS transistor through the fourth resistor. The first capacitor is connected in parallel to the gate (G) and drain (D) of the second PMOS transistor. The gate (G) of the second PMOS transistor is electrically connected to the positive terminal of the diode. The source (S) of the second PMOS transistor is electrically connected to the negative terminal of the diode. The negative terminal of the diode is electrically connected to the first end of the third resistor. The second end of the third resistor is electrically connected to the source (S) of the first PMOS transistor.

[0010] Preferably, it also includes a filter circuit; The filter circuit is configured between the power supply circuit and the load.

[0011] The second embodiment of this utility model is an electronic device, including a standby power supply timing lock fast discharge circuit as described in any one of the above.

[0012] Based on the standby power supply timing-locked fast discharge circuit and electronic device disclosed in this utility model, during normal operation, the voltage divider circuit divides the standby power supply voltage and controls the power supply circuit to conduct, providing normal power to the load, while the delayed discharge circuit is in the off state. When the ATX power supply is disconnected, the control signal disappears, causing the voltage divider circuit to lose its control reference, and the power supply circuit immediately shuts off, cutting off the direct connection between the standby power supply and the load, preventing residual charge from flowing back into the ATX power supply. At this time, the delayed discharge circuit detects the disappearance of the control signal and automatically conducts after a preset delay time, quickly discharging the residual charge at the output of the power supply circuit to the ground wire through a controlled path. This ensures that other circuits complete their respective discharge processes before the standby power supply is turned off, avoiding the problem of incomplete discharge caused by the loss of control signal. The entire process realizes the transformation from passive resistor discharge to active timing-controlled discharge, safely clearing all residual charge within milliseconds, effectively preventing stress damage to circuit components caused by charge accumulation and safety hazards during insertion and removal. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a standby power supply timing lock fast discharge circuit provided by this utility model; Figure 2This is a schematic diagram of other power supply discharge circuits provided by this utility model. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Therefore, the following detailed description of the embodiments of this utility model provided in the accompanying drawings is not intended to limit the scope of the claimed utility model, but merely represents selected embodiments of this utility model. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0015] The specific embodiments of this utility model are described in detail below with reference to the accompanying drawings.

[0016] This utility model discloses a standby power supply timing lock fast discharge circuit and electronic device, which aims to realize delayed automatic discharge of the motherboard standby power supply and avoid residual charge from damaging the circuit.

[0017] Please see Figure 1 The first embodiment of this utility model provides a standby power supply timing lock fast discharge circuit, including: an ATX power supply, a voltage divider circuit 1, a power supply circuit 2, and a delayed discharge circuit 3. The input terminal of the voltage divider circuit 1 is used to connect to the standby power supply, the standby power supply is electrically connected to the input terminal of the power supply circuit 2, the output terminal of the power supply circuit 2 is used to connect to the load, and the output terminal of the voltage divider circuit 1 is electrically connected to the control terminal of the power supply circuit 2. The control signal of the ATX power supply is electrically connected to the control terminal of the delayed discharge circuit 3, the output terminal of the power supply circuit 2 is electrically connected to the input terminal of the delayed discharge circuit 3, and the output terminal of the delayed discharge circuit 3 is grounded. The delayed discharge circuit 3 is configured to delay grounding the power supply circuit 2 after the control signal of the ATX power supply disappears.

[0018] In this embodiment, the ATX power supply provides a 5V standby power supply (5VSB) and a control signal ATX_POWER. The 5VSB standby power supply serves as the main power source for the entire circuit, continuously providing a 5V DC voltage during normal system operation. The control signal ATX_POWER maintains a high level of 3.3V during normal power supply operation and drops to a low level of 0V when the ATX power supply is disconnected or malfunctions. Changes in the control signal ATX_POWER trigger the initiation of the entire discharge process.

[0019] Voltage divider circuit 1 consists of a first resistor R1 and a second resistor R2 connected in series. The resistance of the first resistor R1 is 470kΩ, and the resistance of the second resistor R2 is 100kΩ. (It should be noted that in other embodiments, the resistance values ​​can be varied according to actual conditions, and are not specifically limited here, but these solutions are all within the protection scope of this utility model.) The input terminal of voltage divider circuit 1 is connected to the standby power supply 5VSB. Through a precise resistance ratio, a voltage divider output of approximately 0.88V is generated across the second resistor R2. This voltage divider output is connected to the control terminal of power supply circuit 2, providing a stable control voltage for power supply circuit 2.

[0020] Power supply circuit 2 is implemented using a P-channel enhancement-mode MOSFET Q1 (i.e., the first PMOS transistor, hereinafter referred to as Q1). In this embodiment, a SIS443DN-T1-GE3 PMOS transistor is selected. The source of this MOSFET serves as the input terminal of power supply circuit 2, directly connected to the standby power supply 5VSB; the drain serves as the output terminal of power supply circuit 2, connected to the load circuit; and the gate serves as the control terminal, connected to the output terminal of voltage divider circuit 1. Under normal operating conditions, since voltage divider circuit 1 provides a gate voltage of approximately 0.88V, while the source voltage is 5V, a gate-source voltage VGS of approximately -4.12V is formed, which far exceeds the turn-on threshold of the PMOS transistor, causing Q1 to be fully turned on, and the standby power supply normally supplies power to the load through Q1. When the ATX power supply is disconnected, the standby power supply loses power, the reference voltage of voltage divider circuit 1 disappears, VGS approaches 0V, and Q1 quickly turns off, effectively isolating the load terminal from the ATX power supply interface and preventing the backflow of residual charge.

[0021] The delayed discharge circuit 3 consists of an RC delay circuit (including a fourth resistor R4 and a first capacitor C1), a discharge switch (i.e., a second PMOS transistor, hereinafter referred to as Q2), and a diode D1 (used for voltage clamping). R4 is a 10kΩ resistor, and C1 is a 22μF capacitor, together forming a delay constant of approximately 220 milliseconds. The discharge switch uses another P-channel enhancement-type MOS transistor, Q2. In this embodiment, the IRF9540S model is selected, with a turn-on voltage range of -2V to -4V. The source of Q2 is connected to the output terminal of power supply circuit 2, i.e., the load side. The drain is grounded through a current-limiting resistor R3, and the gate is connected to the ATX_POWER control signal through R4. The voltage clamping circuit is implemented by a Zener diode D1, specifically a BZX84-C2V4 model, with a reverse breakdown voltage of 2.4V, connected between the gate and source of Q2.

[0022] The delayed discharge circuit 3 operates using timing control. During normal system operation, the ATX_POWER signal is 3.3V high, charging C1 to 3.3V through R4. At this time, Q2's VGS is approximately -1.7V, below its turn-on threshold, and Q2 remains off, with no discharge path. When the ATX power supply is disconnected, the ATX_POWER signal drops to 0V, and C1 begins to slowly discharge through R4. As the voltage of C1 decreases, the gate voltage of Q2 also decreases. When the gate voltage drops to VGS of -2V, Q2 begins to conduct. The Zener diode D1 plays a crucial role in this process, clamping the gate-source voltage of Q2 at -2.4V, ensuring that Q2 can fully conduct without being damaged by excessive VGS.

[0023] In one possible implementation of this utility model, a filter circuit 4 is also included; The filter circuit is configured between the power supply circuit 2 and the load.

[0024] Specifically, this includes a second capacitor C2 and a third capacitor C3. These two capacitors are directly connected in parallel to the output terminal of power supply circuit 2, specifically between the drain of PMOS transistor Q1 and ground. Both capacitors C2 and C3 are 220μF electrolytic capacitors, together forming a filter energy storage network with a total capacitance of 440μF. This not only effectively filters out power supply ripple but also provides energy buffering during transient load changes, ensuring the stability of the load terminal voltage.

[0025] Furthermore, please combine Figure 2Under normal operating conditions, the ATX power supply continuously supplies power, and the ATX_POWER signal remains at a high level of 3.3V. A1 is pulled up via R6 (10kΩ). While A1 is conducting, it doesn't discharge the 5VSB power supply. At this time, the gates of A2 / A3 are not turned on due to the low level, so 5VS and 3VS remain powered and continue to supply the load normally. When the ATX power supply is unplugged, the 3.3V signal goes low. Because of the delayed discharge circuit 3, 5VSB still exists, causing A1 to turn off. The gates of A2 / A3 receive a high level and turn on, discharging 5VS and 3VS. Finally, 5VSB discharges automatically after its delay ends.

[0026] The second embodiment of this utility model is an electronic device, including a standby power supply timing lock fast discharge circuit as described in any one of the above.

[0027] Based on the standby power supply timing-locked fast discharge circuit and electronic device disclosed in this utility model, during normal operation, the voltage divider circuit divides the standby power supply voltage and controls the power supply circuit to conduct, providing normal power to the load, while the delayed discharge circuit is in the off state. When the ATX power supply is disconnected, the control signal disappears, causing the voltage divider circuit to lose its control reference, and the power supply circuit immediately shuts off, cutting off the direct connection between the standby power supply and the load, preventing residual charge from flowing back into the ATX power supply. At this time, the delayed discharge circuit detects the disappearance of the control signal and automatically conducts after a preset delay time, quickly discharging the residual charge at the output of the power supply circuit to the ground wire through a controlled path. This ensures that other circuits complete their respective discharge processes before the standby power supply is turned off, avoiding the problem of incomplete discharge caused by the loss of control signal. The entire process realizes the transformation from passive resistor discharge to active timing-controlled discharge, safely clearing all residual charge within milliseconds, effectively preventing stress damage to circuit components caused by charge accumulation and safety hazards during insertion and removal.

[0028] The above are merely preferred embodiments of this utility model. The protection scope of this utility model is not limited to the above embodiments. All technical solutions that fall within the scope of this utility model's concept are protected by this utility model.

Claims

1. A standby power supply timing-locked fast discharge circuit, characterized in that, include: ATX power supply, voltage divider circuit, power supply circuit, and delayed discharge circuit; The input terminal of the voltage divider circuit is used to connect to the standby power supply, the standby power supply is electrically connected to the input terminal of the power supply circuit, the output terminal of the power supply circuit is used to connect to the load, and the output terminal of the voltage divider circuit is electrically connected to the control terminal of the power supply circuit. The control signal of the ATX power supply is electrically connected to the control terminal of the delayed discharge circuit, the output terminal of the power supply circuit is electrically connected to the input terminal of the delayed discharge circuit, and the output terminal of the delayed discharge circuit is grounded. The delayed discharge circuit is configured to delay grounding the power supply circuit after the control signal of the ATX power supply disappears.

2. The standby power supply timing-locked fast discharge circuit according to claim 1, characterized in that, The voltage divider circuit includes a first resistor and a second resistor; The first end of the first resistor is electrically connected to the standby power supply, and the second end of the first resistor is grounded through the second resistor.

3. The standby power supply timing-locked fast discharge circuit according to claim 2, characterized in that, The power supply circuit includes a first PMOS transistor; In this configuration, the gate (G) of the first PMOS transistor is electrically connected to the second terminal of the first resistor, the source (S) of the first PMOS transistor is electrically connected to the first terminal of the first resistor, and the drain (D) of the first PMOS transistor is used to connect to the load.

4. The standby power supply timing-locked fast discharge circuit according to claim 3, characterized in that, The delayed discharge circuit includes a third resistor, a fourth resistor, a second PMOS transistor, a first capacitor, and a diode; The control signal of the ATX power supply is electrically connected to the gate (G) of the second PMOS transistor through the fourth resistor. The first capacitor is connected in parallel to the gate (G) and drain (D) of the second PMOS transistor. The gate (G) of the second PMOS transistor is electrically connected to the positive terminal of the diode. The source (S) of the second PMOS transistor is electrically connected to the negative terminal of the diode. The negative terminal of the diode is electrically connected to the first end of the third resistor. The second end of the third resistor is electrically connected to the source (S) of the first PMOS transistor.

5. The standby power supply timing-locked fast discharge circuit according to claim 1, characterized in that, It also includes a filter circuit; The filter circuit is configured between the power supply circuit and the load.

6. An electronic device, characterized in that, Includes a standby power supply timing lock fast discharge circuit as described in any one of claims 1 to 5.

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