A three-state input detection circuit and an ultra-low power three-state input detection device

Abstract

The utility model provides a kind of tri-state input detection circuit and ultra-low power consumption tri-state input detection device, tri-state input detection circuit includes first resistance, second resistance, transistor and combination logic circuit: one end of first resistance, the control end of transistor and the first input end of combination logic circuit are detection signal input end, receive voltage signal to be detected;The level output end of combination logic circuit is detection result output end, output logic level signal, indicate the level state of voltage signal to be detected.The utility model avoids the parallel mismatch problem caused by using two transistors, while reducing wiring complexity.

Description

Technical Field

[0001] This utility model relates to the field of circuit detection technology, and in particular to a three-state input detection circuit and an ultra-low power three-state input detection device. Background Technology

[0002] like Figure 1 As shown, in a traditional three-state input detection circuit, the input high level must be greater than VDD-|VTHP1|, where VDD is the power supply voltage and VTHTP1 is the threshold voltage of P1. Furthermore, in the high-impedance state, R1 and R2 draw current, and N1 and P1 are both in the ON state, resulting in significant power consumption. In other words, if the input detection high level is less than VDD-|VTHP1|, or if extremely low power consumption in the high-impedance state is required, the traditional three-state input detection circuit cannot meet the requirements.

[0003] The prior art, patent application number CN202321204050.2 (title: An ultra-low power tri-state input detection circuit for WiFi-FEM), provides a tri-state input detection circuit including transistor P1, transistor P2, and NAND gate N1. This circuit can still operate normally when the high level input at the Vin terminal is less than VDD-|VTHP1|. However, in this patent document, transistors P1 and P2 perform signal inversion processing on the Vin terminal input to improve noise immunity, but this also results in problems such as high wiring complexity and parallel mismatch. Utility Model Content

[0004] To address the shortcomings of existing technologies, this invention provides a tri-state input detection circuit and an ultra-low power tri-state input detection device, which solves the problems of high wiring complexity and parallel mismatch in existing tri-state input detection circuits.

[0005] According to an embodiment of the present invention, a first aspect provides a three-state input detection circuit, including a first resistor, a second resistor, a transistor, and combinational logic circuitry:

[0006] One end of the first resistor, the control terminal of the transistor, and the first input terminal of the combinational logic circuit are detection signal input terminals, receiving the voltage signal to be detected; the level output terminal of the combinational logic circuit is the detection result output terminal, outputting a logic level signal to indicate the level state of the voltage signal to be detected;

[0007] The other end of the first resistor and the input terminal of the transistor are connected to the power supply voltage. The output terminal of the transistor is connected to the second input terminal of the combinational logic circuit and one end of the second resistor. The other end of the second resistor is grounded.

[0008] Optionally, the combinational logic circuit includes at least a first-level output, a second-level output, and a third-level output;

[0009] The first level output is high level, and the voltage signal to be detected is in a high level state;

[0010] The second level output is high, and the voltage signal to be detected is low.

[0011] The third level output is high level, and the voltage signal to be detected is in a high impedance state.

[0012] Optionally, the combinational logic circuit includes a decoder.

[0013] Optionally, the combinational logic circuit includes a two-to-four decoder.

[0014] Optionally, it may also include a status indication module connected to the level output terminal of the combinational logic circuit.

[0015] Alternatively, the power supply voltage may be provided by one of an LDO linear power supply, an isolated power supply, or a DC-DC power supply.

[0016] Optionally, the transistor is a PMOS transistor.

[0017] Optionally, a third resistor may also be included;

[0018] One end of the third resistor is connected to the control terminal of the transistor, and the other end of the third resistor is the detection signal input terminal.

[0019] Optionally, the transistor is a PNP transistor and further includes a third resistor, one end of which is connected to the control terminal of the transistor, and the other end of which is a detection signal input terminal.

[0020] The second aspect provides an ultra-low power tri-state input detection device, including the tri-state input detection circuit described above.

[0021] The tri-state input detection circuit provided by this invention includes only one transistor, avoiding the parallel mismatch problem caused by using two transistors, and reducing wiring complexity. Furthermore, the tri-state input detection circuit provided by this invention has low quiescent current, and the combinational logic circuit also has almost no quiescent power consumption; therefore, the overall circuit power consumption is extremely low. Attached Figure Description

[0022] Figure 1 It is a traditional three-state input detection circuit;

[0023] Figure 2 This is a schematic diagram of the circuit structure of the three-state input detection circuit according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the circuit structure of the three-state input detection circuit according to an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the circuit structure of another three-state input detection circuit according to an embodiment of the present invention. Detailed Implementation

[0026] The technical solution of this utility model will be further described below with reference to the accompanying drawings and embodiments.

[0027] like Figure 2 As shown in the figure, this utility model embodiment proposes a three-state input detection circuit, including a first resistor R1, a second resistor R2, a transistor P1, and a combinational logic circuit A.

[0028] The connection relationship of the above circuit parts is as follows: the other end of the first resistor R1 and the input terminal of transistor P1 are connected to the power supply voltage VDD, the output terminal of transistor P1 is connected to the second input terminal A2 of combinational logic circuit A and one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0029] Among them, one end of the first resistor R1, the control terminal of transistor P1, and the first input terminal A1 of the combinational logic circuit A are the detection signal input terminal IN, which receives the voltage signal to be detected; the combinational logic circuit A also includes a second input terminal A2, which receives the signal from the output terminal of transistor P1, and the level output terminal of the combinational logic circuit A is the detection result output terminal OUT. Thus, the combinational logic circuit A outputs a logic level signal according to the input signals from the first input terminal A1 and the second input terminal A2, and uses this logic level signal to represent the level state of the voltage signal to be detected.

[0030] This embodiment of the invention uses PMOS transistor P1 to describe the detailed operation of the above-mentioned three-state input detection circuit: When the detection signal input terminal IN is high, transistor P1 is turned on. At this time, the first input terminal A1 and the second input terminal A2 of the combinational logic circuit A are both high. When the detection signal input terminal IN is low, transistor P1 is turned on. At this time, the first input terminal A1 of the combinational logic circuit A is low, and the second input terminal A2 is high. When the detection signal input terminal IN is in a high-impedance state, the level signal obtained by the first input terminal A1 of the combinational logic circuit A is pulled up to VDD by the first resistor R1, and transistor P1 is turned off. At this time, the first input terminal A1 of the combinational logic circuit A is high, and the second input terminal A2 is low. The combinational logic circuit A outputs logic level signals based on the input signals from the first input terminal A1 and the second input terminal A2, namely [A1=high, A2=high], [A1=low, A2=high], and [A1=high, A2=low], respectively, representing the three different level states of the voltage signal to be detected, namely high level state, low level state, and high impedance state, thus realizing the function of three-state input detection.

[0031] It should be noted that, in the above process, the high level input at the detection signal input terminal IN must be less than VDD-|VTHP1|, where VTHP1 is the threshold voltage of transistor P1. In specific applications, the power supply voltage VDD can be provided by any one of the following: an LDO linear power supply, an isolated power supply, or a DC-DC power supply.

[0032] The tri-state input detection circuit provided by this invention includes only one transistor, avoiding the parallel mismatch problem caused by using two transistors, and reducing wiring complexity. Furthermore, the tri-state input detection circuit provided by this invention has low quiescent current, and the combinational logic circuit also has almost no quiescent power consumption; therefore, the overall circuit power consumption is extremely low.

[0033] In this embodiment of the present invention, the combinational logic circuit A includes at least a first level output, a second level output, and a third level output. The first level output, the second level output, and the third level output indicate that the combinational logic circuit A selects a level output channel to output a high-level signal based on the input signals of the first input terminal A1 and the second input terminal A2, thereby distinguishing the three different level states of the voltage signal to be detected.

[0034] For example, the first level output is high only when the input signals at the first input terminal A1 and the second input terminal A2 are [A1=high, A2=high], then the first level output is high and the voltage signal to be detected is in a high-level state; the second level output is high only when the input signals at the first input terminal A1 and the second input terminal A2 are [A1=low, A2=high], then the second level output is high and the voltage signal to be detected is in a low-level state; the third level output is high only when the input signals at the first input terminal A1 and the second input terminal A2 are [A1=high, A2=low], then the third level output is high and the voltage signal to be detected is in a high-impedance state.

[0035] In practical applications, combinational logic circuit A only needs to be able to output at least three logic level signals based on the input signals from the first input terminal A1 and the second input terminal A2, such as using a decoder with multiple outputs. Figure 3 As shown, this embodiment of the invention provides a better implementation of combinational logic circuit A, namely, combinational logic circuit A includes a 2-to-4 decoder. Table 1 below is the truth table of the 2-to-4 decoder, wherein the output terminal Y1 of the 2-to-4 decoder corresponds to the second level output shown above; the output terminal Y2 of the 2-to-4 decoder corresponds to the third level output shown above; and the output terminal Y3 of the 2-to-4 decoder corresponds to the first level output shown above. Therefore, the 2-to-4 decoder can clearly represent the three different level states of the voltage signal to be detected.

[0036] Table 1:

[0037] 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1

[0038] In a better implementation, a status indicator module, including a first status indicator unit, a second status indicator unit, and a third status indicator unit, can be connected to the output terminal OUT of the detection result of the combinational logic circuit A, corresponding one-to-one with the first level output, the second level output, and the third level output mentioned above.

[0039] In this embodiment of the invention, transistor P1 can be a PMOS transistor or a PNP transistor. When transistor P1 is a PMOS transistor, an optional solution is to further include a third resistor; when transistor P1 is a PNP transistor, a necessary solution is to include a third resistor.

[0040] like Figure 4 As shown, this utility model illustrates a scheme where transistor P1 is a PNP transistor, which, in such a way... Figure 1 Based on the tri-state input detection circuit shown, a third resistor R3 is also included. Figure 4In the circuit, one end of the third resistor R3 is connected to the control terminal of transistor P1, i.e., the base of the PNP transistor, and the other end of the third resistor R3 is the detection signal input terminal IN. The third resistor R3 is used to suppress transient impacts, eliminate oscillations, control switching speed, etc., and improve the stability of the three-state input detection circuit.

[0041] It is understandable that, such as Figure 4 The three-state input detection circuit shown is also applicable to the device types shown in the above embodiments, such as two-to-four decoders, status indicator modules, etc., which will not be described again here.

[0042] On the other hand, this utility model embodiment also provides an ultra-low power tri-state input detection device, which includes the tri-state input detection circuit shown in the above embodiment.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model and are not intended to limit it. Although this utility model has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this utility model without departing from the spirit and scope of the technical solutions of this utility model, and all such modifications or substitutions should be covered within the scope of the claims of this utility model.

Claims

1. A three-state input detection circuit, characterized in that, Includes a first resistor, a second resistor, transistors, and combinational logic circuitry: One end of the first resistor, the control terminal of the transistor, and the first input terminal of the combinational logic circuit are detection signal input terminals, receiving the voltage signal to be detected; the level output terminal of the combinational logic circuit is the detection result output terminal, outputting a logic level signal to indicate the level state of the voltage signal to be detected; The other end of the first resistor and the input terminal of the transistor are connected to the power supply voltage. The output terminal of the transistor is connected to the second input terminal of the combinational logic circuit and one end of the second resistor. The other end of the second resistor is grounded.

2. The tri-state input detection circuit as described in claim 1, characterized in that, The combinational logic circuit includes at least a first-level output, a second-level output, and a third-level output; The first level output is high level, and the voltage signal to be detected is in a high level state; The second level output is high, and the voltage signal to be detected is low. The third level output is high level, and the voltage signal to be detected is in a high impedance state.

3. The tri-state input detection circuit as described in claim 2, characterized in that, The combinational logic circuit includes a decoder.

4. The three-state input detection circuit as described in claim 2, characterized in that, The combinational logic circuit includes a two-to-four decoder.

5. The tri-state input detection circuit as described in claim 1, characterized in that, It also includes a status indication module connected to the level output terminal of the combinational logic circuit.

6. The tri-state input detection circuit as described in claim 1, characterized in that, The power supply voltage is provided by one of the following: an LDO linear power supply, an isolated power supply, or a DC-DC power supply.

7. The three-state input detection circuit as described in any one of claims 1 to 6, characterized in that, The transistor is a PMOS transistor.

8. The three-state input detection circuit as described in claim 7, characterized in that, It also includes a third resistor; One end of the third resistor is connected to the control terminal of the transistor, and the other end of the third resistor is the detection signal input terminal.

9. The three-state input detection circuit as described in any one of claims 1 to 6, characterized in that, The transistor is a PNP transistor and also includes a third resistor. One end of the third resistor is connected to the control terminal of the transistor, and the other end of the third resistor is the detection signal input terminal.

10. An ultra-low power tri-state input detection device, characterized in that, Includes the three-state input detection circuit as described in any one of claims 1 to 9.

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