A circuit board layout structure of an active inter-cell equalization board

Abstract

The utility model relates to the circuit board layout structure of active equalizing plate between electric core, and PCB board is in turn top layer, GND layer, POWER layer and bottom layer along the thickness direction, and top layer is provided with power module, CAN communication network mouth, relay, PWM controller, electric core collection mouth and first group NMOS switch, and PWM controller is arranged in top layer horizontal center area, and its grid pole drive output pin is towards first group NMOS switch, and CAN communication network mouth and relay are respectively set up in both sides of PWM controller, and power module is set up with CAN communication network mouth same side, and GND layer is provided with a plurality of first copper area, and POWER layer is provided with power supply wiring and second copper area, and bottom layer is provided with MCU and second group NMOS switch, and first group NMOS switch and second group NMOS switch equal number and are mirror image alignment up and down, are used for shortening equalizing current loop area, the utility model discloses can realize the collection and equalization of electric core, reduce the size of board, save the cost, reduce the circuit interference, improve the space utilization, and the utility model discloses are small and convenient to install.

Description

Technical Field

[0001] This utility model relates to the technical field of energy storage, and in particular to a circuit board layout structure for an active balancing board between battery cells. Background Technology

[0002] Energy storage battery packs are typically composed of multiple cells connected in series. Due to variations in manufacturing processes, operating temperature gradients, and aging rates, the voltage and capacity of each cell may differ during cycling. If these differences are allowed to increase, individual cells may be overcharged or over-discharged, reducing the overall usable capacity of the pack, shortening cycle life, and even causing safety accidents.

[0003] To maintain cell consistency, existing technologies employ passive balancing schemes, which dissipate excess charge from high-energy cells as heat through resistive discharge. While simple in structure, this approach is inefficient, generates significant heat, and cannot recover energy. Active balancing technology, on the other hand, utilizes energy storage components such as inductors, capacitors, or transformers to transfer charge from high-energy cells to low-energy cells. This offers advantages such as high energy utilization and low temperature rise, and has become the development direction for mid-to-high-end energy storage systems.

[0004] However, active equalization boards require a large number of power switches, drive circuits, sampling and communication devices to be arranged within a limited area. Existing layouts generally suffer from the following drawbacks: The equalization current loop area is large, resulting in severe high-frequency interference between channels; Power devices are scattered irregularly, resulting in low heat dissipation and space utilization. Incomplete ground / power planes and common impedance coupling cause signal crosstalk. The decoupling path is long, resulting in poor power integrity for the MCU and driver chip.

[0005] Therefore, a circuit board layout structure for an active balancing board between battery cells is needed to address the shortcomings of existing technologies. Utility Model Content

[0006] Therefore, the technical problem to be solved by this utility model is to overcome the shortcomings of the prior art and provide a circuit board layout structure for an active equalization board between battery cells, which can realize the collection and equalization of battery cells, reduce the board size, save costs, reduce circuit interference, improve space utilization, and is compact and easy to install. While reducing the board size, it can also shorten the equalization current loop, reduce inter-channel coupling, and improve system reliability.

[0007] To solve the above technical problems, this utility model provides a circuit board layout structure for an active balancing board between battery cells, characterized in that it includes a PCB board, wherein the PCB board consists of a top layer, a GND layer, a POWER layer and a bottom layer along the thickness direction. The top layer includes a power module, a CAN communication port, a relay, a PWM controller, a battery cell acquisition port, and a first group of NMOS switches. The PWM controller is located in the horizontal center of the top layer, with its gate drive output pin facing the first group of NMOS switches. The CAN communication port and the relay are located on opposite sides of the PWM controller. The power module is located on the same side as the CAN communication port. The GND layer is provided with several first copper-paved areas; The POWER layer has power traces and a second copper plating area to provide uniform current distribution.

[0008] The underlying layer includes an MCU and a second set of NMOS switches; The first group of NMOS switches and the second group of NMOS switches have the same number of switches and are mirror-aligned vertically to shorten the area of ​​the equalization current loop.

[0009] In one embodiment of this utility model, the spacing between the first copper-paved areas is greater than 20 mil.

[0010] In one embodiment of this utility model, the first group of NMOS switches and the second group of NMOS switches each include 8 switches, for a total of 16 NMOS switches corresponding to 16 strings of cells, forming a one-to-one equalization channel.

[0011] In one embodiment of this utility model, four of the first group of NMOS switches are arranged equidistantly along the long side of the PCB board, and the other four are arranged equidistantly along the short side of the PCB board, forming an "L" shaped layout.

[0012] In one embodiment of this invention, the power traces and the second copper plating area of ​​the POWER layer are configured to provide a uniform current distribution to the 16 battery cells.

[0013] In one embodiment of this utility model, a decoupling capacitor is provided next to the power supply pin of the MCU, and the first pad of the decoupling capacitor is connected to the power supply pin of the MCU through a lead.

[0014] In one embodiment of this invention, the second pad of the decoupling capacitor is connected to GND or power supply via a lead or via.

[0015] In one embodiment of this utility model, the decoupling capacitor and the MCU are located on the same layer and the distance between them is no more than 2mm.

[0016] In one embodiment of this utility model, the battery cell acquisition port includes two sets of pin headers, which are connected to external battery cells to achieve battery cell acquisition and active balancing.

[0017] In one embodiment of this utility model, the CAN communication port is arranged near the edge of the PCB board.

[0018] Compared with the prior art, the above-mentioned technical solution of this utility model has the following beneficial effects: The circuit board layout structure of the active balancing board between battery cells described in this utility model can realize the acquisition and balancing of battery cells, reduce board size, save costs, reduce circuit interference, improve space utilization, and is compact and easy to install; and while reducing the board size, it can also shorten the balancing current loop, reduce inter-channel coupling, and improve system reliability. Attached Figure Description

[0019] To make the content of this utility model easier to understand, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings. Figure 1 This is a schematic diagram of the circuit board layout structure of the active balancing board between battery cells in a preferred embodiment of this utility model; Figure 2 This is a schematic diagram of the top layer structure of this utility model; Figure 3 This is a schematic diagram of the GND layer structure of this utility model; Figure 4 This is a schematic diagram of the POWER layer structure of this utility model; Figure 5 This is a schematic diagram of the underlying structure of this utility model; Explanation of reference numerals in the instruction manual: 1. PCB board; 2. Power module; 3. CAN communication port; 4. Relay; 5. PWM controller; 6. Battery cell acquisition port; 7. First group of NMOS switches; 8a. Power trace; 8b. Second copper pour area; 9. MCU; 10. Second group of NMOS switches; 11. First copper pour area. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments are not intended to limit the present invention.

[0021] Reference Figure 1-5 As shown, the circuit board layout structure of the active balancing board between battery cells of this utility model includes: PCB board 1, which has a top layer, a GND layer, a POWER layer and a bottom layer in sequence along the thickness direction. The top layer includes a power module 2, a CAN communication port 3, a relay 4, a PWM controller 5, a battery cell acquisition port 6, and a first set of NMOS switches 7. The PWM controller 5 is located in the horizontal center area of ​​the top layer, with its gate drive output pin facing the first set of NMOS switches 7. The CAN communication port 3 and the relay 4 are respectively located on both sides of the PWM controller 5. The power module 2 is located on the same side as the CAN communication port 3. The POWER layer has power traces 8a and a second copper plating area 8b to provide uniform current distribution and reduce voltage fluctuations. The GND layer has several first copper-poured areas 11; The underlying setup includes an MCU9 and a second set of NMOS switches 10; The first group of NMOS switches 7 and the second group of NMOS switches 10 are equal in number and mirror-aligned vertically to shorten the area of ​​the equalization current loop.

[0022] In this embodiment, the four-layer PCB board 1 typically uses the top and bottom layers as signal layers to facilitate connections between components; the middle GND and POWER layers serve as reference planes, providing a continuous, low-impedance return path for high-speed or power signals.

[0023] In the above structure, PCB board 1 is divided into four layers: top layer, GND layer, POWER layer, and bottom layer. Within a limited board area, the first group of NMOS switches 7 and the second group of NMOS switches 10 can be integrated and mirrored, allowing for vertical interconnection of balanced current, significantly shortening the loop area and reducing parasitic inductance and spikes. Simultaneously, the power module 2, CAN communication port 3, and relay 4 are concentrated on the top layer, while the bottom layer has a dedicated MCU 9. This reduces cross-layer routing, improves space utilization, simplifies installation, and achieves efficient, compact, and low-interference active balancing functionality.

[0024] The spacing between adjacent first copper pour areas 11 is greater than 20 mil. The first copper pour area 11 of the GND layer maintains a gap of >20 mil, which forms a continuous reference plane while meeting the safety creepage distance requirements, reducing ground impedance and ground bounce noise, and improving the return integrity of high-speed equalization pulses.

[0025] Both the first group of NMOS switches 7 and the second group of NMOS switches 10 include 8 switches each, for a total of 16 NMOS switches, each corresponding to one of the 16 battery cells, forming a one-to-one equalization channel. The 16 NMOS switches correspond one-to-one with the 16 battery cells, and the hardware channels are independent, avoiding timing competition caused by multiplexing; the mirror alignment ensures that the heat dissipation area of ​​the top and bottom layers is equal, resulting in a more uniform heat distribution.

[0026] Four NMOS switches in the first group 7 are arranged equidistantly along the long side of PCB 1, and the other four are arranged equidistantly along the short side of PCB 1, forming an "L" shape. This 4-horizontal and 4-vertical "L" shape layout makes full use of the corner space, shortens the gate drive traces, and the gate traces of the horizontal and vertical groups naturally converge on one side of the PWM controller 5. Equal-length drive reduces turn-on time difference, and the power copper and signal traces are automatically separated to reduce cross-interference. The "L" shape of the first group of NMOS switches 7 releases heat to the control and interface devices in the central area, and the heat is diffused laterally through the plane of the POWER layer and GND layer, avoiding local hot spots. At the same time, it reduces the length of the peripheral wiring harness and the need for shielding, achieving a highly integrated, compact, and easy-to-install active balancing function.

[0027] Furthermore, the power traces 8a and the second copper plating area 8b of the POWER layer are configured to provide a uniform current distribution to the 16 cells.

[0028] Furthermore, a decoupling capacitor 12 is placed next to the power supply pin of MCU9. The first pad of the decoupling capacitor 12 is connected to the power supply pin of MCU9 via a lead. The first pad of the decoupling capacitor 12 is directly adjacent to the power supply pin of MCU9, which shortens the initial power supply path, reduces the first-stage parasitic inductance, provides transient charge to MCU9, and reduces the interference of power supply glitches on digital logic.

[0029] The second pad of the decoupling capacitor is connected to GND or power supply via leads and vias. The second pad of the decoupling capacitor is directly inserted into the GND / power plane through the same layer of leads and vias, forming a low-impedance discharge channel of "capacitor-via-plane". The high-frequency current generated during equalization switching can be immediately returned, suppressing the outward radiation of power supply noise.

[0030] In this embodiment, the decoupling capacitor and MCU9 are located on the same layer and the distance between them is no more than 2 mm.

[0031] Furthermore, the battery cell acquisition port 6 includes two sets of pin headers, which connect to external battery cells to achieve battery cell acquisition and active balancing.

[0032] In this embodiment, the CAN communication port 3 is arranged near the edge of the PCB board 1. The wiring harness can be inserted directly into the PACK side slot at a 90° angle, eliminating the need for plastic bridges and copper pillars for positioning. The metal casing also functions as a micro heat sink, keeping the CAN transceiver away from the central heat zone and doubling its lifespan. At the same time, the test points and programming ports are fully exposed on the board edge, allowing for immediate testing with a clip after sales, thus reducing production line cycle time and BOM costs.

[0033] Based on the above-mentioned active equalization board layout structure, the acquisition and equalization between 16 strings of cells can be realized, saving costs, reducing circuit interference, improving space utilization, and being compact and easy to install.

[0034] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the protection scope of this invention.

Claims

1. A circuit board layout structure for an active balancing board between battery cells, characterized in that, The PCB board includes a top layer, a GND layer, a POWER layer, and a bottom layer in sequence along the thickness direction. The top layer includes a power module, a CAN communication port, a relay, a PWM controller, a battery cell acquisition port, and a first group of NMOS switches. The PWM controller is located in the horizontal center of the top layer, with its gate drive output pin facing the first group of NMOS switches. The CAN communication port and the relay are located on opposite sides of the PWM controller. The power module is located on the same side as the CAN communication port. The GND layer is provided with several first copper-paved areas; The POWER layer is provided with power traces and a second copper plating area to provide uniform current distribution. The underlying layer includes an MCU and a second set of NMOS switches; The first group of NMOS switches and the second group of NMOS switches have the same number of switches and are mirror-aligned vertically to shorten the area of ​​the equalization current loop.

2. The circuit board layout structure of the cell-to-cell active balancing board according to claim 1, characterized in that, The spacing between adjacent first copper-paved areas on the GND layer is greater than 20 mil.

3. The circuit board layout structure of the cell-to-cell active balancing board according to claim 1, characterized in that, The first group of NMOS switches and the second group of NMOS switches each include 8 switches, for a total of 16 NMOS switches corresponding to 16 strings of cells, forming a one-to-one equalization channel.

4. The circuit board layout structure of the active balancing board between battery cells according to claim 3, characterized in that, Four of the NMOS switches in the first group are arranged horizontally at equal intervals along the long side of the PCB board, and the other four are arranged vertically at equal intervals along the short side of the PCB board, forming an "L" shaped layout.

5. The circuit board layout structure of the active balancing board between battery cells according to claim 1, characterized in that, The power traces and second copper plating area of ​​the POWER layer are configured to provide a uniform current distribution to the 16 cells.

6. The circuit board layout structure of the cell-to-cell active balancing board according to claim 1, characterized in that, A decoupling capacitor is provided next to the power supply pin of the MCU, and the first pad of the decoupling capacitor is connected to the power supply pin of the MCU through a lead.

7. The circuit board layout structure of the cell-to-cell active balancing board according to claim 6, characterized in that, The second pad of the decoupling capacitor is connected to GND or power supply via a lead or via.

8. The circuit board layout structure of the cell-to-cell active balancing board according to claim 6, characterized in that, The decoupling capacitor is located on the same layer as the MCU and the distance between them is no more than 2 mm.

9. The circuit board layout structure of the cell-to-cell active balancing board according to claim 1, characterized in that, The cell acquisition port includes two sets of pin headers, which are connected to external cells for cell acquisition and active balancing.

10. The circuit board layout structure of the cell-to-cell active balancing board according to claim 1, characterized in that: The CAN communication port is located near the edge of the PCB board.

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