Printed circuit board and electronic device

Abstract

The utility model embodiment provides a kind of printed circuit board and electronic equipment.Printed circuit board includes at least two substrates, which are sequentially stacked, each dielectric layer is located between two first conductive layers, the conductive medium is filled in the through hole of dielectric layer setting, the conductive medium and each first conductive layer contact, each first conductive layer is electrically connected to the first conductive layer of the first substrate of the first layer substrate in stacking direction by conductive medium;Plug hole penetrates each substrate along the stacking direction, plug hole is inserted with plug pin, the first conductive layer of the first layer substrate is welded by fixing piece and plug pin, and the plug pin is electrically connected to the first conductive layer of the first substrate of the first layer substrate in stacking direction at least.The wiring of each substrate can be introduced to the first conductive layer of the first layer substrate by conductive medium, and the electrical connection position of plug pin and the first conductive layer of the first layer substrate can be ensured with fixing piece, to ensure the stability of connection.

Description

Technical Field

[0001] This utility model relates to the field of circuit board manufacturing technology, and in particular to a printed circuit board and electronic equipment. Background Technology

[0002] Electronic devices typically include printed circuit boards (PCBs). To increase the integration density of PCBs, multiple conductive layers are stacked to achieve complex wiring within a limited space.

[0003] Typically, printed circuit boards (PCBs) can be configured with connector pins that penetrate multiple conductive layers and establish electrical connections between them, thus enabling cross-layer electrical connections. However, since the tightness of the electrical connection between the inner conductive layers and the connector pins cannot be visually assessed, the connection can easily break due to external forces during connector pin soldering or rework / reassembly. This can affect the stability of the electrical connection between the connector pins and the various conductive layers. Utility Model Content

[0004] To solve or partially solve the above problems, this utility model discloses a printed circuit board and electronic device to address the problem that the inner conductive layer and the plug-in pins are easily disconnected due to external force during the soldering or rework process of plug-in pins in the prior art.

[0005] To address the aforementioned problems, in a first aspect, embodiments of this application provide a printed circuit board, comprising:

[0006] At least two substrate layers are stacked sequentially. Each substrate layer includes a dielectric layer and a first conductive layer on the surface of the dielectric layer. Each dielectric layer is located between two first conductive layers. The dielectric layer is provided with a through hole, which is filled with a conductive medium. The conductive medium is in contact with each first conductive layer. Each first conductive layer is electrically connected to the first conductive layer of the first substrate layer in the stacking direction through the conductive medium.

[0007] The insertion hole penetrates each layer of the substrate along the stacking direction, and the insertion pin is inserted into the insertion hole. The first conductive layer of the first layer of the substrate in the stacking direction is soldered to the insertion pin through a fastener. The insertion pin is electrically connected to at least the first conductive layer of the first layer of the substrate in the stacking direction.

[0008] Optionally, one of the vias penetrates each of the dielectric layers.

[0009] Optionally, the via includes a first sub-via and a second sub-via offset along the stacking direction, wherein the first sub-via penetrates at least the dielectric layer including the first layer of the substrate, and the second sub-via penetrates the dielectric layers included in the remaining other substrates.

[0010] Optionally, the through hole includes a third sub-hole and a first through hole;

[0011] The third sub-hole penetrates at least the dielectric layer including the first substrate layer, and the first through-hole is located on one side of the third sub-hole, penetrating the dielectric layer included in each substrate layer.

[0012] Optionally, both the through hole and the plug-in hole are circular holes, and the diameter of the through hole is smaller than that of the plug-in hole.

[0013] Optionally, the diameter of the through hole is less than or equal to 0.5 mm and greater than or equal to 0.2 mm.

[0014] Optionally, in the stacking direction, the first layer of the substrate includes a first conductive layer and the plug-in pins electrically connected by a second conductive layer, the second conductive layer being disposed on the wall of the plug-in hole.

[0015] Optionally, the second conductive layer and the first substrate layer in the stacking direction are disposed in the same layer as the first conductive layer.

[0016] Optionally, the second conductive layer covers the hole wall of the plug-in hole.

[0017] Secondly, embodiments of this application provide an electronic device, which includes the printed circuit board described in any embodiment of the first aspect.

[0018] In this embodiment, each substrate layer includes a dielectric layer and a first conductive layer on the surface of the dielectric layer. Each dielectric layer is located between two first conductive layers. The dielectric layer has a via, which is filled with a conductive medium. The conductive medium is in contact with each first conductive layer. Therefore, through the conductive medium in the via, each first conductive layer can be electrically connected to the first conductive layer of the first substrate layer in the stacking direction. That is, the traces of each substrate layer can be introduced to the first conductive layer of the first substrate layer in the stacking direction through the conductive medium. Furthermore, since the insertion hole penetrates each substrate layer along the stacking direction, and the insertion hole contains an insertion pin, the first conductive layer of the first substrate layer in the stacking direction is soldered to the insertion pin through a fixing member. The insertion pin is electrically connected to at least the first conductive layer of the first substrate layer in the stacking direction. Therefore, it can be ensured that the electrical connection position between the insertion pin and the first conductive layer of the first substrate layer in the stacking direction has a fixing member. That is, the electrical connection position between the insertion pin and the first conductive layer will not fall off at least at the location of the fixing member. In other words, the connection position between the insertion pin and the first conductive layer can be prevented from breaking through the fixing member. In summary, in the embodiments of this application, even if the plug-in pins are displaced due to external force during the soldering or rework of the plug-in pins, the traces of each substrate can be introduced to the first conductive layer of the first substrate in the stacking direction through the conductive medium. Furthermore, the electrical connection stability between the first conductive layer of the first substrate in the stacking direction and the plug-in pins will remain stable due to the setting of the fixing component, thereby ensuring that each first conductive layer can stably establish an electrical connection with the plug-in pins. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This represents one of the cross-sectional views of a printed circuit board provided in an embodiment of this application;

[0021] Figure 2 This is a second cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0022] Figure 3 This is a third cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0023] Figure 4 This is the fourth cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0024] Figure 5 This is the fifth cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0025] Figure 6 This is the sixth cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0026] Figure 7 This is the seventh cross-sectional view of a printed circuit board provided in an embodiment of this application;

[0027] Figure 8 This is the eighth cross-sectional view of a printed circuit board provided in an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1: Substrate; 11: Dielectric layer; 12: First conductive layer; 13: Through hole; 131: First sub-hole; 132: Second sub-hole; 133: Third sub-hole; 134: First through hole; 14: Conductive dielectric; 15: Insertion hole; 151: Second conductive layer; 2: Insertion pin; 3: Fixing component. Detailed Implementation

[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0031] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0032] like Figure 1 As shown, the printed circuit board includes:

[0033] At least two substrates 1 are stacked sequentially. Each substrate 1 includes a dielectric layer 11 and a first conductive layer 12 on the surface of the dielectric layer 11. Each dielectric layer 11 is located between two first conductive layers 12. The dielectric layer 11 is provided with a through hole 13. The through hole 13 is filled with a conductive medium 14. The conductive medium 14 is in contact with each first conductive layer 12. Each first conductive layer 12 is electrically connected to the first conductive layer 12 included in the first substrate 1 in the stacking direction through the conductive medium 14.

[0034] Insertion hole 15, insertion hole 15 penetrates each substrate 1 along the stacking direction, insertion pin 2 is inserted into insertion hole 15, the first conductive layer 12 of the first substrate 1 in the stacking direction is welded to insertion pin 2 by fastener 3, and insertion pin 2 is electrically connected to at least the first conductive layer 12 of the first substrate 1 in the stacking direction.

[0035] As can be seen from the above embodiments, since each substrate 1 includes a dielectric layer 11 and a first conductive layer 12 on the surface of the dielectric layer 11, each dielectric layer 11 is located between two first conductive layers 12, the dielectric layer 11 is provided with a via 13, the via 13 is filled with a conductive medium 14, the conductive medium 14 is in contact with each first conductive layer 12, so that each first conductive layer 12 can be electrically connected to the first conductive layer 12 included in the first substrate 1 in the stacking direction through the conductive medium 14 of the via 13, that is, the traces of each substrate 1 can be introduced to the first conductive layer 12 included in the first substrate 1 in the stacking direction through the conductive medium 14. Furthermore, since the insertion hole 15 penetrates each substrate 1 along the stacking direction, and the insertion pin 2 is inserted into the insertion hole 15, the first conductive layer 12 of the first substrate 1 in the stacking direction is welded to the insertion pin 2 through the fastener 3. The insertion pin 2 is electrically connected to the first conductive layer 12 of the first substrate 1 in the stacking direction. Therefore, it can be ensured that the electrical connection position between the insertion pin 2 and the first conductive layer 12 of the first substrate 1 in the stacking direction has the fastener 3. That is, the electrical connection position between the insertion pin 2 and the first conductive layer 12 will not fall off at least at the position where the fastener 3 is located. In other words, the connection position between the insertion pin 2 and the first conductive layer 12 can be prevented from breaking through the fastener 3. In summary, in the embodiments of this application, during the soldering or rework of the plug-in pin 2, even if the plug-in pin 2 is displaced due to external force, the traces of each substrate 1 can be introduced to the first conductive layer 12 of the first substrate 1 in the stacking direction through the conductive medium 14. The electrical connection stability between the first conductive layer 12 of the first substrate 1 in the stacking direction and the plug-in pin 2 will also remain stable due to the setting of the fixing member 3, thereby ensuring that each first conductive layer 12 can stably establish an electrical connection with the plug-in pin 2.

[0036] In the above embodiments, the dielectric layer 11 is an insulating material compartment separating the conductive layer. The dielectric layer 11 can be any one of glass fiber reinforced epoxy resin, polyimide, low-k material, high-k material, etc. The first conductive layer 12 can include at least one of copper foil, copper plating, tin plating, silver paste, graphene, carbon nanotube, etc., and this application embodiment does not limit the choice of materials. The conductive layer and the dielectric layer 11 are alternately arranged along the stacking direction, forming a "sandwich" structure of first conductive layer 12-dielectric layer 11-conductive layer. The dielectric layer 11 has through holes 13, which can be a single through hole structure, multiple through hole structures, or a combination of blind holes and through holes, and this application embodiment does not limit the choice of materials. The via 13 needs to penetrate through multiple layers of substrate 1. After filling the via 13 with conductive medium 14, the conductive medium 14 can contact each first conductive layer 12, thereby allowing each first conductive layer 12 to be traced through the conductive medium 14, and finally conductively connected to the first conductive layer 12 included in the first layer of substrate 1 in the stacking direction. The conductive medium 14 can be any of the following materials: copper foil, copper plating, tin plating, silver paste, graphene, carbon nanotubes, etc., and this application embodiment does not limit it.

[0037] The insertion hole 15 needs to penetrate each substrate 1 along the stacking direction. The insertion pin 2 is soldered to the first conductive layer 12 of the first substrate 1 in the stacking direction by a fixing member 3. The fixing member 3 can be solder, sintered silver material, or other soldering fixing member 3. In this way, the electrical connection position between the insertion pin 2 and the first conductive layer 12 is the position where the fixing member 3 is located, which is the most securely fixed position between the insertion pin 2 and the multilayer substrate 1. Therefore, when the traces of each substrate 1 can be introduced to the first conductive layer 12 of the first substrate 1 in the stacking direction through the conductive medium 14, it can be ensured that each first conductive layer 12 can be traced to the insertion pin 2 through the first conductive layer 12 of the first substrate 1. It should be noted that the stacking direction in this embodiment is as follows: Figure 1 As shown in Z in the diagram.

[0038] In some embodiments, such as Figure 1 and Figure 2 As shown, a via 13 penetrates each dielectric layer 11.

[0039] In this embodiment, since a via 13 penetrates each dielectric layer 11, the conductive medium 14 in the via can be electrically connected to the first conductive layer 12 included in each dielectric layer 11. That is, by setting a via 13, the traces of multiple first conductive layers 12 can be guided to the first conductive layer 12 of the first substrate 1 in the stacking direction. This not only helps to reduce the difficulty of opening via 13 on the printed circuit board, but also reduces the manufacturing cost of the printed circuit board.

[0040] It should be noted that, as Figure 1 As shown, a through hole 13 can be opened on either side of the insertion hole 15 along the first direction X, such as... Figure 2 As shown, through holes 13 can also be formed on both sides of the insertion hole 15 along the first direction X, and this embodiment of the application does not limit this. When through holes 13 are formed on both sides of the insertion hole 15 along the first direction X, the conductive medium 14 in the through hole 13 on one side of the insertion hole 15 along the first direction X can guide the wiring of at least the first conductive layer 12 including the first substrate 1, and the conductive medium 14 in the through hole 13 on the other side of the insertion hole along the first direction X can guide the wiring of the first conductive layer 12 of the remaining substrate 1. This allows the multiple first conductive layers 12 to have two wiring paths, thereby reducing the wiring difficulty and avoiding mutual interference of the wiring.

[0041] In some embodiments, such as Figure 3 and Figure 4 As shown, the via 13 includes a first sub-hole 131 and a second sub-hole 132 that are offset along the stacking direction. The first sub-hole 131 penetrates at least the dielectric layer 11 included in the first substrate 1, and the second sub-hole 132 penetrates the dielectric layer 11 included in the remaining other substrates 1.

[0042] In this embodiment, since the via 13 includes a first sub-via 131 and a second sub-via 132 staggered along the stacking direction, the first sub-via 131 penetrates at least the dielectric layer 11 including the first substrate 1, and the second sub-via 132 penetrates the dielectric layers 11 included in the remaining substrates 1, the first conductive layer 12 including the first substrate 1 can be traced through the dielectric layer 11 in the first sub-via 131, and the first conductive layers 12 included in the remaining substrates 1 can be traced through the dielectric layer 11 in the second sub-via 132 to the first conductive layer 12 at the middle position, and then traced from the first conductive layer 12 to the first sub-via 131. This also allows for the connection of multiple layers of first conductive layers 12 to the first conductive layer 12 of the first substrate 1. For example, taking a printed circuit board including three substrates 1 as an example... Figure 3 As shown, the first sub-hole 131 can penetrate the dielectric layer 11 of the first substrate 1, and the second sub-hole 132 simultaneously penetrates the dielectric layers 11 of both the intermediate substrate 1 and the bottom substrate 1, or as shown... Figure 4As shown, the first sub-hole 131 can penetrate the dielectric layer 11 of the first substrate 1 and the intermediate substrate 1, and the second sub-hole 132 can penetrate the dielectric layer 11 of the bottom substrate 1. The first substrate 1 and the intermediate substrate 1 can be traced through the first conductive layer 12 on their surfaces to the conductive dielectric 14 in the first sub-hole 131, and then traced to the first conductive layer 12 on the surface of the first substrate 1. The bottom substrate 1 can be traced through the first conductive layer 12 on its surface to the conductive dielectric 14 in the second sub-hole 132, and then traced to the first conductive layer 12 on the surface of the intermediate substrate 1. Finally, the conductive dielectric 14 in the first sub-hole 131 traces back to the first conductive layer 12 on the surface of the first substrate 1. In this way, the routing methods of the multiple first conductive layers 12 can be enriched, thereby reducing the routing difficulty.

[0043] In some embodiments, such as Figure 5 , Figure 6 and Figure 7 As shown, the via 13 includes a third sub-via 133 and a first through-via 134. The third sub-via 133 penetrates at least the dielectric layer 11 including the first substrate 1. The first through-via 134 is located on one side of the third sub-via 133 and penetrates the dielectric layer 11 included in each substrate 1.

[0044] In this embodiment, since the third sub-hole 133 penetrates at least the dielectric layer 11 including the first substrate 1, and the first through-hole 134 is located on one side of the third sub-hole 133, and the first through-hole 134 penetrates the dielectric layer 11 included in each substrate 1, the first conductive layer 12 including the first substrate 1 is routed through the dielectric layer 11 in the third sub-hole 133. The remaining first conductive layers 12 included in other substrates 1 are routed through the dielectric layer 11 in the first through-hole 134 to the first conductive layer 12 at the middle position, and then routed from the first conductive layer 12 to the first sub-hole 131. This also allows for the routing of multiple first conductive layers 12 to the first conductive layer 12 of the first substrate 1, enriching the routing methods of multiple first conductive layers 12 and thus reducing routing difficulty. For example, taking a printed circuit board including three substrate layers 1 as an example... Figure 5 As shown, the third sub-hole 133 can penetrate the dielectric layer 11 of the first substrate 1, and the first through-hole 134 simultaneously penetrates the dielectric layers 11 of all substrates 1. Thus, the first substrate 1 is routed through the conductive medium 14 in the third sub-hole 133 to the first conductive layer 12 on its surface. The first conductive layers 12 on the surfaces of the intermediate substrates 1 and the bottom substrate 1 are routed to the conductive medium 14 in the first through-hole 134, and finally, the conductive medium 14 in the first through-hole 134 routes to the first conductive layer 12 on the surface of the first substrate 1. Alternatively, as... Figure 6As shown, the third sub-hole 133 can penetrate the dielectric layer 11 of the first substrate 1 and the intermediate substrate 1, and the first through-hole 134 penetrates the dielectric layer 11 of all substrates 1. The first substrate 1 is traced to the first conductive layer 12 on its surface through the conductive dielectric 14 in the third sub-hole 133. The first conductive layer 12 of the intermediate substrate 1 is traced to the first conductive layer 12 on the surface of the first substrate 1 through the conductive dielectric 14 in the third sub-hole 133 or the first through-hole 134. The first conductive layer 12 on the surface of the bottom substrate 1 is traced to the conductive dielectric 14 in the first through-hole 134, and finally traced to the first conductive layer 12 on the surface of the first substrate 1 through the conductive dielectric 14 in the first through-hole 134.

[0045] It should be noted that, as Figure 5 and Figure 6 As shown, the third sub-hole 133 and the first through hole 134 can be located on the same side of the insertion hole 15 along the first direction X, such as... Figure 7 As shown, the third sub-hole 133 and the first through hole 134 can be disposed on different sides of the plug-in hole 15 along the first direction X, and this application embodiment does not limit this.

[0046] In some embodiments, both the through hole 13 and the insertion hole 15 are circular holes, and the diameter of the through hole 13 is smaller than that of the insertion hole 15.

[0047] In this embodiment, since both the via hole 13 and the insertion hole 15 are circular holes, and the diameter of the via hole 13 is smaller than that of the insertion hole 15, it is easier to prepare the via hole 13 and it is beneficial to reduce the loss of effective area of ​​the printed circuit board caused by the opening of the via hole 13.

[0048] In some embodiments, the diameter of the via 13 is less than or equal to 0.5 mm and greater than or equal to 0.2 mm. This ensures the dimensional specifications of the via 13 and further reduces the loss of effective area of ​​the printed circuit board caused by the via 13.

[0049] In some embodiments, such as Figure 1 and Figure 8 As shown, in the stacking direction, the first substrate 1 includes a first conductive layer 12 and a plug pin 2 which are electrically connected by a second conductive layer 151. The second conductive layer 151 is disposed on the hole wall of the plug hole 15.

[0050] In this embodiment, since the first substrate 1 in the stacking direction includes a first conductive layer 12 and a plug pin 2 electrically connected by a second conductive layer 151, and the second conductive layer 151 is disposed on the hole wall of the plug hole 15, the second conductive layer 151 facilitates the electrical connection between the plug pin 2 and the first conductive layer 12, and at the same time helps to ensure the stability of the electrical connection between the plug pin 2 and the first conductive layer 12.

[0051] In some embodiments, such as Figure 8 As shown, the second conductive layer 151 and the first substrate 1 in the stacking direction include the first conductive layer 12 and are disposed in the same layer.

[0052] In this embodiment, since the second conductive layer 151 and the first substrate 1 including the first conductive layer 12 are disposed in the same layer in the stacking direction, the second conductive layer 151 is only disposed between the first substrate 1 including the first conductive layer 12 and the plug pin 2. This avoids the second conductive layer 151 being disposed on other substrate layers 1 of the printed circuit board, thereby reducing the area of ​​the first conductive layer 12 disposed on the hole wall of the plug hole 15, and thus reducing the manufacturing cost of the printed circuit board.

[0053] In some embodiments, such as Figures 1 to 7 As shown, the second conductive layer 151 covers the hole wall of the plug hole 15.

[0054] In this embodiment, since the second conductive layer 151 covers the hole wall of the insertion hole 15, the hole wall of the insertion hole 15 is provided with the second conductive layer 151. This facilitates the fabrication of the second conductive layer 151 on the hole wall while allowing each first conductive layer 12 to be electrically connected to the second conductive layer 151. Therefore, without separation between the first conductive layer 12 and the second conductive layer 151 of each layer, the first conductive layer 12 of other substrates 1 besides the first conductive layer 12 of the first substrate 1 can either be routed through the conductive medium 14 filled in the through hole 13 or directly routed to the second conductive layer 151 through the first conductive layer 12, further enriching the routing paths.

[0055] As can be seen from the above embodiments, since each substrate 1 includes a dielectric layer 11 and a first conductive layer 12 on the surface of the dielectric layer 11, each dielectric layer 11 is located between two first conductive layers 12, the dielectric layer 11 is provided with a via 13, the via 13 is filled with a conductive medium 14, the conductive medium 14 is in contact with each first conductive layer 12, so that each first conductive layer 12 can be electrically connected to the first conductive layer 12 included in the first substrate 1 in the stacking direction through the conductive medium 14 of the via 13, that is, the traces of each substrate 1 can be introduced to the first conductive layer 12 included in the first substrate 1 in the stacking direction through the conductive medium 14. Furthermore, since the insertion hole 15 penetrates each substrate 1 along the stacking direction, and the insertion pin 2 is inserted into the insertion hole 15, the first conductive layer 12 of the first substrate 1 in the stacking direction is welded to the insertion pin 2 through the fastener 3. The insertion pin 2 is electrically connected to the first conductive layer 12 of the first substrate 1 in the stacking direction. Therefore, it can be ensured that the electrical connection position between the insertion pin 2 and the first conductive layer 12 of the first substrate 1 in the stacking direction has the fastener 3. That is, the electrical connection position between the insertion pin 2 and the first conductive layer 12 will not fall off at least at the position where the fastener 3 is located. In other words, the connection position between the insertion pin 2 and the first conductive layer 12 can be prevented from breaking through the fastener 3. In summary, in the embodiments of this application, during the soldering or rework of the plug-in pin 2, even if the plug-in pin 2 is displaced due to external force, the traces of each substrate 1 can be introduced to the first conductive layer 12 included in the first substrate 1 in the stacking direction through the conductive medium 14. The electrical connection stability between the first conductive layer 12 included in the first substrate 1 in the stacking direction and the plug-in pin 2 will also remain stable due to the setting of the fixing member 3, thereby ensuring that each first conductive layer 12 can stably establish an electrical connection with the plug-in pin 2.

[0056] This application provides an electronic device that includes the printed circuit board in any of the above embodiments.

[0057] It should be noted that, in the embodiments of this application, the electronic device includes, but is not limited to, controllers, smart devices, terminal products, etc., wherein smart devices include, for example, smartphones, smart TVs, smart speakers, smart robots, Volta R devices, AR devices, XR devices, etc., and terminal products include, for example, personal computers, tablet computers, etc. The beneficial effects of this electronic device are the same as those of the printed circuit board described above, and will not be repeated in the embodiments of this application.

[0058] The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0059] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0060] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0061] The present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A printed circuit board, characterized in that, include: At least two substrate layers are stacked sequentially. Each substrate layer includes a dielectric layer and a first conductive layer on the surface of the dielectric layer. Each dielectric layer is located between two first conductive layers. The dielectric layer has a via, which is filled with a conductive medium. The conductive medium is in contact with each first conductive layer. Each first conductive layer is electrically connected to the first conductive layer of the first substrate layer in the stacking direction through the conductive medium. The stacking direction is the direction in which at least two substrate layers are stacked. The insertion hole penetrates each layer of the substrate along the stacking direction. An insertion pin is inserted into the insertion hole. The first conductive layer of the first layer of the substrate in the stacking direction is soldered to the insertion pin through a fastener. The insertion pin is electrically connected to at least the first conductive layer of the first layer of the substrate in the stacking direction.

2. The printed circuit board according to claim 1, characterized in that, One of the vias penetrates each of the dielectric layers.

3. The printed circuit board according to claim 1, characterized in that, The via includes a first sub-via and a second sub-via offset along the stacking direction. The first sub-via penetrates at least the dielectric layer including the first layer of the substrate, and the second sub-via penetrates the dielectric layers included in the remaining substrates.

4. The printed circuit board according to claim 1, characterized in that, The through hole includes a third sub-hole and a first through hole; The third sub-hole penetrates at least the dielectric layer including the first substrate layer, and the first through-hole is located on one side of the third sub-hole, penetrating the dielectric layer included in each substrate layer.

5. The printed circuit board according to claim 1, characterized in that, Both the through hole and the plug-in hole are circular holes, and the diameter of the through hole is smaller than that of the plug-in hole.

6. The printed circuit board according to claim 5, characterized in that, The diameter of the through hole is less than or equal to 0.5 mm and greater than or equal to 0.2 mm.

7. The printed circuit board according to claim 1, characterized in that, The first layer of the substrate in the stacking direction includes a first conductive layer and the plug pins electrically connected by a second conductive layer, the second conductive layer being disposed on the wall of the plug hole.

8. The printed circuit board according to claim 7, characterized in that, The second conductive layer and the first layer of the substrate in the stacking direction are disposed in the same layer as the first conductive layer.

9. The printed circuit board according to claim 7, characterized in that, The second conductive layer covers the hole wall of the plug-in hole.

10. An electronic device, characterized in that, The electronic device includes the printed circuit board according to any one of claims 1 to 9.

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