A trench gate silicon carbide vdmos for 2kV and above

Abstract

The utility model provides a kind of for 2kV above trench gate silicon carbide VDMOS, comprising: drift layer is connected to silicon carbide substrate;Insulating dielectric layer is connected to drift layer;Schottky metal layer is connected to drift layer, Schottky metal layer outside is connected to insulating dielectric layer inside;P-type well region is connected to drift layer, P-type well region outside is connected to Schottky metal layer inside, P-type well region inside is connected to current-sharing layer;N-type source region is connected to P-type well region, N-type source region outside is connected to Schottky metal layer inside;Insulating dielectric layer outside is connected P-type well region and N-type source region respectively, and insulating dielectric layer is equipped with groove inside;Gate metal layer is located in groove;Source metal layer is connected N-type source region and Schottky metal layer respectively;Drain metal layer is connected to silicon carbide substrate, realize the small cell of device under 2kV above voltage resistance condition, high current density, low on-resistance.

Description

Technical Field

[0001] This utility model relates to a trench gate silicon carbide VDMOS for voltages above 2kV. Background Technology

[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally have high withstand voltage compared to Si VDMOS devices. However, in fields such as high-voltage power transmission, the structure of traditional silicon carbide VDMOS devices cannot meet the withstand voltage requirements of devices above 2kV. This leads to increasing the withstand voltage by sacrificing device size and on-resistance, which affects the device characteristics. Summary of the Invention

[0003] The technical problem to be solved by this utility model is to provide a trench gate silicon carbide VDMOS for voltages above 2kV, which achieves small cell size, high current density and low on-resistance under voltage conditions above 2kV.

[0004] In a first aspect, this utility model provides a trench-gate silicon carbide VDMOS for voltages above 2kV, comprising: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a first groove is provided on the drift layer; A flow equalization layer is provided in the lower part of the flow equalization layer within a first groove. The flow equalization layer is provided with a shielding layer and a second groove, with the shielding layer located at the bottom of the second groove. An isolation dielectric layer, wherein the lower side of the isolation dielectric layer is connected to the upper side of the drift layer; A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, and the outer side of the Schottky metal layer is connected to the inner side of the isolation dielectric layer; The P-type well region has its lower side connected to the upper side of the drift layer, its outer side connected to the inner side of the Schottky metal layer, and its inner side connected to the equalization layer. The N-type source region has its lower side connected to the upper side of the P-type well region, and its outer side connected to the inner side of the Schottky metal layer. An insulating dielectric layer is provided at its lower part within a second groove. The outer surface of the insulating dielectric layer is connected to a P-type well region and an N-type source region, respectively. A trench is provided within the insulating dielectric layer. A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the N-type source region and the Schottky metal layer respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0005] Secondly, this utility model provides a trench gate silicon carbide VDMOS for voltages above 2kV, wherein the silicon carbide VDMOS is prepared by the preparation method of the trench gate silicon carbide VDMOS for voltages above 2kV described in the first aspect.

[0006] The advantages of this utility model are: I. This utility model constructs a symmetrical structure of isolation medium, Schottky metal, P-type well region, and gate structure. The newly added isolation medium can realize direct isolation between device cells and suppress the diffusion of electric field to the cell edge under high drain voltage conditions above 2kV, thereby increasing the cell density of silicon carbide VDMOS on trench above 2kV. Second, an N-type current-equalizing layer wrapped with a P-type shielding layer is constructed at the bottom of the device trench gate. While ensuring gate reliability under a withstand voltage of over 2kV, a low-resistance path from the N-type source to the JFET region is provided, thereby reducing the on-resistance of the device. Third, to meet the withstand voltage requirements of 2kV and above, a thick P-type well region and a narrow conductive channel (the width of the N-type current sharing region distributed on both sides of the insulating medium is only 100nm) structure is adopted, thereby reducing the on-resistance of the device while ensuring the withstand voltage capability of the device. Fourth, a Schottky metal is constructed inside the isolation medium of the device, and the constructed Schottky body diode completes low-resistance freewheeling in the non-conducting state of the device. Attached Figure Description

[0007] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0008] Figure 1 This is a schematic diagram of a trench gate silicon carbide VDMOS for voltages above 2kV according to the present invention.

[0009] Figure 2 This is a cross-sectional view of the process of a trench-gate silicon carbide VDMOS for voltages above 2kV according to this utility model. Figure 1 .

[0010] Figure 3 This is a cross-sectional view of the process of a trench-gate silicon carbide VDMOS for voltages above 2kV according to this utility model. Figure 2 .

[0011] Figure 4 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 3 .

[0012] Figure 5 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 4 .

[0013] Figure 6 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 5 .

[0014] Figure 7 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 6 .

[0015] Figure 8 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 7 .

[0016] Figure 9 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 8 .

[0017] Figure 10 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 9 .

[0018] Figure 11 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 10 .

[0019] Figure 12 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 10 one.

[0020] Figure 13 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 10 two.

[0021] Figure 14 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 10 three.

[0022] Figure 15 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 10 Four.

[0023] Figure 16 This is a cross-sectional view of the process for a trench-gate silicon carbide VDMOS with a voltage of 2kV or higher according to this utility model. Figure 10 five. Detailed Implementation

[0024] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0027] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0028] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0029] like Figure 1 As shown, this application embodiment provides a trench-gate silicon carbide VDMOS for voltages above 2kV, comprising: Silicon carbide substrate 101, A drift layer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101, and a first groove (not shown in the figure) is provided on the drift layer 102. A flow equalization layer 103 is provided in a first groove at its lower part. A shielding layer 1031 and a second groove (not shown in the figure) are provided in the flow equalization layer 103. The shielding layer 1031 is located at the bottom of the second groove. An isolation medium layer 104, the lower side of which is connected to the upper side of the drift layer 102; Schottky metal layer 105, the lower side of which is connected to the upper side of drift layer 102, and the outer side of which is connected to the inner side of isolation medium layer 104; P-type well region 106, the lower side of the P-type well region 106 is connected to the upper side of the drift layer 102, the outer side of the P-type well region 106 is connected to the inner side of the Schottky metal layer 105, and the inner side of the P-type well region 106 is connected to the flow equalization layer 103. N-type source region 107, the lower side of which is connected to the upper side of P-type well region 106, and the outer side of which is connected to the inner side of Schottky metal layer 105; An insulating dielectric layer 108 is provided at its lower part in a second groove. The outer side of the insulating dielectric layer 108 is connected to a P-type well region 106 and an N-type source region 107, respectively. A groove 1081 is provided in the insulating dielectric layer 108. A gate metal layer 109 is disposed within the trench 1081; Source metal layer 110, which is connected to N-type source region 107 and Schottky metal layer 105 respectively; And a drain metal layer 111, which is connected to the lower side of the silicon carbide substrate 101.

[0030] In this embodiment, preferably, the doping concentration of the current equalization layer 103 is greater than the doping concentration of the drift layer 102.

[0031] In this embodiment, preferably, the doping concentration of the current equalization layer 103 is less than or equal to the doping concentration of the shielding layer 1031.

[0032] In this embodiment, preferably, the width of the shielding layer 1031 is equal to the width of the insulating dielectric layer 108.

[0033] In this embodiment, preferably, the doping concentration of the current equalization layer 103 is less than the doping concentration of the P-type well region 106.

[0034] In this embodiment, preferably, the silicon carbide substrate 101, the drift layer 102, and the current equalization layer 103 are all N-type, and the shielding layer 1031 is P-type.

[0035] like Figures 1 to 16 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 111; epitaxially grow a drift layer 102 on the upper side of silicon carbide substrate 101; Step 2: Form a barrier layer 112 above the drift layer 102, etch the barrier layer 112 to form vias, and perform ion implantation to form a flow equalization layer 103; Step 3: Ion implantation to form the first well region 1061; Step 4: Ion implantation to form a shielding layer 1031; Step 5: Ion implantation to form a second well region 1062. The P-type well region 106 includes a first well region 1061 and a second well region 1062. Step 6: Ion implantation to form an N-type source region 107; Step 7: Etch the drift layer to form the first trench 113, and then deposit it to form the isolation dielectric layer 104; Step 8: Etch the drift layer to form the second trench 114, then deposit metal to form the Schottky metal layer 105; Step 9: Etch the drift layer 102 and the shielding layer 1031 to form the third groove 115, and oxidize to form an insulating dielectric layer 108, wherein the insulating dielectric layer 108 is provided with trenches 1081; Step 10: Deposit metal to form gate metal layer 109; Step 11: Etch the drift layer to form the third trench 116, deposit metal to form the source metal layer 110; Before steps 3 to 11, the barrier layer 112 from the previous step needs to be removed, and the barrier layer 112 is etched to form a through hole.

[0036] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 6-10e15cm. -3 The doping concentration of the N-type current-averaging layer 103 is 6-10e16cm. -3 The doping concentration of the P-type shielding layer 1031 is 1-5e17cm. -3 The doping concentration of the P-type well region 106 is 6-10e17cm. -3 The material of the isolation dielectric layer 104 can be silicon dioxide, the material of the insulating dielectric layer 108 can be silicon dioxide, and the doping concentration of the N-type source region 107 is 2-8e18cm. -3 ; The doping concentration of the N-type silicon carbide substrate 101 is designed to ensure a low-resistance ohmic contact with the drain metal layer 111, reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 represents a trade-off between the device's reverse breakdown voltage and on-resistance. The doping concentration of the N-type current sharing layer 103 is designed to reduce the device's on-resistance. Its relationship with the doping concentration of the P-type shielding layer 1031 ensures the protective effect of the P-type shielding layer 1031 on the device's gate insulating dielectric layer 108. The doping concentration of the P-type shielding layer 1031 is designed to improve the reliability of the bottom of the device's gate insulating dielectric layer 108, ensuring that the leakage current is sufficiently small during reverse breakdown, shielding the capacitance from the device's gate to the drain, and reducing the device's Miller capacitance. The doping concentration of the P-type well region 106 is designed to protect the device's source metal layer 110, ensuring its breakdown voltage capability during reverse breakdown. The doping concentration of the N-type source region 107 is designed to reduce the device's contact resistance, thereby reducing the device's on-resistance. Since trench-gate silicon carbide VDMOS devices above 2kV require thick epitaxy, the silicon carbide substrate thickness is designed to be 1.5μm to ensure support during device fabrication. The N-type drift layer 102 has a thickness of 150-300μm, and the device withstand voltage range is 2kV-4.5kV, adjusted within this range according to different requirements for device withstand voltage characteristics. The source metal layer 110 has a thickness of 300nm and a width of 800nm, the N-type source region 107 has a thickness of 200nm and a width of 800nm, the P-type well region 106 has a maximum thickness of 1.5μm and a width of 800nm, the Schottky metal layer 105 has a thickness of 2μm and a width of 300nm, the isolation dielectric layer 104 has a thickness of 2μm and a width of 300nm, and the thickness of the P-type well region 106 is designed for withstand voltage requirements above 2kV. The design is based on a high-density cell design of the device based on the shielding structure of the isolation dielectric layer 104 and the Schottky metal layer 105. The device insulating dielectric layer 108 has a width of 1μm and a thickness of 1μm. The gate metal layer 109 has a width of 900nm and a thickness of 900nm. The bottom thickness of the insulating dielectric layer 108 is 100nm, and the thickness on the left and right sides is 50nm. The P-type shielding layer 1031 has a width of 1μm and a thickness of 300nm. This is to ensure the protection of the insulating dielectric layer 108 at the bottom of the device gate. The N-type current sharing layer 103 has a width of 1.4μm and a thickness of 1μm. This is to ensure that there is a 200nm conductive channel width on the left and right sides of the device gate control region. A low-resistance region unaffected by the P-type well region 106 is constructed at the bottom of the device P-type well region 106, which effectively reduces the on-resistance of the device.

[0037] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A trench-gate silicon carbide VDMOS for voltages above 2kV, characterized in that: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a first groove is provided on the drift layer; A flow equalization layer is provided in the lower part of the flow equalization layer within a first groove. The flow equalization layer is provided with a shielding layer and a second groove, with the shielding layer located at the bottom of the second groove. An isolation dielectric layer, wherein the lower side of the isolation dielectric layer is connected to the upper side of the drift layer; A Schottky metal layer, wherein the lower side of the Schottky metal layer is connected to the upper side of the drift layer, and the outer side of the Schottky metal layer is connected to the inner side of the isolation dielectric layer; The P-type well region has its lower side connected to the upper side of the drift layer, its outer side connected to the inner side of the Schottky metal layer, and its inner side connected to the flow equalization layer. The N-type source region has its lower side connected to the upper side of the P-type well region, and its outer side connected to the inner side of the Schottky metal layer. An insulating dielectric layer is provided at its lower part in a second groove. The outer side of the insulating dielectric layer is connected to a P-type well region and an N-type source region, respectively. The insulating dielectric layer is provided with grooves. A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the N-type source region and the Schottky metal layer respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The trench-gate silicon carbide VDMOS for voltages above 2kV as described in claim 1, characterized in that: The doping concentration of the current equalization layer is greater than that of the drift layer.

3. The trench-gate silicon carbide VDMOS for voltages above 2kV as described in claim 1, characterized in that: The doping concentration of the current equalization layer is less than or equal to the doping concentration of the shielding layer.

4. The trench-gate silicon carbide VDMOS for voltages above 2kV as described in claim 1, characterized in that: The width of the shielding layer is equal to the width of the insulating dielectric layer.

5. A trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the current equalization layer is less than that of the P-type well region.

6. A trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The silicon carbide substrate, drift layer, and current equalization layer are all N-type, and the shielding layer is P-type.

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