4.5kv super junction trench gate silicon carbide vdmos
Patent Information
- Application Number
- CN202522177678.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-15
- Publication Date
- 2026-10-16
- Estimated Expiration
- 2035-10-15
AI Technical Summary
[0002]碳化硅VDMOS器件由于其宽禁带特性，相比Si VDMOS器件天然具备高耐压的特点，但是在高压输电等领域，传统碳化硅VDMOS器件的结构难以实现4.5kV高耐压和低导通电阻的兼具
一、本实用新型构建了P型区与屏蔽层的超结器件结构，在器件反向耐压时，在器件底部构建漂移层和P型区的横向空间电荷区耐压，在器件顶部构建屏蔽层和低阻区的横向空间电荷区耐压，可以在有限的元胞体积条件下提高器件的耐压能力；
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Figure CN224863304U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a 4.5kV superjunction trench gate silicon carbide VDMOS. Background Technology
[0002] Due to its wide bandgap characteristics, silicon carbide VDMOS devices naturally possess high voltage withstand capability compared to Si VDMOS devices. However, in fields such as high-voltage power transmission, the structure of traditional silicon carbide VDMOS devices makes it difficult to achieve both a high voltage withstand capability of 4.5kV and low on-resistance. Summary of the Invention
[0003] The technical problem to be solved by this utility model is to provide a 4.5kV superjunction trench gate silicon carbide VDMOS. By using the superjunction trench gate structure of the upper and lower layers of the device, the withstand voltage of the device is increased to 4.5kV while ensuring low on-resistance.
[0004] In a first aspect, this utility model provides a 4.5kV superjunction trench gate silicon carbide VDMOS, comprising: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a P-type region is provided in the drift layer; The lower side of the P+ region is connected to the P-type region; A low-resistivity region, the lower side of which is connected to the drift layer, and the outer side of which is connected to the inner side of the P+ region; A shielding layer, wherein the lower side of the shielding layer is connected to the upper side of the drift layer, and the outer side of the shielding layer is connected to the inner side of the low-resistivity region; The lower side of the P-type well region is connected to the low-resistivity region, and the outer side of the P-type well region is connected to the inner side of the P+ region. The N-type source region has its lower side connected to the upper side of the P-type well region, and its outer side connected to the inner side of the P+ region. An insulating dielectric layer is provided, the lower side of which is connected to a shielding layer, and the outer side of which is connected to the inner side of the low-resistivity region, the inner side of the P-type well region, and the inner side of the N-type source region, respectively; the insulating dielectric layer is provided with trenches. A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P+ region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
[0005] The advantages of this utility model are: I. This utility model constructs a superjunction device structure with a P-type region and a shielding layer. When the device is reverse withstand voltage, a drift layer and a lateral space charge region of the P-type region are constructed at the bottom of the device to withstand voltage, and a shielding layer and a low-resistivity region are constructed at the top of the device to withstand voltage. This can improve the withstand voltage capability of the device under the condition of limited cell volume. Second, the shielding layer of this utility model can protect the gate of the device and avoid electric field concentration during reverse withstand voltage, which could lead to gate reliability problems. Third, this utility model constructs a conductive channel of N-type source region-P-type well region-low resistance region. The design of the low resistance region can effectively reduce the JFET region resistance of the device and reduce the on-resistance of the device. Fourth, the P+ region of this utility model can effectively conduct the source potential to the shielding gate and the P-type region, reduce the electric field strength inside the device, and improve the reliability of the device. Attached Figure Description
[0006] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0007] Figure 1 This is a schematic diagram of a 4.5kV superjunction trench gate silicon carbide VDMOS according to the present invention.
[0008] Figure 2 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 1 .
[0009] Figure 3 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 2 .
[0010] Figure 4 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 3 .
[0011] Figure 5 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 4 .
[0012] Figure 6 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 5 .
[0013] Figure 7 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 6 .
[0014] Figure 8This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 7 .
[0015] Figure 9 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 8 .
[0016] Figure 10 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 9 .
[0017] Figure 11 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 10 .
[0018] Figure 12 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 10 one.
[0019] Figure 13 This is a cross-sectional view of the process of a 4.5kV superjunction trench gate silicon carbide VDMOS according to this utility model. Figure 10 two. Detailed Implementation
[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0023] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0024] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0025] like Figures 1 to 13 As shown, this application embodiment provides a 4.5kV superjunction trench gate silicon carbide VDMOS, comprising: Silicon carbide substrate 101, A drift layer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101, and a P-type region 1021 is provided in the drift layer 102; P+ region 103, the lower side of which is connected to P-type region 1021; Low-resistivity region 104, the lower side of which is connected to drift layer 102, and the outer side of which is connected to the inner side of P+ region 103; The shielding layer 105 has its lower side connected to the upper side of the drift layer 102, and its outer side connected to the inner side of the low-resistance region 104. P-type well region 106, the lower side of the P-type well region 106 is connected to the low resistance region 104, and the outer side of the P-type well region 106 is connected to the inner side of the P+ region 103. N-type source region 107, the lower side of the N-type source region 107 is connected to the upper side of the P-type well region 106, and the outer side of the N-type source region 107 is connected to the inner side of the P+ region 103; An insulating dielectric layer 108 is provided, the lower side of which is connected to a shielding layer 105, and the outer side of which is connected to the inner side of the low-resistivity region 104, the inner side of the P-type well region 106, and the inner side of the N-type source region 107, respectively; a trench 1081 is provided in the insulating dielectric layer 108. A gate metal layer 109 is disposed within the trench 1081; Source metal layer 110, which is connected to the P+ region 103 and the N-type source region 107 respectively; And a drain metal layer 111, which is connected to the lower side of the silicon carbide substrate 101.
[0026] In this embodiment, preferably, the doping concentration of the P-type region 1021 is greater than or equal to the doping concentration of the drift layer 102, and the doping concentration of the P+ region 103 is greater than the doping concentration of the P-type region 1021.
[0027] In this embodiment, preferably, the width of the P-type region 1021 is equal to the width of the P+ region 103.
[0028] In this embodiment, preferably, the doping concentration of the low-resistivity region 104 is greater than the doping concentration of the drift layer 102, and the doping concentration of the low-resistivity region 104 is greater than the doping concentration of the P-type well region 106.
[0029] In this embodiment, preferably, the widths of the low-resistivity region 104, the P-type well region 106, and the N-type source region 107 are equal.
[0030] In this embodiment, preferably, the doping concentration of the low-resistivity region 104 is less than the doping concentration of the shielding layer 105.
[0031] In this embodiment, preferably, the width of the shielding layer 105 is equal to the width of the insulating dielectric layer 108.
[0032] like Figures 1 to 13 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 111, and epitaxially grow on the upper side of silicon carbide substrate 101 to form drift layer 102. Step 2: Form a barrier layer 112 above the drift layer 102, etch the barrier layer 112 to form a via, and implant ions to form a P-type region 1021; Step 3: Remove the blocking layer 112 from step 2, and epitaxially grow on the drift layer 102 to form an epitaxial layer 113; Step 4: Form a barrier layer 112 on the epitaxial layer 113, etch the barrier layer 112 to form a via, and implant ions to form a P+ region 103. Step 5: Ion implantation to form a P-type shielding layer 105; Step 6: Ion implantation to form an N-type low-resistivity region 104; Step 7: Ion implantation to form a P-type well region 106; Step 8: Ion implantation to form N-type source region 107; Step 9: Etch the epitaxial layer 113 to form a groove 1131, and oxidize the groove 1131 to form an insulating dielectric layer 108, wherein the insulating dielectric layer 108 has a trench 1081. Step 10: Deposit metal to form gate metal layer 109; Step 11: Etch epitaxial layer 113, then deposit metal to form source metal layer 110, remove barrier layer 112, and complete the fabrication; Before steps 5, 6, 9 to 11, the barrier layer 112 from the previous step needs to be removed and the barrier layer 112 is etched to form a through hole.
[0033] In another embodiment of this invention, the silicon carbide substrate 101, the drift layer 102, and the low-resistivity region 104 are all N-type, and the shielding layer 105 is P-type; the N-type silicon carbide substrate is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 6-10e16cm. -3 The doping concentration of the P-type region 1021 is 1-5e17cm. -3 The doping concentration of P+ region 103 is 1-5e18cm. -3 The doping concentration of the N-type low-resistivity region 104 is 6-10e17cm.-3 The doping concentration of the P-type shielding layer 105 is 1-5e18cm. -3 The doping concentration of the P-type well region 106 is 1-5e16cm. -3 The insulating dielectric layer 108 can be made of silicon dioxide, and the doping concentration of the N-type source region 107 is 2-8e¹⁸cm⁻¹. -3 The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 111, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 and the P-type region 1021 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. Their concentration relationship can ensure the lateral and longitudinal diffusion relationship of the space charge region of the pn junction of the device, realize the superjunction structure of the device, and thus ensure that the device has both breakdown voltage and low on-resistance. The doping concentration of P+ region 102 is to ensure that the device forms a gradually changing junction near the source and gate regions when the device is reverse breakdown voltage, thereby improving the breakdown voltage capability of the source and gate of the device and improving the reliability of the device. The doping concentration of the N-type low-resistance region 104 is to reduce the on-resistance of the device from the N-type source region 107 through the gate control region to the device JFET region. The P-type shielding layer 105 serves two purposes: first, to ensure the protection effect of the P-type shielding layer 105 on the gate insulating medium of the device, improve the reliability of the bottom of the gate insulating medium of the device, ensure that the leakage current is small enough when the device is reverse withstand voltage, shield the capacitance from the gate to the drain of the device, and reduce the Miller capacitance of the device; second, to form a lateral pn junction structure with the N-type low-resistance region 104 of the device, and to build a combined lateral and longitudinal withstand voltage structure in the part of the device near the gate, so as to ensure both the withstand voltage capability and the on-resistance of the device. The P-type well region 106 is used to form the gate control structure of the device and realize the trench gate control of the device; The doping concentration of the P-type shielding layer 105 and the N-type low-resistivity region 104 is higher than that of the P-type region 1021 and the N-type drift layer 102. This is to reduce the diffusion rate of the space charge region of the pn junction near the gate when the drain withstand voltage is applied, thereby ensuring the gate and source withstand voltage of the device and improving the device reliability. Because 4.5kV trench-gate silicon carbide VDMOS devices require thick epitaxy, the N-type silicon carbide substrate 101 is designed to be 1.2μm thick to ensure support during device fabrication. The N-type drift layer 102 is 100μm thick, the device withstand voltage is 4.5kV, the source metal layer 110 is 300nm thick and 1.6μm wide, the N-type source region 107, P-type well region 106, and N-type low-resistivity region 104 are all 800nm wide, the N-type source region 107 is 300nm thick, the P-type well region 106 is 300nm thick, the N-type low-resistivity region 104 is 800nm thick, the P+ region 103 is 800nm wide and 1.4μm thick, and the insulating dielectric layer 108 is 1μm wide with a maximum thickness of 1.1μm. The gate metal layer 109 has a width of 900 nm and a thickness of 1 μm. The lower side of the gate metal layer 109 is 100 nm lower than the lower side of the P-type well region 106. This is to ensure the gate control capability of the device and to ensure low resistance characteristics when the device is turned on. The P-type shielding layer 105 has a width of 1 μm and a thickness of 600 nm, forming a lateral space charge region withstand voltage structure. The insulating dielectric layer 108 has a bottom thickness of 100 nm and a thickness of 50 nm on the left and right sides. This is to form the gate control capability on the left and right sides of the device. The P-type region 1021 has a width of 800 nm and a thickness of 60-80 μm. This is to form the potential transfer from the source metal layer 110 to the P+ region 103 to the P-type region 1021, ensuring the lateral and longitudinal combined space charge region withstand voltage structure of the device.
[0034] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A 4.5kV superjunction trench gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, and a P-type region is provided in the drift layer; The lower side of the P+ region is connected to the P-type region; A low-resistivity region, the lower side of which is connected to the drift layer, and the outer side of which is connected to the inner side of the P+ region; A shielding layer, wherein the lower side of the shielding layer is connected to the upper side of the drift layer, and the outer side of the shielding layer is connected to the inner side of the low-resistivity region; The lower side of the P-type well region is connected to the low-resistivity region, and the outer side of the P-type well region is connected to the inner side of the P+ region. The N-type source region has its lower side connected to the upper side of the P-type well region, and its outer side connected to the inner side of the P+ region. An insulating dielectric layer, the lower side of which is connected to a shielding layer, and the outer side of which is connected to the inner side of the low-resistivity region, the inner side of the P-type well region, and the inner side of the N-type source region, respectively. The insulating dielectric layer has grooves inside; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is connected to the P+ region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. A 4.5kV superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type region is greater than or equal to the doping concentration of the drift layer, and the doping concentration of the P+ region is greater than the doping concentration of the P-type region.
3. A 4.5kV superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the P-type region is equal to the width of the P+ region.
4. A 4.5kV superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the low-resistivity region is greater than that of the drift layer, and the doping concentration of the low-resistivity region is greater than that of the P-type well region.
5. A 4.5kV superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The widths of the low-resistivity region, the P-type well region, and the N-type source region are equal.
6. A 4.5kV superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration in the low-resistivity region is less than that in the shielding layer.
7. A 4.5kV superjunction trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the shielding layer is equal to the width of the insulating dielectric layer.