A silicon carbide mosfet chip with built-in protection unit

Abstract

The utility model provides a kind of silicon carbide MOSFET chip of built-in protection unit, it is related to power semiconductor device technical field, including N type silicon carbide substrate and N type epitaxial layer on it, active region is successively divided into cell area, protection unit area and terminal area on plane, multiple parallel MOSFET cells are formed in cell area;Protection unit area is located between cell area and terminal area, and is electrically isolated with cell area by dielectric isolation groove or junction terminal extension;P+ doped region and N+ doped region laterally adjacent with it are formed in N type epitaxial layer in protection unit area, P+ doped region and N+ doped region realize ohmic contact with upper source metal layer through same contact opening, and source metal layer is continuously extended above protection unit area and is electrically connected with N+ source area in cell area.The scheme provides internal discharge path for gate-source overvoltage under the premise of keeping silicon carbide MOSFET process flow basically unchanged, and it is beneficial to improve the operation reliability of chip.

Description

Technical Field

[0001] This utility model relates to the field of power semiconductor device technology, and in particular to a silicon carbide MOSFET chip with a built-in protection unit. Background Technology

[0002] Silicon carbide MOSFET chips are characterized by high voltage withstand capability, good high-temperature stability, and fast switching speed, and have been widely used in electric vehicle drives, photovoltaic inverters, and industrial power supplies. These chips typically employ a structure in which an N-type drift layer is epitaxially grown on an N-type silicon carbide substrate. A large number of parallel MOSFET cells are arranged in the central region of the chip, and a termination region is set at the periphery of the chip to withstand the edge electric field and improve the blocking voltage.

[0003] During long-term operation and system debugging, the gate-source terminals may experience overvoltage stress caused by drive circuitry, electrostatic discharge, and electromagnetic interference. Due to the thin gate oxide thickness and high operating electric field, if there is a lack of an effective discharge path between the gate and source, local potential concentration can easily form inside the chip, thus affecting gate oxide reliability. Existing solutions either add external protection devices to the package or at the board level, or utilize simplified doped regions near the termination area or pads inside the chip to form a discharge path to share the overvoltage current to some extent. However, external solutions are significantly affected by parasitic parameters such as lead inductance, resulting in longer response paths; internal simplified protection regions still have room for improvement in terms of their placement, electrical isolation from the cell region, and connection method with the source metal. Utility Model Content

[0004] To overcome the shortcomings of existing technologies, the technical problem to be solved by this utility model is to propose a silicon carbide MOSFET chip with a built-in protection unit, and the following technical solution is adopted: This utility model provides a silicon carbide MOSFET chip with a built-in protection unit, comprising: An N-type silicon carbide substrate and an N-type epitaxial layer formed on the substrate; The cell region is located within the active region of the epitaxial layer, and a plurality of parallel MOSFET cells are formed in the cell region. And a terminal region arranged outside the aforementioned cell region, the aforementioned terminal region being used to withstand the electric field at the edge of the chip; A protection unit region for gate-source protection is provided between the aforementioned cell region and the aforementioned terminal region. The aforementioned protection unit region is electrically isolated from the aforementioned cell region by an isolation structure. Within the aforementioned protective unit region, a P+ doped region that cooperates with the aforementioned N-type epitaxial layer and an N+ doped region adjacent to the aforementioned P+ doped region are formed. The aforementioned P+ doped region and the aforementioned N+ doped region are in ohmic contact with the source metal layer covering the aforementioned cell region and the aforementioned protective unit region through the same contact opening. The aforementioned source metal layer extends continuously above the aforementioned protective unit region and is electrically connected to the N+ source region within the aforementioned cell region.

[0005] As a further improvement, the aforementioned protective unit areas are arranged in strips or in intervals along the outer edge of the aforementioned cell areas on the plane, forming a closed or nearly closed protective band surrounding the aforementioned cell areas.

[0006] As a further improvement, the P+ doped region in the above-mentioned protection unit region, the above-mentioned N-type epitaxial layer, the P-type body region located at the edge of the above-mentioned cell region, and the above-mentioned N+ doped region are stacked sequentially in the vertical direction to form multiple alternating PN junctions, so as to form a multi-junction conduction path between the above-mentioned source metal layer and the above-mentioned N-type epitaxial layer.

[0007] As a further improvement, multiple P+ field limiting rings are arranged along the periphery of the chip in the aforementioned terminal area. The innermost P+ field limiting ring is connected to the P+ doped region in the aforementioned protection unit area on the plane, forming an integrated P-type ring band. One side of the aforementioned P-type ring band is adjacent to the aforementioned cell region, and the other side is adjacent to the terminal area where the remaining field limiting rings are located.

[0008] As a further improvement, the above isolation structure is a dielectric isolation trench that penetrates the dielectric layer above the gate dielectric and extends into the above N-type epitaxial layer. The sidewalls and / or bottom of the above dielectric isolation trench are provided with field plates electrically connected to the gate electrode. The field plates extend between the above cell region and the above protection unit region and partially cover one side of the above terminal region.

[0009] As a further improvement, the contact opening is formed in a narrow strip shape on the plane along the direction parallel to the source metal layer strip. The contact opening spans both the P+ doped region and the N+ doped region in the protection unit region in the length direction, and extends at least one cell pitch along the periphery of the chip.

[0010] As a further improvement, a polysilicon field plate or a metal field plate electrically connected to the gate electrode is provided in the aforementioned terminal area, and the aforementioned field plate extends laterally above the terminal area outside the aforementioned protection unit area.

[0011] As a further improvement, a drain metal layer is formed on the back side of the aforementioned N-type silicon carbide substrate, and the drain metal layer is connected to the substrate through an ohmic contact formed by laser annealing.

[0012] Compared with the prior art, the beneficial effects of this utility model are: Firstly, this invention forms an independent protection unit region between the cell region and the termination region, and is electrically isolated from the cell region through an isolation structure. The protection unit region is located between the cell region and the termination region, and internally forms a P+ doped region that cooperates with the N-type epitaxial layer and an adjacent N+ doped region. Both are in ohmic contact with the source metal layer through a unified contact opening. This region is electrically isolated from the cell region through dielectric isolation trenches or junction terminations. While providing a gate-source overvoltage discharge path, it confines the conduction range of the protection unit to the protection unit region, which helps to reduce the impact on the normal conduction characteristics of the cell region.

[0013] Secondly, in this invention, the protective unit region is arranged in a strip-like pattern along the outer edge of the cell region and cooperates with the P-type field-limiting ring of the terminal region, which is beneficial to the distribution of electric field and current. The protective unit region is arranged continuously or segmentally in a strip-like pattern along the outer edge of the cell region on the plane, so that the protective function basically covers the boundary of the cell region in the circumferential range. The innermost P+ field-limiting ring and the P+ doped region in the protective unit region are connected on the plane to form a continuous P-type ring band, which not only facilitates the completion of the two regions in the same P-type ion implantation, but also facilitates the smooth transition of potential between the terminal region and the protective unit region, making the electric field distribution in the terminal region more uniform.

[0014] Thirdly, this invention employs a strip-shaped contact opening that spans both the P+ and N+ doped regions, facilitating the formation of a low-resistance conduction path and improving carrier extraction. The contact opening in the guard cell region is designed as a long, narrow strip parallel to the source metal strip, simultaneously exposing both the P+ and N+ doped regions along its length, with ohmic contact achieved by the same source metal layer. This arrangement increases the effective length of the metal-semiconductor contact, reduces the series resistance of the guard cell region, and provides a more continuous extraction channel for carriers within the region after surge subsidence, thus aiding in the restoration of a stable operating state.

[0015] Fourth, the terminal region of this invention features a field plate connected to the gate potential and a back drain metal layer formed by laser annealing, which improves overall withstand voltage and conduction performance. The terminal region is equipped with a polysilicon field plate or a metal field plate electrically connected to the gate electrode. The field plate extends laterally above the terminal region outside the protection unit region, working together with the terminal doped region to improve the electric field distribution on the terminal surface. The back of the chip forms an ohmic contact with the N-type substrate through metal deposition and laser annealing, which helps reduce drain contact resistance and ensures conduction performance during high-current operation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a longitudinal structural cross-sectional view of the present invention.

[0018] Figure label: 101 - N-type silicon carbide substrate; 102 - N-type epitaxial layer; 103 - P-type body region; 104 - N+ source region; 105 - P+ doped region; 106 - gate; 107 - gate dielectric layer; 108 - source metal layer; 109 - drain metal layer. Detailed Implementation

[0019] To facilitate understanding by those skilled in the art, the structure of this utility model will now be described in further detail with reference to the accompanying drawings: The embodiments of this utility model are described below with reference to the accompanying drawings. This utility model is not limited to the specific embodiments described below; aspects not described in detail can be implemented using conventional methods in the art.

[0020] This invention provides a silicon carbide MOSFET chip with a built-in protection unit. The chip includes an N-type silicon carbide substrate 101 and an N-type silicon carbide epitaxial layer formed on the substrate. The active region is divided in a plane into a cell region in the middle, a terminal region on the outer side, and a protection unit region disposed between the cell region and the terminal region. Multiple parallel MOSFET cells are arranged in the cell region at periodic pitch to handle the switching of the main power current. The terminal region is provided with a field-limiting ring or other terminal doped region to withstand the electric field at the chip edge and improve the blocking capability.

[0021] The protection unit region is electrically isolated from the cell region through an isolation structure. This isolation structure can be a dielectric isolation trench or a junction termination extension region. Within the protection unit region, a P+ doped region 105 is formed in the N-type epitaxial layer 102, and an N+ doped region laterally adjacent to it is formed on one side of the P+ doped region 105. The P+ doped region 105 and the N+ doped region achieve ohmic contact with the upper source metal layer 108 through the same contact opening. The source metal layer 108 is connected above the cell region to conductive areas such as the N+ source region 104 and electrode lead-out pads within the cell region, and extends continuously above the protection unit region. This arrangement ensures that both the P+ doped region 105 and the N+ doped region within the protection unit region are connected to the source potential, providing a conduction path for subsequent surge currents.

[0022] In one embodiment, the protection unit area is arranged in a strip shape along the outer edge of the cell area. The strip can be continuously formed into a closed loop around the cell area, or it can be segmented according to the chip size and process requirements. However, it extends basically along the outline of the cell area on the plane, thereby forming a coverage area within the circumferential range of the cell area, which facilitates the extraction of surges from different directions into the protection unit area.

[0023] In a vertical cross-section, the P+ doped region 105 within the protection unit region and the underlying N-type epitaxial layer 102 together form a PN junction. Laterally, the P+ doped region 105 forms a continuous current path through the N-type epitaxial layer 102, the P-type body region 103 at the edge of the cell region, and the N+ doped region within the protection unit region. Thus, multiple interconnected PN junctions are formed between the P+ doped region 105, the N-type epitaxial layer 102, the P-type body region 103, and the N+ doped region. When the potential difference between the source metal layer 108 and the N-type epitaxial layer 102 reaches a certain level, the multiple PN junctions within the protection unit region can conduct, establishing a low-resistance current channel between the source metal and the N-type epitaxial layer 102 to discharge current caused by overvoltage.

[0024] In the design of the terminal region, this invention arranges the terminal region and the protection unit region in a coordinated manner. Multiple P+ field-limiting rings are sequentially arranged along the periphery of the chip in the terminal region to adjust the electric field distribution in the terminal area. In a preferred embodiment, the innermost P+ field-limiting ring closest to the cell region is connected to the P+ doped region 105 in the protection unit region on a plane, forming a continuous P-type ring band. One side of this P-type ring band is adjacent to the cell region boundary, and the other side faces the remaining field-limiting rings in the terminal region. This interconnected arrangement facilitates the simultaneous formation of the P+ doped region 105 in the protection unit region and the innermost field-limiting ring in the terminal region during a one-step P-type ion implantation process, simplifying the process steps while ensuring the potential continuity between the two.

[0025] In one specific embodiment, the isolation structure is a dielectric isolation trench. This trench extends downwards through the gate dielectric and interlayer dielectric layer into the N-type epitaxial layer 102 to a certain depth, physically separating the cell region from the guard cell region. A field plate is disposed on the sidewalls and / or bottom of the dielectric isolation trench. The field plate is electrically connected to the gate electrode 106 via metal leads, extends along the boundary between the cell region and the guard cell region, and may partially extend above the terminal region. The field plate can regulate the surface electric field near the isolation trench, sharing some of the displacement current during high-voltage switching, thereby reducing the risk of the guard cell being falsely triggered during normal operation.

[0026] Regarding metal interconnects, to reduce the series resistance of the guard cell region and improve the uniformity of current distribution, this invention employs a strip-shaped arrangement of contact openings in the guard cell region. The contact openings extend in a plane parallel to the source metal strip, exhibiting a narrow and elongated shape, and simultaneously spanning both the P+ doped region 105 and the N+ doped region within the guard cell region. A single metallization process enables both doped regions to make 108-ohm contact with the same source metal layer. Preferably, the length of the contact openings along the chip periphery is greater than or equal to one cell pitch, thereby forming a continuous carrier extraction path within a certain range, which is beneficial for managing the carrier distribution within the guard cell region after surge subsidence.

[0027] Within the termination region, a polysilicon field plate or a metal field plate electrically connected to the gate 106 electrode can be disposed. This field plate is located outside the protection unit region, extending laterally above the termination region, and cooperates with the P+ field limiting ring or other termination doped regions within the termination region to improve the electric field distribution in the termination region, reduce local electric field peaks, and increase the chip's voltage withstand margin.

[0028] On the back side of the chip, a drain metal layer 109 for external electrical connection is formed after thinning the back side of the N-type silicon carbide substrate 101. The drain metal layer 109 can be deposited by evaporation or sputtering and then processed by laser annealing to form a stable ohmic contact between the metal layer and the substrate, thereby obtaining low contact resistance and good long-term operating stability.

[0029] The following example uses an N-type SiC MOSFET suitable for a voltage rating of approximately 1200V to illustrate the manufacturing process for implementing the aforementioned chip. Those skilled in the art can adjust the specific process parameters according to their actual design.

[0030] First, an N-type 4H-SiC epitaxial wafer with a predetermined resistivity and thickness is prepared. A polysilicon hard mask is formed through thermal oxidation and chemical vapor deposition, and an opening is formed in a predetermined area using a Pwell photolithography and etching process. Within the exposed area, silicon dioxide is deposited as an implantation masking layer, and aluminum is introduced for multi-energy, multi-dose ion implantation to obtain the desired doping profile, forming a P-type body region 103. After implantation, the masking layer is removed.

[0031] Subsequently, the gate stack and N+ source region 104 are fabricated. After removing the hard mask, a layer of N-type polysilicon with a thickness of, for example, 0.5 μm is deposited by chemical vapor deposition. The gate 106 pattern is formed by photolithography and etching. Then, polysilicon sidewalls are formed on the sidewalls of the gate 106 using anisotropic etching. Using the sidewalls as a self-aligned mask, nitrogen ion implantation is performed on one side of the gate region to form a heavily doped N+ source region 104. After completion, the implantation masking layer is removed.

[0032] Next, through photolithography and ion implantation, a P+ field-limiting ring in the terminal region and a P+ doped region 105 in the protective unit region are simultaneously formed. Aluminum can be used as the implanting element, and multiple implantations are performed to achieve the predetermined doping depth and concentration distribution. This step integrates the terminal field-limiting ring and the protective unit P+ doped region 105. Afterwards, high-temperature activation annealing is performed, for example using a carbon film protection process, under an argon atmosphere to activate the aforementioned P-type body region 103, N+ source region 104, and P+ doped region 105, while simultaneously repairing lattice damage. The surface carbon film is then removed after annealing.

[0033] After doping activation, a thin oxide layer is formed on the SiC surface using a sacrificial oxidation process and then removed to eliminate surface damage. A gate dielectric layer 107 of the target thickness is then grown in a humid oxygen environment, followed by interface passivation treatment in a nitrogen-containing atmosphere to improve the gate-oxide interface characteristics. Subsequently, an interlayer dielectric layer is deposited, for example, using a low-temperature oxide combined with borosilicate glass to form a multilayer dielectric, and planarization is performed.

[0034] Source contact holes are formed in the cell region and guard cell region using ohmic contact photolithography and etching processes. Within the guard cell region, the contact holes are designed as elongated strips, simultaneously exposing the P+ doped region 105 and the N+ doped region along their length. Simultaneously, gate 106 lead holes and metal contact areas for the terminal region or isolation trench inner field plate are etched. After contact hole etching, metal stacks such as titanium / nickel / silver are sequentially deposited using sputtering processes. Source electrodes, gate 106 electrodes, and related interconnect metals are formed through photolithography and etching, connecting the P+ doped region 105 and the N+ doped region within the guard cell region via the same source metal strip.

[0035] The back side of the substrate is then thinned to achieve the desired chip thickness. A back metal layer, such as nickel or silver, is deposited on the back side, and an ohmic contact with the N-type substrate is formed by laser annealing, thus obtaining the back drain metal electrode.

[0036] Through the above embodiments, a silicon carbide MOSFET chip can be obtained, in which a protective cell region is set between the cell region and the terminal region, and the P+ doped region 105 and the N+ doped region are connected through the same contact opening within the protective cell region. This chip features a coordinated design in terms of the layout relationship, isolation method, and contact geometry between the cell region, the terminal region, and the protective cell region. While maintaining the existing silicon carbide MOSFET process flow essentially unchanged, it provides an internal integrated path for discharging gate-source overvoltage, making it suitable for power electronics applications requiring high reliability.

[0037] The above embodiments are used to illustrate the chip structure and implementation of this utility model. Those skilled in the art can substitute and adjust the specific layout size, doping parameters, terminal form, or metal material without departing from the core concept of this utility model; all such equivalent modifications should be included within the protection scope of this utility model.

Claims

1. A silicon carbide MOSFET chip with a built-in protection unit, characterized in that, include: An N-type silicon carbide substrate and an N-type epitaxial layer formed on the substrate; A cell region is disposed within the active region of the epitaxial layer, wherein a plurality of parallel MOSFET cells are formed in the cell region; And a terminal region arranged outside the cell region, the terminal region being used to withstand the electric field at the edge of the chip; A protection unit region for gate-source protection is provided between the cell region and the terminal region, and the protection unit region is electrically isolated from the cell region by an isolation structure. Within the protection unit region, a P+ doped region that cooperates with the N-type epitaxial layer and an N+ doped region adjacent to the P+ doped region are formed. The P+ doped region and the N+ doped region are in ohmic contact with the source metal layer covering the cell region and the protection unit region through the same contact opening. The source metal layer extends continuously above the protection unit region and is electrically connected to the N+ source region within the cell region.

2. The silicon carbide MOSFET chip with built-in protection unit according to claim 1, characterized in that: The protective unit area is arranged in a strip-like continuous or intermittent segment along the outer edge of the cell area on the plane, forming a closed or nearly closed protective band around the cell area.

3. The silicon carbide MOSFET chip with built-in protection unit according to claim 2, characterized in that: The P+ doped region in the protection unit region, the N-type epitaxial layer, the P-type body region located at the edge of the cell region, and the N+ doped region are stacked sequentially in the vertical direction to form multiple alternating PN junctions, thereby forming a multi-junction conduction path between the source metal layer and the N-type epitaxial layer.

4. The silicon carbide MOSFET chip with built-in protection unit according to claim 3, characterized in that: Multiple P+ field limiting rings are arranged along the periphery of the chip in the terminal area. The innermost P+ field limiting ring is connected to the P+ doped region in the protection unit area on the plane to form an integrated P-type ring band. One side of the P-type ring band is adjacent to the cell region, and the other side is adjacent to the terminal area where the remaining field limiting rings are located.

5. The silicon carbide MOSFET chip with built-in protection unit according to claim 4, characterized in that: The isolation structure is a dielectric isolation trench that penetrates the dielectric layer above the gate dielectric and extends into the N-type epitaxial layer. The sidewalls and / or bottom of the dielectric isolation trench are provided with field plates electrically connected to the gate electrode. The field plates extend between the cell region and the protection cell region and partially cover one side of the terminal region.

6. The silicon carbide MOSFET chip with built-in protection unit according to claim 5, characterized in that: The contact opening is formed in a narrow strip shape on a plane along a direction parallel to the source metal layer strip. The contact opening spans both the P+ doped region and the N+ doped region in the protection unit region in the length direction, and extends at least one cell pitch along the periphery of the chip.

7. The silicon carbide MOSFET chip with built-in protection unit according to claim 1, characterized in that: The terminal area is provided with a polysilicon field plate or a metal field plate that is electrically connected to the gate electrode, and the field plate extends laterally above the terminal area outside the protection unit area.

8. The silicon carbide MOSFET chip with built-in protection unit according to claim 1, characterized in that: A drain metal layer is formed on the back side of the N-type silicon carbide substrate, and the drain metal layer is connected to the substrate through an ohmic contact formed by laser annealing.

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