Semiconductor device

Abstract

A semiconductor device includes a first fin and a second fin on a semiconductor substrate, wherein a first width of the first fin is different from a second width of the second fin; a plurality of first nanostructures on the first fin; a plurality of second nanostructures on the second fin; a first gate structure on the first fin, wherein the first gate structure separates individual adjacent first nanostructures; and a second gate structure on the second fin, wherein the second gate structure separates individual adjacent second nanostructures; and an isolation structure extending from the first fin to the second fin, wherein the isolation structure protrudes into the semiconductor substrate.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to fins segmented from a continuous fin structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum structural dimensions to improve the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, or the like, allowing more components to be integrated into a given area. However, as the minimum structural dimensions shrink, additional problems arise that need to be addressed. Utility Model Content

[0004] In one embodiment, the semiconductor device includes a first fin and a second fin located on a semiconductor substrate, wherein a first width of the first fin is different from a second width of the second fin; a plurality of first nanostructures located on the first fin; a plurality of second nanostructures located on the second fin; a first gate structure located on the first fin, wherein the first gate structure separates individual adjacent first nanostructures; and a second gate structure located on the second fin, wherein the second gate structure separates individual adjacent second nanostructures; and an isolation structure extending from the first fin to the second fin, wherein the isolation structure protrudes into the semiconductor substrate.

[0005] In some embodiments, the distance between the first fin and the second fin is 20 nm to 80 nm.

[0006] In some embodiments, the semiconductor device further includes a shallow trench isolation region surrounding the first fin, wherein the isolation structure extends between the first fin and the shallow trench isolation region.

[0007] In some embodiments, the difference between the first width and the second width is 5 nm to 115 nm.

[0008] In some embodiments, the semiconductor device further includes a third fin located on the semiconductor substrate, wherein the isolation structure extends from the first fin to the third fin.

[0009] In some embodiments, the semiconductor device further includes a plurality of third nanostructures located on the third fin, and a third gate structure located on the third fin, wherein the third gate structure separates individual adjacent third nanostructures.

[0010] In some embodiments, a third width of the third fin is different from the first width.

[0011] In some embodiments, a third width of the third fin is equal to the second width.

[0012] In some embodiments, the isolation structure completely covers the sidewall of the first fin.

[0013] In some embodiments, the isolation structure completely covers the sidewall of the second fin. Attached Figure Description

[0014] Figure 1 These are three-dimensional diagrams of nanostructured field-effect transistors in some embodiments.

[0015] Figure 2 , 3A ,3B,4,5A,5B,6A,6B,7A,7B,8A,8B,8C,8D,9A,9B,10A,10B,11A,11B,11C,12A,12B,12C,13A,13B, 14A, 14B, 14C, 14D, 14E, 15A, 15B, 15C, 15D, 16A, 16B, 16C, 16D, 17A, 17B, 17C, 17D, 18A, 18B, 18C, 18D 19A, 19B, 19C, 19D, 20, 21A, 21B, 22A, 22B, 22C, 22D, 23A, 23B, 23C, 23D, 24A, 24B, 24C, 24D, 25A, 25B, 25C, 25D, 26A, 26B, 26C, 26D, 27A, 27B, 27C, 27D, 28A, 28B, and 28C are various patterns of intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments.

[0016] Figure 29A , 29B Figures 29C and 29C are plan views of the continuous fin structure in some embodiments.

[0017] Figure 30A , 30B 30C and 30D are plan views of the isolation zone between fins in some embodiments.

[0018] Figure 31A , 31B 31C, 31D, 31E, 31F, and 31G are plan views of the continuous fin structure in some embodiments.

[0019] Figure 32A , 32B33A, 33B, 33C, 33D, 34A, 34B, 34C, 34D, 35A, 35B, 35C, 35D, 36A, 36B, 36C, 36D, 37A, 37B, 37C, 37D, 38, and 39 are various diagrams of intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments.

[0020] The reference numerals in the attached figures are explained as follows:

[0021] A-A', A1-A1', A2-A2', A3-A3', B-B', B1-B1', B2-B2', C-C': Section

[0022] D1, D2, D3: Deviation

[0023] S1: Separation distance

[0024] WA, WB, WC: Width

[0025] 50: Substrate

[0026] 50N: n-type region

[0027] 50P: p-type area

[0028] 51: Fin terminal area

[0029] 51': Off-end region

[0030] 52: Multi-layer stacking

[0031] 54: First semiconductor layer

[0032] 56: Second semiconductor layer

[0033] 61: Continuous fin structure

[0034] 62, 62A, 62B, 62C, 62D, 62E: Fins

[0035] 62', 62A', 62B', 62C', 62D', 62E': Fin-like portions

[0036] 64: First Nanostructure

[0037] 64 / 66: Nanostructures

[0038] 65, 123: Opening

[0039] 66: Second Nanostructure

[0040] 68: Insulation materials

[0041] 70, 125: Quarantine Zone

[0042] 71: Dummy Materials

[0043] 72: Virtual Area

[0044] 82: Virtual Dielectric Layer

[0045] 84: Dummy Gate

[0046] 86: Mask

[0047] 90: Spacer layer

[0048] 92: Gate spacer

[0049] 94: Fin-shaped spacers

[0050] 96: Source / Drain dip

[0051] 96', 108: Depression

[0052] 97: Side wall depression

[0053] 98: Inner spacer

[0054] 100: Source / Drain Region

[0055] 100': Semiconductor layer

[0056] 102: Contact Etching Stop Layer

[0057] 104: First interlayer dielectric layer

[0058] 110: Gate dielectric layer

[0059] 112: Gate

[0060] 120: Gate isolation region

[0061] 122: Hard mask layer

[0062] 124: Padding layer

[0063] 126: Filler material

[0064] 128: Etching Stop Layer

[0065] 130: Second interlayer dielectric layer

[0066] 132: Gate contact

[0067] 133: Metal-Semiconductor Alloy Region

[0068] 134: Source / Drain Contact Detailed Implementation

[0069] The following detailed description, accompanied by accompanying drawings, will aid in understanding all aspects of this utility model. It is worth noting that the various structures are for illustrative purposes only and are not drawn to scale, as is customary in the art. In practice, the dimensions of various structures may be increased or decreased arbitrarily for clarity.

[0070] It is understood that the different embodiments or examples provided below may implement different structures of the present invention. The specific components and arrangements described are intended to simplify this disclosure and not to limit the present invention. For example, a description of a first component being formed on a second component includes direct contact between the two, or a separation between the two by other additional components rather than direct contact. Furthermore, the same reference numerals may be repeated in various embodiments of the present invention for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same correspondence.

[0071] In addition, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90 degrees or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0072] The following embodiments are specifically illustrated using a die containing a nanostructured field-effect transistor. However, various embodiments can be used in dies containing other types of transistors (such as fin field-effect transistors, planar transistors, stacked transistors, or the like) to replace or combine with nanostructured field-effect transistors.

[0073] In various embodiments, oxide dummy regions are used to fill the areas between the channel regions of the nanostructured field-effect transistor, i.e., after the gate structure is formed. Using oxide dummy regions allows for more selective etching during their removal, reducing the risk of etch damage to the channel regions or source / drain regions. This reduced risk of etch damage allows for safer formation of isolation regions after the gate structure is formed, improving device density and yield.

[0074] Figure 1 These are three-dimensional images of nanostructured field-effect transistors (such as nanowire field-effect transistors, nanosheet field-effect transistors, nanostructured field-effect transistors, fully wound gate field-effect transistors, or the like) in some embodiments. Figure 1Some structures of the nanostructured field-effect transistor are simplified and / or omitted for clarity of illustration. The nanostructured field-effect transistor includes a second nanostructure 66 (such as a nanosheet, nanowire, or the like) situated on a fin 62 on a substrate 50 (such as a semiconductor substrate), and the second nanostructure 66, such as a semiconductor structure, may serve as the channel region used by the nanostructured field-effect transistor. The second nanostructure 66 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. Isolation regions 70, such as shallow trench isolation regions, are situated between adjacent fins 62, and the fins 62 may protrude above the adjacent isolation regions 70. The second nanostructure 66 is situated between and above adjacent isolation regions 70. A protective layer or hard masking layer (not shown) Figure 1 The fin 62 may cover a portion of the isolation region 70. Although the isolation region 70 is separated from the substrate 50 in the illustration and figures, the term "substrate" as used herein may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fin 62 in the figures is a single continuous material with the substrate 50, the bottom of the fin 62 and / or the substrate 50 may comprise a single material or multiple materials. In this description, fin 62 refers to the portion extending between adjacent isolation regions 70.

[0075] Gate dielectric layer 110 is located on the upper surface of fin 62 and extends along the upper surface, sidewalls, and lower surface of the second nanostructure 66. Gate 112 is located on gate dielectric layer 110. Gate dielectric layer 110 and gate 112 can be considered together as a "gate structure" or "gate stack". Isolation region (not shown) Figure 1 (As detailed below) Source / drain regions 100 may be formed between fins 62 or at the ends of some fins 62. Source / drain regions 100 (such as epitaxial source / drain regions) are located on the fins 62 on both sides of the gate dielectric layer 110 and the gate 112. Source / drain regions 100 may be considered as sources or drains individually or together, depending on the content. A first interlayer dielectric layer 104 is formed on the source / drain regions 100. Contacts connected to the source / drain regions 100 (as described later) pass through the first interlayer dielectric layer 104. Source / drain regions 100 may be shared among various second nanostructures 66. For example, adjacent source / drain regions 100 may be electrically connected by merging epitaxially grown source / drain regions 100, or by being coupled to source / drain regions 100 by the same contact.

[0076] Figure 1The reference cross-sections used in subsequent illustrations are also shown. Cross-section A-A' runs along the longitudinal axis of the fin 62 of the nanostructured field-effect transistor and in the current direction between the source / drain regions 100 of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and extends along the longitudinal axis of the gate 112. Cross-section C-C' is parallel to cross-section B-B' (i.e., perpendicular to cross-section A-A') and extends through the source / drain regions 100 of the nanostructured field-effect transistor. Subsequent illustrations are based on these reference cross-sections for clarity.

[0077] Some embodiments described herein are illustrated using nanostructured field-effect transistors (FETs) formed using a post-gate fabrication process. In other embodiments, a gate-first fabrication process may be used. Furthermore, some embodiments may be used in planar devices (such as planar FETs) or fin FETs to replace or complement nanostructured FETs. For example, a fin FET may include semiconductor fins located on a substrate, and the semiconductor fins, such as semiconductor structures, may serve as channel regions for the fin FET. Similarly, a planar FET includes a substrate, and the flat portion of the substrate, such as a semiconductor structure, may serve as a channel region for the planar FET. Other FETs or FET configurations are also possible.

[0078] Figures 2 to 28C These are diagrams illustrating intermediate stages in the fabrication of nanostructured field-effect transistors in some embodiments. Figure 2 , 3B 5B, 6A, 7A, 8A, 8D, 9A, 10A, 11A, 11C, 12A, 12C, 13A, 13B, 14A, 14E, 15A, 15D, 16A, 16D, 17A, 17D, 18A, 18D, 19A, 19D, 20, 21A, 22A, 22D, 23A, 23D, 24A, 24D, 25A, 25D, 26A, 26D, 27A, 27D, and 28A are along a similar path. Figure 1 A sectional view of section A-A' in the diagram. Figure 3A , 4 Numbers 5A, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 14B, 15B, 16B, 17B, 18B, 19B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, and 28B are along a path similar to... Figure 1 A sectional view of section B-B' in the diagram. Figure 8C , 14C 14C, 15C, 16C, 17C, 18C, 19C, 22C, 23C, 24C, 25C, 26C, 27C, and 28C are along a path similar to Figure 1 A sectional view of section C-C' in the diagram.

[0079] exist Figure 2 In some embodiments, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a substrate semiconductor, a semiconductor-on-insulator (SIA) substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate may be a wafer such as a silicon wafer. Generally, a SIA substrate has a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. An insulating layer is provided on the substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, semiconductor compounds (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium arsenide phosphide indium), or combinations thereof.

[0080] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as n-type metal-oxide-semiconductor transistors (e.g., n-type nanostructure field-effect transistors), while the p-type region 50P can be used to form p-type devices such as p-type metal-oxide-semiconductor transistors (e.g., p-type nanostructure field-effect transistors). The n-type region 50N and the p-type region 50P may be physically separated (not shown), and any number of device structures (e.g., other active regions, doped regions, isolation structures, or the like) may be located between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P may be provided. The subsequent process steps shown in the diagram may be performed in either the n-type region 50N or the p-type region 50P, unless otherwise stated.

[0081] exist Figure 2 In some embodiments, a multilayer stack 52 is formed on a substrate 50. The multilayer stack 52 includes an interleaved first semiconductor layer 54 and a second semiconductor layer 56. The first semiconductor layer 54 is composed of a first semiconductor material, and the second semiconductor layer 56 is composed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50. In the embodiments described, the first semiconductor layer 54 is removed and the second semiconductor layer 56 is patterned to form channel regions used by nanostructured field-effect transistors in the n-type region 50N and the p-type region 50P, as detailed below. In these embodiments, the channel regions in the n-type region 50N and the p-type region 50P may have the same material composition (such as silicon or another semiconductor material) and may be formed simultaneously. The first semiconductor layer 54 is a dummy layer that will be removed in a subsequent process to expose the upper and lower surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54, such as silicon-germanium, has high etch selectivity relative to the second semiconductor layer 56. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0082] In another embodiment (not shown), a first semiconductor layer 54 is patterned to form a channel region for a nanostructured field-effect transistor in one region (e.g., p-type region 50P), and a second semiconductor layer 56 is patterned to form a channel region for a nanostructured field-effect transistor in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon-germanium, pure germanium, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like. The second semiconductor material of the second semiconductor layer 56 may be a material suitable for n-type devices, such as silicon, silicon carbide, group III-V semiconductor compounds, group II-VI semiconductor compounds, or the like. The first and second semiconductor materials may have high etch selectivity relative to each other, so that the first semiconductor layer 54 can be removed in the n-type region 50N without significantly removing the second semiconductor layer 56, and the second semiconductor layer 56 can be removed in the p-type region 50P without significantly removing the first semiconductor layer 54.

[0083] The multilayer stack 52 in the diagram includes four first semiconductor layers 54 and four second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56. Each layer of the multilayer stack 52 may be formed using growth processes such as vapor phase epitaxy or molecular beam epitaxy, deposition processes such as chemical vapor deposition or atomic layer deposition, or similar processes. In some embodiments, the thickness of some layers of the multilayer stack 52 is less than the thickness of other layers of the multilayer stack 52. For example, the bottommost second semiconductor layer 56 (such as the second semiconductor layer 56 closest to the substrate 50) may be thinner than the upper second semiconductor layers 56 to improve short-channel control of the final nanostructure field-effect transistor. Other combinations or variations in layer thickness are also possible.

[0084] exist Figure 3A and Figure 3B In some embodiments, the fin 62 is formed in the substrate 50, while the first nanostructure 64 and the second nanostructure 66 are formed in the multilayer stack 52. The first nanostructure 64 and the second nanostructure 66 can be considered together here as nanostructures 64 / 66. Figure 3A It is along a path similar to Figure 1 A sectional view of section B-B' in the diagram, and Figure 3B It is along a path similar to Figure 1 A sectional view of section A-A' in the diagram. Figure 3B The distal portion of fin 62 and the above nanostructures 64 / 66 are shown, wherein the nanostructures 64 / 66 and fin 62 are removed to longitudinally terminate the fin 62 and nanostructures 64 / 66. The area located in or near the fin 62 and nanostructures 64 / 66 is marked as... Figure 3BThe fin-like terminal region 51. Figure 3A and Figure 3B It can be an n-type region 50N or a p-type region 50P of the substrate 50, unless otherwise specified.

[0085] In some embodiments, nanostructures 64 / 66 and fins 62 may be formed in the multilayer stack 52 and the substrate 50, respectively, by etching trenches in the multilayer stack 52 and the substrate 50. The etching may be any acceptable etching process such as reactive ion etching, neutral beam etching, similar processes, or combinations thereof. The etching may be anisotropic. Etching the multilayer stack 52 to form nanostructures 64 / 66 may further define a first nanostructure 64 from the first semiconductor layer 54 and a second nanostructure 66 from the second semiconductor layer 56.

[0086] The fins 62 and nanostructures 64 / 66 can be patterned by any suitable method. For example, the fins 62 and nanostructures 64 / 66 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, resulting in a pattern pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate, and the sacrificial layer is patterned using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers are subsequently used to pattern the fins 62 and nanostructures 64 / 66. Other patterning techniques are also possible. In some examples, the fins 62 can be patterned into a continuous fin structure 61, which is then separated into separate fins 62 by an isolation region 125, such as in combination with Figures 29A to 31G The details are as follows.

[0087] The illustrated fin 62 may have substantially the same width in both the n-type region 50N and the p-type region 50P. In some embodiments, the width of the fin 62 in the n-type region 50N may be greater than the width of the fin 62 in the p-type region 50P. Furthermore, while the fin 62 and nanostructures 64 / 66 in the illustration have fixed widths, in other embodiments the fin 62 and nanostructures 64 / 66 may have trapezoidal sidewalls, meaning that the width of each of the fin 62 and / or nanostructures 64 / 66 continuously increases in the direction toward the substrate 50. In these embodiments, the widths of the nanostructures 64 / 66 may be different and may be trapezoidal.

[0088] exist Figure 4In this embodiment, an insulating material 68 is formed on the substrate 50 and between adjacent fins 62 and adjacent nanostructures 64 / 66. The insulating material 68 may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and its formation method may be high-density plasma chemical vapor deposition, flowable chemical vapor deposition, similar methods, or a combination thereof. Other insulating materials formed by any acceptable process may also be used. In some embodiments, the insulating material 68 comprises silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material 68 is formed, an annealing process can be performed. Although the insulating material 68 in the figures is a single layer, in some embodiments the insulating material 68 may be multilayered. For example, in some embodiments, a pad (not shown) may first be formed along the surfaces of the substrate 50, fins 62, and nanostructures 64 / 66. A filler material (such as the aforementioned insulating material) may then be formed on the pad.

[0089] Insulating material 68 may be deposited on the fins 62 and the nanostructures 64 / 66, such that excess insulating material 68 covers the nanostructures 64 / 66. A removal process is then performed on the insulating material 68 to remove the excess insulating material 68 from the nanostructures 64 / 66. In some embodiments, a planarization process such as chemical mechanical polishing, etch-back, a combination thereof, or a similar process may be used. The planarization process exposes the nanostructures 64 / 66, so that the nanostructures 64 / 66 are flush with the upper surface of the insulating material 68 after the planarization process.

[0090] exist Figure 5A and Figure 5B In some embodiments, the insulating material 68 is recessed to form a shallow trench isolation region 70. The shallow trench isolation region 70 is adjacent to the fin 62 and may be adjacent to the end portion of the fin 62 (e.g., fin end region 51). The insulating material 68 is recessed such that the upper portion of the fin 62 and / or the nanostructures 64 / 66 protrude from between adjacent shallow trench isolation regions 70. The upper portion of the fin 62 and / or the nanostructures 64 / 66 is higher than the shallow trench isolation region 70. In some examples, portions of the fin 62 and / or the nanostructures 64 / 66 may be lower than the upper surface of the shallow trench isolation region 70. Furthermore, the upper surface of the shallow trench isolation region 70 may be a flat surface, a convex surface, a recessed surface (e.g., dished), or a combination thereof, as illustrated. The upper surface of the shallow trench isolation region 70 may be flat, convex, and / or recessed by suitable etching. The shallow trench isolation region 70 can be recessed using an acceptable etching process, such as an etching process selectively etching the insulating material 68 (where the etching rate of the insulating material 68 is greater than the etching rate of the fins 62 and the nanostructures 64 / 66). For example, an oxide removal method using diluted hydrofluoric acid can be used.

[0091] The above-described process is merely one example of how the fins 62 and nanostructures 64 / 66 can be formed. In some embodiments, a masking and epitaxial growth process can be used to form the fins 62 and / or nanostructures 64 / 66. For example, a dielectric layer can be formed on the upper surface of the substrate 50, and trenches can be etched to penetrate the dielectric layer and expose the underlying substrate 50. An epitaxial structure can be epitaxially grown in the trenches, causing the dielectric layer to be recessed, thus the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64 / 66. The epitaxial structure may include the aforementioned interleaved semiconductor materials, such as a first semiconductor material and a second semiconductor material. In some embodiments, the epitaxial structure is formed by epitaxial growth, in which case the epitaxial growth material can be in-situ doped during growth to omit the preceding and / or subsequent implantation, but in-situ doping and implantation doping can be used in combination.

[0092] exist Figure 5A and Figure 5B Suitable wells (not shown) can be formed in the fins 62, nanostructures 64 / 66, and / or shallow trench isolation regions 70. In embodiments with different well morphologies, photoresist or other masks (not shown) can be used to achieve different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed on the fins 62, nanostructures 64 / 66, and shallow trench isolation regions 70 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating technology and patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurities can be implanted in the p-type region 50P, while the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, and the concentration in the implanted region can be about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 The photoresist can be removed after application, and the removal method can be an acceptable ashing process.

[0093] Before or after implanting the p-type region 50P, photoresist or other masks (not shown) can be formed on the fins 62, nanostructures 64 / 66, and shallow trench isolation regions 70 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating technology and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurities can be implanted in the n-type region 50N, while the photoresist acts as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or the like, and the concentration implanted in the region can be about 10. 13 atoms / cm 3 To about 10 14 atoms / cm3 The photoresist can be removed after application, and the removal method can be an acceptable ashing process.

[0094] After implanting the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped to omit implantation, but in-situ doping and implantation doping can be used in combination.

[0095] In other embodiments, a hard mask (not shown) may be formed on the upper surface of the shallow trench isolation region 70 to protect the shallow trench isolation region 70 in subsequent process steps. For example, the hard mask may be formed by first depositing a hard mask material on the nanostructures 64 / 66, the fins 62, and the shallow trench isolation region 70. In some examples, the hard mask material is compliantly deposited to form a continuous layer. The hard mask material is then removed from the upper surface and sidewalls of the nanostructures 64 / 66 and the fins 62 using an etching process, and the remaining portion of the hard mask material on the shallow trench isolation region 70 forms the hard mask. The method for removing the upper portion of the hard mask material may employ an acceptable etching process, such as dry etching, wet etching, or a combination thereof. The hard mask material may include one or more materials that have high etch selectivity relative to the material of the shallow trench isolation region 70 and / or the nanostructures 64 / 66. For example, hard masking materials may include nitrides such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, combinations thereof, or the like. In some examples, hard masking materials include oxides such as hafnium oxide, zirconium oxide, or the like. In some examples, other materials are also possible, and hard masking materials may include multiple layers of different materials. The deposition method for hard masking materials may employ suitable processes, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar methods.

[0096] exist Figure 6A and Figure 6BIn some embodiments, a dummy dielectric layer 82, a dummy gate 84, and a mask 86 are formed along the sidewalls and top surface of the fins 62 and / or nanostructures 64 / 66. In some embodiments, the dummy dielectric layer is formed on the fins 62 and / or nanostructures 64 / 66. The dummy dielectric layer may be composed of silicon oxide, silicon nitride, a combination thereof, or the like, and may be formed by deposition or thermal growth according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a mask is formed on the dummy gate layer. The dummy gate layer may be deposited on the dummy dielectric layer, and then planarized by a chemical mechanical polishing process or a similar method. The dummy gate layer may be composed of a conductive or non-conductive material, selected from amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide, or metal. The deposition method for the material of the dummy gate layer may be chemical vapor deposition, physical vapor deposition, sputtering deposition, or another suitable technique. The dummy gate layer can be composed of other materials, as long as it has high etch selectivity relative to insulating materials such as shallow trench isolation region 70 and / or dummy dielectric layer. A masking layer can be deposited on the dummy gate layer. The masking layer can be composed of dielectric materials such as silicon nitride, silicon oxynitride, or the like.

[0097] The mask layer is then patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 can then be transferred to a dummy gate layer and a dummy dielectric layer to form dummy gate 84 and dummy dielectric layer 82, respectively. The dummy gate 84 covers individual channel regions of nanostructures 64 / 66. The pattern of mask 86 can be used to physically separate each adjacent dummy gate 84. The length direction of the dummy gate 84 can also be substantially perpendicular to the length direction of the individual fins 62 (e.g., longitudinal). Mask 86 can be removed after patterning, and the removal method can be any acceptable etching technique. In this example, a single dummy gate layer and a single mask layer are formed to cross the n-type region 50N and the p-type region 50P. In an exemplary embodiment, the dummy dielectric layer covers the shallow trench isolation region 70, such that the dummy dielectric layer 82 extends between the dummy gate 84 and the shallow trench isolation region 70. In another embodiment, the dummy dielectric layer 82 covers only the fins 62 and / or nanostructures 64 / 66.

[0098] exist Figure 7A and Figure 7B In some embodiments, a spacer layer 90 is compliantly formed on the structure. The spacer layer 90 is formed on the nanostructures 64 / 66 and the shallow trench isolation region 70. The spacer layer 90 is also formed on the exposed sidewalls of the mask 86 (if present), the dummy gate 84, the dummy dielectric layer 82, the nanostructures 64 / 66, and / or the fins 62. The spacer layer 90 may be composed of one or more dielectric materials. Figure 7A and 7BThe spacer layer 90 shown is a single layer of dielectric material, but in other embodiments, the spacer layer 90 may be two or more layers of dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, and may be formed by deposition processes such as chemical vapor deposition, atomic layer deposition, or similar methods. Other dielectric materials formed using any acceptable process may also be used. The spacer layer 90 may then be etched to form the spacers.

[0099] exist Figures 8A to 8D In the middle, a patterned spacer layer 90 is used to form a gate spacer 92 and a fin spacer 94. Figure 8D The distal portion of the fin 62, which contains a fin-like distal region, shown is similar to... Figure 3B Similar to the illustration. Any acceptable etching process, such as dry etching, wet etching, similar processes, or combinations thereof, can be performed to pattern the spacer layer 90. The etching can be anisotropic. The etched spacer layer 90 has portions retained on the sidewalls of the dummy gate 84 (thus forming gate spacers 92) and portions retained on the sidewalls of the fins 62 and / or nanostructures 64 / 66 (thus forming fin spacers 94). The etched fin spacers 94 and / or gate spacers 92 can have flat or curved sidewalls. In some embodiments, shallow trench isolation regions 70 can also be etched when patterning the spacer layer 90. For example, etching can cause a partial recess in the shallow trench isolation regions 70 between the fins 62 and / or between the gate spacers 92. The gate spacers 92 and / or fin spacers 94 can have flat sidewalls (as illustrated) or curved sidewalls (not illustrated).

[0100] Furthermore, the implantation used for lightly doped source / drain regions (not shown) can be performed. In embodiments of different device types, similar to the implantation used for the aforementioned well, a mask, such as photoresist, can be formed on the n-type region 50N, exposing the p-type region 50P, and a suitable type (such as p-type) of impurity can be implanted into the exposed fins 62 and nanostructures 64 / 66 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain regions can be approximately 10. 15 atoms / cm 3 To about 10 19 atoms / cm 3 Annealing can be used to repair damage and revitalize implanted impurities.

[0101] It is worth noting that the above describes a general process for forming spacers and lightly doped source / drain regions. Other processes and sequences can also be used. For example, fewer or additional steps can be used, different step sequences can be used, additional spacers can be formed and removed, and / or similar adjustments can be made. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0102] like Figures 8A to 8D In some embodiments shown, source / drain recesses 96 are patterned in the fins 62, nanostructures 64 / 66, and substrate 50. Epitaxial source / drain regions are then formed in the source / drain recesses 96. The source / drain recesses 96 may extend through the nanostructures 64 / 66 into the substrate 50. Figure 8C In some embodiments shown, the fins 62 may be etched such that the lower surface of the source / drain recess 96 is lower than the upper surface of the shallow trench isolation region 70. In other embodiments, the lower surface of the source / drain recess 96 is generally flush with or higher than the upper surface of the shallow trench isolation region 70. The source / drain recess 96 may be formed by using anisotropic etching processes such as reactive ion etching, neutral beam etching, or similar processes to etch the fins 62, nanostructures 64 / 66, and substrate 50. In some embodiments, in the etching process used to form the source / drain recess 96, the gate spacer 92 and the dummy gate 84 mask portions of the fins 62, nanostructures 64 / 66, shallow trench isolation region 70, and / or substrate 50. A single etching process or multiple etching processes may be used to etch each layer of the nanostructures 64 / 66 and / or the fins 62. A time-controlled etching process can be used to stop etching the source / drain recess 96 after it has reached the desired depth. Etching may etch the shallow trench isolation region 70 to form the recess 96', which may extend into the shallow trench isolation region 70 between the gate spacers 92. In other embodiments, the shallow trench isolation region 70 is not etched. For embodiments in which a hard mask is formed on the shallow trench isolation region 70, etching may stop at the hard mask, thin the hard mask, or remove the hard mask, depending on the characteristics of the etching process.

[0103] exist Figure 9A and Figure 9BNext, the remainder of the first nanostructure 64 is removed to form an opening 65 in the region between the second nanostructures 66. The remainder of the first nanostructure 64 can be removed via an etching process through a source / drain recess 96. The etching process can include any acceptable etching process that selectively etches the material of the first nanostructure 64 at a rate greater than the rate at which it etches the material of the second nanostructure 66 and the fin 62. The etching process can include a wet etching process and / or a dry etching process, and the etching can be isotropic. For example, when the first nanostructure 64 is composed of silicon-germanium and the second nanostructure 66 is composed of silicon or silicon carbide, the etching process can be a wet etching using tetramethylammonium hydroxide, ammonium hydroxide, or the like. In other embodiments, the etching process can be a dry etching using fluorine gas, ammonia, hydrofluoric acid, chlorine trifluoride, xenon trifluoride, or the like. In some embodiments, a trimming process (not shown) is performed to reduce the thickness of the exposed portion of the second nanostructure 66 and enlarge the opening 65. The second nanostructure 66 can be considered as a nanostructure, and the vertically adjacent second nanostructures 66 on each fin 62 can be considered as a stack of second nanostructures 66.

[0104] exist Figures 10A to 11C In some embodiments, the first nanostructure 64 is replaced with a dummy material 71 to form a dummy region 72. In some examples, the dummy material 71 can be considered a sacrificial material or a sacrificial oxide. In some examples, the dummy region 72 can be considered a sacrificial region, a dielectric dummy region, a dummy nanostructure, a dummy gate region, or a one-time oxide interposer. Replacing the first nanostructure 64 with the dummy region 72 can provide advantages. For example, subsequent source / drain formation steps may involve one or more high-temperature processes to activate the dopants in the source / drain regions. When the first nanostructure 64 (such as silicon-germanium or the like) is exposed to high temperatures, germanium may mix with each other, and the interface roughness between the first nanostructure 64 and the second nanostructure 66 may increase. These manufacturing defects may degrade the performance of the final transistor device. For example, when germanium diffuses into the second nanostructure 66, germanium residue may remain in the channel region of the final transistor device, which may negatively affect the performance of the channel region. Furthermore, mixing with each other may cause a decrease in the etch selectivity of the first nanostructure 64 or the second nanostructure 66 and reduce the etch definition. For example, this could result in unwanted removal of portions of the second nanostructure 66, reducing yield and / or degrading performance. Replacing the first nanostructure 64 with an insulating material (such as a dummy material) prior to high-temperature processes (such as source / drain annealing) can reduce manufacturing defects and improve device performance (e.g., increase drive current, reduce capacitance, and improve short-channel effects). Furthermore, the dummy material 71 and the material of the second nanostructure 66 can have high etch selectivity to improve etch definition and reduce unwanted etching of the second nanostructure 66.

[0105] exist Figure 10A and Figure 10B In some embodiments, dummy material 71 is deposited in the source / drain recess 96 and the opening 65. The deposition method for the dummy material 71 may be a compliant deposition process such as chemical vapor deposition, atomic layer deposition, or a similar process. The dummy material 71 may include an insulating material such as silicon oxide or the like, which has etch selectivity relative to the second nanostructure 66 and the fin 62. Figure 10A and 10B As shown, the dummy material 71 can fill or overfill the opening 65 and can cover the sidewalls of the second nanostructure 66. The dummy material 71 can cover the upper surface of the fin 62. In some embodiments, the dummy material 71 does not completely fill the source / drain recess 96.

[0106] exist Figures 11A to 11C In some embodiments, dummy material 71 may be etched to form dummy region 72. Etching may be isotropic or anisotropic. For example, a wet etching process such as dilute hydrofluoric acid or the like may be used to etch the dummy material 71. In some embodiments, etching is performed until the sidewalls of the dummy material 71 are recessed beyond the sidewalls of the second nanostructure 66 to form sidewall recesses 97. In summary, the width of the dummy region 72 is smaller than the width of the second nanostructure 66. In some examples, the sidewall recess 97 may be considered as a portion of the source / drain recess 96. Although the sidewalls of the dummy region 72 in the illustrated sidewall recess 97 are flat, the sidewalls may be recessed or protruding. Figure 11C As shown, the dummy material 71 can be completely removed from the sidewall recess 97 in the fin end region 51 to expose the dummy gate 84 adjacent to the fin end region 51. In other embodiments, a portion of the etched dummy material 71 may remain in the sidewall recess 97 in the fin end region 51.

[0107] exist Figures 12A to 12C In some embodiments, an inner spacer 98 is formed in the sidewall recess 97. In other words, the inner spacer 98 is formed on the sidewall of the dummy region 72. As detailed below, source / drain regions are subsequently formed in the source / drain recess, and the dummy region 72 can then be replaced with the corresponding gate structure. The inner spacer 98 serves as an isolation structure between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the inner spacer 98 can be used to prevent subsequent etching processes from damaging the subsequently formed source / drain regions.

[0108] In some embodiments, the inner spacer 98 is formed by conformally depositing an insulating material in the source / drain recess 96 and the sidewall recess 97, followed by etching the insulating material. The insulating material may be silicon nitride, silicon oxynitride, or the like. However, any suitable material, such as a material with a low dielectric constant (less than about 3.5), may be used. The insulating material may be formed by a deposition process such as atomic layer deposition, chemical vapor deposition, or a similar process. The etching method for the insulating material may be anisotropic. For example, the etching process may be dry etching such as reactive ion etching, neutral beam etching, or a similar process. After etching the insulating material, the remaining portion of the insulating material in the sidewall recess 97 forms the inner spacer 98. The thickness of the inner spacer 98 may be less than, approximately equal to, or greater than the thickness of the adjacent dummy region 72.

[0109] Although the outer sidewall of the illustrated inner spacer 98 is flush with (approximately coplanar with) the sidewall of the second nanostructure 66, the outer sidewall of the inner spacer 98 may extend beyond or recess into the sidewall of the second nanostructure 66. In other words, the inner spacer 98 may partially fill, completely fill, or overfill the sidewall recess 97. Furthermore, although... Figures 12A to 12C The sidewalls of the inner spacer 98 are flat, and the sidewalls of the inner spacer 98 may be concave or convex. In one example, Figure 13A In the illustrated embodiment, the sidewall of the dummy region 72 is arc-shaped, the outer sidewall of the inner spacer 98 is recessed, and the inner spacer 98 is recessed from the sidewall of the second nanostructure 66. In another example, Figure 13B In the illustrated embodiment, the sidewalls of the dummy region 72 are arc-shaped, the outer sidewalls of the inner spacer 98 are flat, and the outer sidewalls of the inner spacer 98 are flush with the sidewalls of the second nanostructure 66. Other configurations of the sidewall contours are also possible.

[0110] exist Figures 14A to 14E In some embodiments, epitaxial source / drain regions 100 are formed within the source / drain recesses 96 of the n-type region 50N and the p-type region 50P. The epitaxial source / drain region 100 can also be considered a source / drain region. For example, the epitaxial source / drain region 100 in the n-type region 50N can be considered an n-type epitaxial source / drain region, while the epitaxial source / drain region 100 in the p-type region 50P can be considered a p-type epitaxial source / drain region. The n-type epitaxial source / drain region 100 can be formed before, after, or simultaneously with the formation of the p-type epitaxial source / drain region 100. The method for forming the epitaxial source / drain region 100 can be an epitaxial process such as vapor phase epitaxy, molecular beam epitaxy, or similar methods.

[0111] In some embodiments, a semiconductor layer 100' may be formed in the source / drain recess 96 before the epitaxial source / drain region 100 is formed in the source / drain recess 96. For example, the semiconductor layer 100' may comprise undoped silicon or the like. Although the upper surface of the illustrated semiconductor layer 100' is flat, the upper surface of the semiconductor layer 100' may be recessed or protruding. The upper surface of the semiconductor layer 100' may be higher than, nearly flush with, or lower than the upper surface of the fin 62. In some embodiments, the semiconductor layer 100' does not physically contact the inner spacers 98. In other embodiments, the semiconductor layer 100' may physically contact some of the sidewalls of the inner spacers 98. In some examples, the semiconductor layer 100' may be considered as a portion of the corresponding epitaxial source / drain region 100. In other embodiments, an insulating layer (not shown) may be deposited in the source / drain recess 96 before forming the semiconductor layer 100' and / or the epitaxial source / drain region 100 in the source / drain recess 96. For example, the insulating layer may include a silicon nitride layer, a silicon oxide layer, or the like.

[0112] In some embodiments, the epitaxial source / drain regions 100 apply stress to the channel regions of the second nanostructure 66 in the n-type region 50N and / or the p-type region 50P to improve performance. The epitaxial source / drain regions 100 are formed in the source / drain recess 96 such that the dummy gates 84 of the p-type region 50P are each located between individual adjacent pairs of epitaxial source / drain regions 100. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain regions 100 from the dummy gates 84, while inner spacers 98 are used to provide a suitable lateral distance between the epitaxial source / drain regions 100 and the second nanostructure 66, so that the epitaxial source / drain regions 100 are not shorted to the gate subsequently formed in the final nanostructure field-effect transistor.

[0113] The epitaxial source / drain region 100 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the n-type epitaxial source / drain region 100 is epitaxially grown within the source / drain recess 96 in the n-type region 50N. The n-type epitaxial source / drain region 100 can comprise any acceptable material suitable for an n-type nanostructure field-effect transistor. For example, if the second nanostructure 66 is silicon, the material comprising the n-type epitaxial source / drain region 100 can be subjected to tensile stress on the second nanostructure 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like.

[0114] The epitaxial source / drain region 100 in the p-type region 50P can be formed by masking the n-type region 50N. The p-type epitaxial source / drain region 100 is then epitaxially grown within the source / drain recess 96 in the p-type region 50P. The p-type epitaxial source / drain region 100 can include any acceptable material suitable for a p-type nanostructure field-effect transistor. For example, if the second nanostructure 66 is silicon, the material comprising the p-type epitaxial source / drain region 100 can be subjected to compressive stress on the second nanostructure 66, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like.

[0115] Dopant can be implanted into the epitaxial source / drain region 100, the second nanostructure 66, and / or the substrate 50 to form the source / drain region, which can be similar to the above-described process for forming lightly doped source / drain regions. Annealing can then be performed. The impurity concentration of the source / drain region can be between approximately 1 x 10⁻⁶. 19 atoms / cm 3 To approximately 1x10 21 atoms / cm 3 Between. The n-type and / or p-type impurities used in the source / drain regions can be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 100 can be doped in situ during growth.

[0116] Epitaxial source / drain regions 100 are formed in the n-type region 50N and the p-type region 50P using an epitaxial process, resulting in a crystal plane on the upper surface of the epitaxial source / drain region 100 that extends laterally outward beyond the sidewalls of the second nanostructure 66. In some embodiments, adjacent epitaxial source / drain regions 100 remain separated after the epitaxial process is completed, such as... Figure 14C As shown. In other embodiments, these crystal planes cause adjacent epitaxial source / drain regions 100 of the same nanostructure field-effect transistor to merge, such as Figure 14D As shown. In Figure 14C and 14D In the illustrated embodiment, fin spacers 94 may be formed on the upper surface of the shallow trench isolation region 70 to block epitaxial growth. In some other embodiments, the fin spacers 94 may cover a portion of the sidewall of the second nanostructure 66 to further block epitaxial growth. In some other embodiments, the spacer etching step used to form the fin spacers 94 may be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the shallow trench isolation region 70.

[0117] The n-type epitaxial source / drain region 100 and / or the p-type epitaxial source / drain region 100 may include one or more semiconductor material layers. The epitaxial source / drain region 100 may employ any number of semiconductor material layers. Each semiconductor material layer may be composed of different semiconductor materials and may be doped to different dopant concentrations. In an embodiment where the epitaxial source / drain region 100 includes three semiconductor material layers, a first semiconductor material layer may be deposited, a second semiconductor material layer may be deposited on the first semiconductor material layer, and a third semiconductor material layer may be deposited on the second semiconductor material layer. In some embodiments, the dopant concentration of the first semiconductor material layer may be less than the dopant concentration of the second semiconductor material layer and greater than the dopant concentration of the third semiconductor material layer. Other semiconductor material layers, dopant concentrations, or arrangements are also possible.

[0118] exist Figures 15A to 15D In this process, a first interlayer dielectric layer 104 is deposited on the epitaxial source / drain region 100, fin spacers 94, gate spacers 92, mask 86 (if present), and / or dummy gate 84. The first interlayer dielectric layer 104 may be composed of a dielectric material, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. Suitable dielectric materials may include silicon oxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials formed by any acceptable process may also be used. In some examples, the first interlayer dielectric layer 104 may extend below the upper surface of the shallow trench isolation region 70 and / or below the lower surface of the epitaxial source / drain region 100. In some embodiments, a capping layer (not shown) is formed on the first interlayer dielectric layer 104. For example, the capping layer can be formed by using a dry or wet etching process to recess the first interlayer dielectric layer 104, followed by depositing dielectric material on the structure. The dielectric material may include one or more materials such as silicon nitride, silicon oxynitride, or the like. A planarization process, such as chemical mechanical polishing or a polishing process, can then be performed to remove excess dielectric material from the structure, leaving the dielectric material remaining on the first interlayer dielectric layer 104 to form the capping layer.

[0119] In some embodiments, a contact etch stop layer 102 is formed between the first interlayer dielectric layer 104 and the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), and / or dummy gate 84. The contact etch stop layer 102 may be composed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, a combination thereof, or the like, which has high etch selectivity relative to the first interlayer dielectric layer 104, and its formation method may employ any suitable deposition process such as chemical vapor deposition, atomic layer deposition, or similar processes.

[0120] exist Figures 16A to 16DIn some embodiments, a removal process is performed to make the upper surface of the first interlayer dielectric layer 104 flush with the upper surfaces of the gate spacer 92 and the dummy gate 84. In some embodiments, a planarization process removes the mask 86 and portions of the gate spacer 92 along the sidewalls of the mask 86. The removal process may include planarization processes such as chemical mechanical polishing, polishing, etch-back, combinations thereof, or similar processes. After the planarization process, the upper surfaces of the first interlayer dielectric layer 104, the gate spacer 92, and the dummy gate 84 may be substantially flush with or coplanar (in process variations). Furthermore, the upper surface of the dummy gate 84 may be exposed from the first interlayer dielectric layer 104. In other embodiments, the planarization process does not remove the mask 86. In these embodiments, after the planarization process, the upper surfaces of the first interlayer dielectric layer 104, the gate spacer 92, and the mask 86 may be substantially flush with or coplanar (in process variations).

[0121] exist Figures 17A to 17D In this process, one or more etching steps are used to remove the mask 86 (if present) and the dummy gate 84 to form a recess 108 between the gate spacers 92. In some embodiments, the dummy gate 84 and the dummy dielectric layer 82 may be removed by an isotropic dry etching process. For example, the etching process may include a dry etching process in which the reactive gas selectively etches the material of the dummy gate 84 at a rate greater than the rate at which the material of the first interlayer dielectric layer 104 and the gate spacers 92 are etched. The dummy dielectric layer 82 may serve as an etch stop layer when the dummy gate 84 is etched away. After the dummy gate 84 is removed, the dummy dielectric layer 82 may be removed.

[0122] exist Figures 18A to 18D In some embodiments, the dummy region 72 is removed to extend the recess 108. Methods for removing the dummy region 72 may include performing an isotropic etching process such as wet etching or a similar process. The etchant used in the etching process may be selective for the material of the dummy region 72, while the second nanostructure 66 remains relatively unetched compared to the dummy region 72. In some embodiments, the shallow trench isolation region 70 may be at least partially etched when removing the dummy region 72, but etching parameters (such as time) for removing the dummy region 72 can be controlled to reduce the total loss of the shallow trench isolation region 70. In other embodiments, a hard mask may protect the shallow trench isolation region 70 from etching, and the hard mask may be used in conjunction with… Figure 5A and Figure 5B The above-described hard mask.

[0123] The dummy material 71 in the dummy area 72 can be completely removed, or a residue of the dummy material 71 can be left on some sidewall portions of the inner spacer 98 in the recess 108 (see...). Figure 20After removing the dummy region 72, each recess 108 exposes a portion of the second nanostructure 66, which can serve as a channel region for the subsequently completed nanostructure field-effect transistor. The portion of the second nanostructure 66 serving as the channel region can be located between adjacent pairs of epitaxial source / drain regions 100.

[0124] In some examples, replacing the first nanostructure 64 with a dummy region 72 reduces the risk of unwanted etching of the epitaxial source / drain regions 100 and / or the second nanostructure 66 near the fin end region 51. For example, the etching process used to remove the dummy region 72 is more selective than the etching process used to remove the first nanostructure 64. In this manner, using the dummy region 72 and more selective etching reduces the risk of unwanted etching of the second nanostructure 66. In some examples, unwanted etching of the second nanostructure 66 in the fin end region 51 may cause adjacent epitaxial source / drain regions 100 to be etched or damaged. In summary, using the dummy region 72 and more selective etching reduces the etching of the second nanostructure 66 in the fin end region 51, thus reducing or eliminating the risk of damage to the epitaxial source / drain regions 100 near the fin end region 51. In some examples, the probability of damage to the epitaxial source / drain region 100 can be reduced or eliminated in some fin end regions 51 of a continuous fin structure formed by fins 62 with different offsets and / or widths (described in detail below).

[0125] exist Figures 19A to 19D In some embodiments, a gate dielectric layer 110 and a gate 112 are formed for the replacement gate structure. The gate dielectric layer 110 is compliantly deposited in the recess 108. The gate dielectric layer 110 may be formed on the upper surface and sidewalls of the substrate 50, and on the exposed upper surface, sidewalls, and lower surface of the second nanostructure 66. The gate dielectric layer 110 may also be deposited on the upper surface of the first interlayer dielectric layer 104, the contact etch stop layer 102, the gate spacer 92, and the shallow trench isolation region 70.

[0126] In some embodiments, the gate dielectric layer 110 includes one or more dielectric layers such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, the gate dielectric layer 110 may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 110 includes a dielectric material with a high dielectric constant (greater than about 7.0), such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or metal oxides or silicates of combinations thereof. The structures of the gate dielectric layer 110 in the n-type region 50N and the p-type region 50P may be the same or different. Methods for forming the gate dielectric layer 110 may include molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or similar methods.

[0127] Gate 112 may be deposited on gate dielectric layer 110 and fill the remaining portion of recess 108. Gate 112 may comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figure 19A , 19B The 19D display shows a single-layer gate 112, which may include any number of pad layers, any number of work function adjustment layers, and conductive filler material. The gate 112, which may be a combination of any layered structures, is deposited on the surface of the second nanostructure 66.

[0128] Gate dielectric layers 110 in both the n-type region 50N and the p-type region 50P can be formed simultaneously, with each region's gate dielectric layer 110 made of the same material. Gates 112 in both the n-type region 50N and the p-type region 50P can also be formed simultaneously, with each region's gate 112 made of the same material. In some embodiments, the gate dielectric layers 110 in the n-type region 50N and the p-type region 50P can be formed by separate processes, allowing each region's gate dielectric layer 110 to be made of different materials and / or have different numbers of layers; and / or the gates 112 in the n-type region 50N and the p-type region 50P can be formed by separate processes, allowing each region's gate 112 to be made of different materials and / or have different numbers of layers. When using separate processes, suitable areas can be masked and exposed through various masking steps.

[0129] After filling the recess 108, a planarization process such as chemical mechanical polishing can be performed to remove excess material from the gate dielectric layer 110 and gate 112 above the upper surface of the first interlayer dielectric layer 104. Therefore, the remaining material of gate 112 and gate dielectric layer 110 can form the replacement gate structure of the final nanostructure field-effect transistor. Gate 112 and gate dielectric layer 110 can be considered together as a gate structure or gate stack.

[0130] Figure 20 yes Figure 19A Detailed diagrams of various units, including epitaxial source / drain regions 100, gate dielectric layer 110, gate 112, second nanostructure 66, and inner spacers 98. Figure 20 This can be a partially enlarged view of a nanostructured field-effect transistor in an n-type 50N or p-type 50P region. Figure 20 In some embodiments shown, residues of the dummy material 71 may remain on the inner spacer 98, for example, between the inner spacer 98 and the gate dielectric layer 110. For instance, the dummy region 72 may not be completely removed, and the gate dielectric layer 110 may be formed on the retained dummy material 71 in the dummy region 72. Since the dummy material 71 is an insulating material (such as silicon oxide or the like), the retained residue does not significantly affect the electrical performance of the final device.

[0131] exist Figure 21A and Figure 21B In some embodiments, a gate isolation region 120 is formed within the gate structure. The gate isolation region 120 separates (e.g., cleaves) the gate structure into independent gate structures, which may be physically and / or electrically isolated from each other. In some embodiments, the gate isolation region 120 may be formed by first forming a trench (not shown) extending through the gate structure (e.g., through the gate 112 and the gate dielectric layer 110). The trench may be formed using suitable photolithography and etching techniques. The etching may be performed using wet etching and / or dry etching processes, which may be anisotropic. An insulating material may then be filled into the trench. The insulating material may include one or more dielectric materials such as silicon nitride, silicon oxide, the like, or combinations thereof. In some examples, a pad or the like may be deposited in the trench before the insulating material is deposited. A planarization process, such as a chemical mechanical polishing process, a polishing process, or a similar process, may then be performed to remove excess insulating material. The remaining portion of the insulating material forms the gate isolation region 120. After the planarization process, the gate structure, gate isolation region 120, first interlayer dielectric layer 104, and the upper surface of the gate spacer 92 can be flush or coplanar.

[0132] The gate isolation region 120 may extend longitudinally (parallel to the fin 62) and may extend between adjacent fins 62. For example... Figure 21B As shown, the gate isolation region 120 extends completely through the gate structure and into the shallow trench isolation region 70. The gate isolation region 120 may extend below the upper surface of the shallow trench isolation region 70. Since the gate isolation region 120 is formed after the gate structure is formed, the gate dielectric layer 110 does not cover the sidewalls of the gate isolation region 120, but the location where the gate dielectric layer 110 physically contacts the lower portion of the gate isolation region 120 may be the location where the gate isolation region 120 passes through the gate dielectric layer 110. In summary, the gate 112 covers the upper sidewalls of the gate isolation region 120. In embodiments where the gate 112 contains multiple layers (such as a pad layer, a work function adjustment layer, a conductive filler material, or the like), the location where each layer of the gate 112 physically contacts the gate isolation region 120 may be the location where the gate isolation region 120 passes through the layers of the gate 112. In some examples, the conductive filler material of the gate 112 may cover the upper sidewalls of the gate isolation region 120. Figure 21B The gate isolation region 120 shown is one example, but the gate isolation region 120 may have other heights, widths, or sidewall profiles than those shown in the figure. The gate isolation region 120 may be formed as appropriate, and other embodiments do not form a gate isolation region 120.

[0133] Figures 22A to 27DThis is a diagram showing the formation of isolation regions 125 between fins 62 in some embodiments. Isolation regions 125 can physically separate adjacent fins 62. In some examples, isolation regions 125 can separate (cut) continuous fin structures (detailed below) into individual fins 62, which can be physically and electrically isolated from each other. Isolation regions 125 can also separate gate structures into individual gate structures, which can be physically and / or electrically isolated from each other. In some examples, isolation regions 125 can be considered as isolation structures, dielectric plugs, dummy fins, or the like. In some examples, isolation regions 125 can be considered as isolation regions of continuous metal on-diffusion edge (CMODE), cut metal on-diffusion edge (CMODE), or continuous polysilicon on-diffusion edge (CPODE).

[0134] exist Figures 22A to 22D In this process, a hard mask layer 122 is formed on the gate structure, the first interlayer dielectric layer 104, the gate spacer 92, and the gate isolation region 120. In some embodiments, the hard mask layer 122 may be a single layer of a suitable dielectric material such as silicon nitride, silicon oxynitride, or the like. In some embodiments, the hard mask layer 122 is a multilayer structure containing layers of different materials. For example, the hard mask layer 122 may include a silicon layer sandwiched between two silicon nitride layers. The material of the hard mask layer 122 may be formed using suitable techniques, such as chemical vapor deposition or similar techniques. Other materials or formation techniques are also possible.

[0135] exist Figures 23A to 23D In some embodiments, patterned openings 123 are formed in the hard mask layer 122. Openings 123 define areas in the structure that are subsequently replaced by isolation regions 125. For example... Figures 23A to 2 As shown in Figure 3, the opening 123 exposes a portion of the gate 112. (As shown in Figure 3) Figure 23B As shown, opening 123 exposes the gate structure on one side of gate isolation region 120, while hard mask layer 122 still covers the gate structure on the opposite side of gate isolation region 120. Figure 23DAs shown, opening 123 exposes the gate structure adjacent to the fin end region 51. The opening 123 can be formed using suitable photolithography and etching techniques. For example, an etch mask, such as photoresist, a multilayer mask structure, or the like, can be formed on the hard mask layer 122, and the etch mask can be patterned. The pattern of the etch mask corresponds to the opening 123. The pattern can then be transferred to the hard mask layer 122 using an etching process to form the opening 123. The etching process can include one or more wet etching processes or dry etching processes, which can be anisotropic. The etch mask can then be removed using suitable techniques such as etching, ashing, polishing, or similar techniques.

[0136] exist Figures 24A to 24D In some embodiments, a portion of the gate structure exposed by opening 123 is removed. In some embodiments, the method for removing a portion of the gate structure may employ one or more selective etching processes that etch the gate 112 and the gate dielectric layer 110 without significantly etching the second nanostructure 66, fins 62, gate spacers 92, inner spacers 98, shallow trench isolation region 70, and / or gate isolation region 120. The etching process may include a wet etching process or a dry etching process, which may be isotropic or anisotropic. For example, some embodiments employ a wet etching process to remove the gate structure. After the etching process, the gate 112 and the gate dielectric layer 110 in the exposed portion of the gate structure are removed (e.g., completely removed), and opening 123 may extend downward through the gate structure to expose the upper surface of the shallow trench isolation region 70. Opening 123 may expose the second nanostructure 66 that previously surrounded the exposed portion of the gate structure. In other words, the upper surface, lower surface, and / or sidewall surface of the second nanostructure 66 may be exposed after the etching process. Furthermore, the upper portion of the fin 62 and the upper surface of the shallow trench isolation region 70 can be exposed. Removing the gate structure in the opening 123 exposes the sidewall surface of the fin end region 51. For example, the sidewalls of the gate isolation region 120, the gate spacer 92, the inner spacer 98, and the second nanostructure 66 can be exposed. In embodiments where the gate isolation region 120 is not formed, the selective etching process can be anisotropic, which can reduce damage (or unintended etching) to the sidewalls of the gate 112 exposed by the opening 123.

[0137] exist Figures 25A to 25DIn some embodiments, an anisotropic etching process is performed to extend the opening 123 through the second nanostructure 66 and the fin 62. In some embodiments, portions of the second nanostructure 66 and the fin 62 exposed by the opening 123 may be completely removed. In some embodiments, the opening 123 may extend through a portion of the shallow trench isolation region 70 into the substrate 50. For example, the anisotropic etching process may include a dry plasma etching process or a similar process. In some embodiments, the anisotropic etching process may include multiple cycles of passivation layer deposition steps and anisotropic etching steps. The anisotropic etching process may be performed until the opening 123 reaches a target depth, such as below the depth of the upper surface of the substrate 50.

[0138] exist Figures 26A to 26D In this process, one or more insulating materials are deposited on the rigid mask layer 122 and within the opening 123 to form the isolation region 125. In some embodiments, a pad layer 124 is compliantly deposited on the rigid mask layer 122 and within the opening 123. The pad layer 124 may comprise a single layer or multiple layers of insulating material. A filler material 126 is then deposited on the pad layer 124 to fill the opening 123. For example, the insulating material may comprise dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, low dielectric constant materials, the like, combinations thereof, or multiple layers thereof. Any suitable formation technique may be employed, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar techniques. For example, in some embodiments, the pad layer 124 comprises an oxide material, while the filler material 126 comprises a nitride material. Other materials, layers, or formation techniques are also possible.

[0139] exist Figures 27A to 27D In some embodiments, a planarization process is performed to remove excess insulating material and hard mask layer 122. Retained portions of the insulating material (such as padding layer 124 and filler material 126) form isolation region 125. For example, the planarization process may include a chemical mechanical polishing process, a polishing process, or a similar process. After the planarization process, the isolation region 125, the gate structure, the gate spacer 92, and the upper surface of the first interlayer dielectric layer 104 may be flush with or coplanar. In some embodiments, the isolation region 125 may extend along a portion of the fin end region 51 and may separate adjacent fin end regions 51. Figure 27B and 27D As shown, the layered structure of the gate structure (such as the gate dielectric layer 110 and the gate 112) may have a gate isolation region 120 with the isolation region 125, so the layered structure of the gate structure does not physically contact the sidewall of the isolation region 125. In addition, since the isolation region 125 is formed after the gate structure is formed, the gate dielectric layer 110 does not extend along the sidewall of the isolation region 125.

[0140] exist Figures 28A to 28CIn some embodiments, a second interlayer dielectric layer 130 is deposited on the gate spacer 92, the contact etch stop layer 102, the first interlayer dielectric layer 104, the gate structure, the gate isolation region 120, and the isolation region 125. In some embodiments, the second interlayer dielectric layer 130 is a flowable chemical vapor deposition (CVD) second interlayer dielectric layer 130. In some embodiments, the second interlayer dielectric layer 130 is composed of a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and its formation method can be any suitable deposition process such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or similar processes.

[0141] In some embodiments, an etch stop layer 128 may be formed prior to the deposition of the second interlayer dielectric layer 130. The etch stop layer 128 may be composed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by any suitable deposition process such as chemical vapor deposition, atomic layer deposition, or similar processes, and has high etch selectivity relative to the second interlayer dielectric layer 130.

[0142] In other embodiments, the gate structure (containing the gate dielectric layer 110 and the corresponding upper gate 112) is recessed, so that the recess (not shown) is formed directly on the gate structure between portions of the gate spacers 92 on both sides. A gate mask (not shown) containing one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like can be filled into the recess, followed by a planarization process to remove excess dielectric material. The gate contact (as described below, gate contact 132) then formed passes through the gate mask to contact the upper surface of the recessed gate 112.

[0143] exist Figures 28A to 28C In this configuration, a gate contact 132 and a source / drain contact 134 are formed to contact the gate 112 and the epitaxial source / drain region 100, respectively. The gate contact 132 is physically and electrically coupled to the gate 112. The source / drain contact 134 is physically and electrically coupled to the epitaxial source / drain region 100.

[0144] In the example of forming the gate contact 132 and the source / drain contact 134, the opening used to form the gate contact 132 passes through the second interlayer dielectric layer 130 and the etch stop layer 128, and the opening used to form the source / drain contact 134 passes through the second interlayer dielectric layer 130, the etch stop layer 128, the first interlayer dielectric layer 104, and the contact etch stop layer 102. The openings can be formed using acceptable photolithography and etching techniques. A pad (not shown, such as a diffusion barrier layer, adhesive layer, or the like) and conductive material are formed in the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of the second interlayer dielectric layer 130. The retained pads and conductive material can form the gate contact 132 and the source / drain contact 134 within the opening. The gate contact 132 and the source / drain contact 134 can be formed by separate processes or the same process. Although the gate contact 132 and the source / drain contact 134 are shown in the same cross-section, it should be understood that the gate contact 132 and the source / drain contact 134 can each be formed in different cross-sections to avoid short-circuiting of the contacts.

[0145] A metal-semiconductor alloy region 133 may be formed at the interface between the epitaxial source / drain region 100 and the source / drain junction 134, depending on the situation. The metal-semiconductor alloy region 133 may be a silicide region composed of metal silicides (such as titanium silicides, cobalt silicides, nickel silicides, or the like), a germanide region composed of metal germanides (such as titanium germanides, cobalt germanides, nickel germanides, or the like), a silicongermide region composed of metal silicides and metal germanides, or the like. Metal may be deposited in the opening used for the source / drain junction 134 before the material forming the source / drain junction 134, followed by a thermal annealing process to form the metal-semiconductor alloy region 133. The metal can be any metal-semiconductor alloy capable of reacting with the semiconductor material (such as silicon, silicon carbide, silicon germanium, germanium, or the like) of the epitaxial source / drain region 100 to form a drop resistance, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be formed by deposition processes such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, or similar processes. After the thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the opening used for the source / drain contact 134, for example, from the surface of the metal-semiconductor alloy region 133. The material for forming the source / drain contact 134 can then be applied to the metal-semiconductor alloy region 133.

[0146] In some embodiments, the continuous fin structure 61 can be divided (e.g., cut) into multiple isolated fins 62 by an isolation region 125. In summary, Figures 29A to 29CThis is a plan view of the continuous fin structure 61 before separation in some embodiments. Figures 30A to 30D This is a plan view after the continuous fin structure 61 is separated by the isolation region 125 in some embodiments. The continuous fin structure 61 and fin 62 are illustrative examples, and the continuous fin structure 61 and fin 62 in other embodiments may have other sizes, shapes, or configurations. Figures 31A to 31G Non-limiting examples of continuous fin-like structures 61 are also shown, detailed below. Although Figures 29A to 31G Using continuous fin structures 61 and fins 62 as an example, the stacking of second nanostructures 66 typically exists on top of continuous fin structures 61 and fins 62. For example, isolation region 125 can also separate a continuous stack of second nanostructures 66 into multiple isolated stacks of second nanostructures 66. In summary, the following description of continuous fin structures 61 and fins 62 can also be applied to the stacking of second nanostructures 66 on continuous fin structures 61 and fins 62.

[0147] Figures 29A to 29C This is a plan view of a continuous fin structure 61 in some embodiments. The continuous fin structure 61 may be a continuous structure formed by fin portions 62' (such as fin portion 62A', fin portion 62B', and the like), which may then be separated into corresponding individual fins 62 (such as fin 62A, fin 62B, and the like) by one or more isolation regions 125. The continuous fin structure 61 may be formed by appropriately patterning a multilayer stack 52, which may be combined with... Figure 3A and Figure 3B The explanation above is similar. In summary, the continuous fin structure 61 can be considered as a continuous structure formed from multiple layers stacked 52. The fin portions 62' of the continuous fin structure 61 may include fin portions 62' offset from each other and / or different fin portions 62' with different widths. For example... Figure 1 As shown, the longitudinal axis of the fin portion 62' extends parallel to section A-A', while the isolation region 125 may extend in a vertical direction, such as section B-B' or C-C'. In summary, in some embodiments, two fin portions 62' (e.g., fin portion 62A' and fin portion 62B') may be offset (e.g., vertically offset) in a direction perpendicular to the longitudinal direction of the fin portion 62'. For example, the offset direction may be parallel to the direction of section B-B' or C-C'. In the plan view, the sides of the continuous fin structure 61 may be stepped, because the sidewall of one fin portion 62' is vertically offset from the sidewall of the adjacent fin portion 62'. Forming the isolation region 125 to divide the continuous fin structure 61 into independent fins 62 allows the fins 62 of the device to be closer together, thereby reducing device size and increasing device density. Figures 29A to 29CThe fin tip region 51 and the offset tip region 51' of the continuous fin structure 61 are also shown. The offset tip region 51' is similar to the fin tip region 51, except that the offset tip region 51' is the tip region of the continuous fin structure 61 formed by the offset and / or different widths of the fin portion 62'. In summary, the offset tip region 51' may include a tip region located at the corner where different fin portions 62' of the continuous fin structure 61 meet. In some embodiments, an isolation region 125 is subsequently formed in or near the offset tip region 51'. In some examples, the aforementioned dummy region 72 can reduce damage to the second nanostructure 66 located in the offset tip region 51' and / or damage to the epitaxial source / drain region 100, which, in conjunction with... Figures 18A to 18D The explanation above is similar.

[0148] Figure 29A The continuous fin structure 61 shown includes a continuous, wider fin portion 62A' and a narrower fin portion 62B'. An isolation region 125 is then formed between the fin portions 62A' and 62B' to form isolated and separated fins 62A and 62B (see...). Figure 30A ).like Figure 29A As shown, fin-shaped portion 62A' and fin-shaped portion 62B' each have a fin-shaped end region 51. Since fin-shaped portion 62B' is narrower than fin-shaped portion 62A', the off-end region 51' of fin-shaped portion 62A' is adjacent to fin-shaped portion 62B'.

[0149] Figure 29B The continuous fin-like structure 61 and Figure 29A Similar to the continuous fin-like structure 61, the difference lies in Figure 29B The continuous fin structure 61 includes a wide fin portion 62A' and two narrow fin portions 62B' and 62C'. An isolation region 125 is then formed between the fin portions 62A' and 62B' and 62C' to form isolated and separated fins 62A to 62C (see...). Figure 30B ).like Figure 29B As shown, fin-shaped portions 62A', 62B', and 62C' each have a fin-like end region 51. Since fin-shaped portions 62B' and 62C' are narrower than fin-shaped portion 62A', the off-end region 51' of fin-shaped portion 62A' is located between fin-shaped portions 62B' and 62C'. In other embodiments, the continuous fin structure 61 may include a wide fin portion and more than two narrow fin portions.

[0150] Figure 29C The continuous fin-like structure 61 and Figure 29A Similar to the continuous fin-like structure 61, the difference lies in Figure 29CThe continuous fin structure 61 includes two offset fin portions 62A' and 62B'. Fin portions 62A' and 62B' may have the same width or different widths. An isolation region 125 is then formed between the fin portions 62A' and 62B' to form separate and isolated fins 62A and 62B (see...). Figure 30C ).like Figure 29C As shown, fin-like portions 62A' and 62B' each have a fin-like end region 51. Since fin-like portions 62A' and 62B' are offset from each other, fin-like portions 62A' and 62B' also each have an offset end region 51'.

[0151] Figures 30A to 30C After the formation of isolation zone 125, Figures 29A to 29C The continuous fin-like structure 61 is divided into individual fin-like structures 62. For example, Figure 30A The isolation zone 125 forms two separate fin-like structures 62A. Figure 30B The isolation zone 125 forms three separate fin-like structures 62A, 62B, and 62C, and Figure 30C The isolation zone 125 forms two separate fins 62A and 62B. The materials and techniques used to form the isolation zone 125 can be combined with... Figures 22A to 27D The explanation above is similar. For example... Figures 30A to 30C As shown, the isolation region 125 may be formed off-end region 51', such that the fin-off-end region 51 of the isolated fin 62 is formed on one or both sides of the isolation region 125. In some examples, the isolation region 125 can be used to make the separation distance S1 (e.g., end-to-end distance) of the fin 62 about 20 nm to about 80 nm, but other separation distances are also possible. In some examples, the isolation region 125 may be located at or near the fin end region 51 (e.g., end-to-end distance). Figure 30D (As shown), and the three isolation zones 125 will Figure 29A The continuous fin-like structure 61 is divided into fins 62A and 62B.

[0152] Figures 31A to 31G These are diagrams of various continuous fin structures 61 in some embodiments. Figures 31A to 31G The examples shown are not limiting examples, and other shapes, arrangements, or configurations of the continuous fin structure 61 are also possible. For example, the fin portions 62' of the continuous fin structure 61 (such as fin portion 62A', fin portion 62B, or the like) may have a width or offset different from that shown, or the fin portions 62' of a single continuous fin structure 61 may have a number or configuration different from that shown.

[0153] Figure 31A The continuous fin-like structure 61 shown is composed of fin-like portions 62A' and fin-like portions 62B'. For example, Figure 31AThe continuous fin structure 61 shown can be divided into fins 62A and fins 62B by the isolation region 125. The width WA of fin 62A is about 5 nm to about 120 nm, and the width WB of fin 62B is about 5 nm to about 120 nm, and the width WB is less than the width WA. The deviation D1 between fins 62A and fin 62B can be about 0 nm to about 115 nm, and the deviation D2 can be about 0 nm to about 115 nm, therefore D1 + D2 = WA - WB. Figure 31B The continuous fin structure 61 shown is formed by fin-shaped portions 62A' and fin-shaped portions 62B'. The width WA of fin-shaped portion 62A' is about 5 nm to about 120 nm, and the width WB of fin-shaped portion 62B' is about 5 nm to about 120 nm, with the width WB being less than the width WA. The deviation D1 between fin-shaped portions 62A' and fin-shaped portions 62B' can be about 0 nm to about 115 nm, therefore D1 = WA - WB. Figure 31C The continuous fin structure 61 shown is formed by fin-shaped portions 62A' and fin-shaped portions 62B'. The width WA of fin-shaped portion 62A' is about 5 nm to about 120 nm, and the width WB of fin-shaped portion 62B' is about 5 nm to about 120 nm, with the width WB being less than the width WA. The deviation D2 between fin-shaped portions 62A' and fin-shaped portions 62B' can be about 0 nm to about 115 nm, therefore D2 = WA - WB.

[0154] Figure 31D The continuous fin-like structure 61 shown is formed by fin-like portions 62A' and fin-like portions 62B'. The width WA of fin-like portion 62A' is about 5 nm to about 120 nm, and the width WB of fin-like portion 62B' is about 5 nm to about 120 nm, wherein fin-like portion 62A' is offset from fin-like portion 62B'. The offset D1 between fin-like portion 62A' and fin-like portion 62B' can be between about 0 nm and about 115 nm, and the offset D2 can be between about 0 nm and about 115 nm.

[0155] Figure 31E The continuous fin structure 61 shown is formed by fin-shaped portions 62A', 62B', and 62C'. The width WA of fin-shaped portion 62A' is approximately 20 nm to approximately 120 nm, the width WB of fin-shaped portion 62B' is approximately 5 nm to approximately 120 nm, and the width WC of fin-shaped portion 62C' is approximately 5 nm to approximately 120 nm, such that widths WB and WC are each smaller than width WA. The deviation D3 between fins 62B and fins 62C is approximately 5 nm to approximately 110 nm, therefore WB + WC + D3 = WA. Figure 31FThe continuous fin structure 61 shown is formed by fin-shaped portions 62A', 62B', and 62C'. The width WA of fin-shaped portion 62A' is approximately 20 nm to approximately 120 nm, the width WB of fin-shaped portion 62B' is approximately 5 nm to approximately 120 nm, and the width WC of fin-shaped portion 62C' is approximately 5 nm to approximately 120 nm, such that widths WB and WC are each smaller than width WA. The deviation D1 between fin 62B and fin 62A can be approximately 0 nm to approximately 105 nm, the deviation D2 between fin 62C and fin 62A can be approximately 0 nm to approximately 105 nm, and the deviation D3 between fin 62B and fin 62C can be approximately 5 nm to approximately 110 nm. Therefore, WB + WC + D1 + D2 + D3 = WA. The continuous fin structure 61 shown in Figure 31 is formed by fin-shaped portions 62A', 62B', and 62C'. The width WA of fin-shaped portion 62A' is approximately 15 nm to approximately 120 nm, the width WB of fin-shaped portion 62B' is approximately 5 nm to approximately 120 nm, and the width WC of fin-shaped portion 62C' is approximately 5 nm to approximately 120 nm. Fin-shaped portion 62B' is offset from fin-shaped portions 62B' and 62C'. The offset D1 between fin-shaped portion 62B and fin-shaped portion 62A can be approximately 0 nm to approximately 105 nm, the offset D2 between fin-shaped portion 62C and fin-shaped portion 62A can be approximately 0 nm to approximately 105 nm, and the offset D3 between fin-shaped portion 62B and fin-shaped portion 62C can be approximately 5 nm to approximately 110 nm. Other widths or offsets are also possible.

[0156] Figures 32A to 39 This is an intermediate step in forming a nanostructured field-effect transistor from the continuous fin structure 61 in some embodiments. As detailed below, the isolation region 125 divides the continuous fin structure 61 into individual fins 62A to 62E. Figures 32A to 39 Many materials, technologies, and structures are similar to a combination Figures 2 to 27D The above content is explained, and some details will not be repeated below. Figure 32A and Figure 32B This is a plan view of the continuous fin structure 61 in some embodiments. Similar to the above, the continuous fin structure 61 includes fins 62 and an upper second nanostructure 66. Figure 32A and Figure 32BAs shown, the continuous fin structure 61 includes fin portions 62A', 62B', 62C', 62D', and 62E', and some fin portions have different widths and / or offsets. The subsequently formed isolation region 125 divides the continuous fin structure 61 into a nanostructured field-effect transistor device containing fins 62A, a nanostructured field-effect transistor device containing fins 62B and 62C, and a nanostructured field-effect transistor device containing fins 62D and 62E. Each nanostructured field-effect transistor device may include one or more nanostructured field-effect transistors, which share the same gate structure.

[0157] Figure 32A The cross-section A1-A1' shown passes through fin-shaped portions 62B' and 62D', and the cross-section A2-A2' passes through fin-shaped portion 62A'. Cross-sections A1-A1' and A2-A2' are... Figure 1 The cross section A-A' in Figure 32 is similar to that in the cross section B1-B1' and B2-B2' in Figure 32. Figure 1 The cross section B-B' is similar. Figure 33A , Figure 34A , Figure 35A , Figure 36A ,and Figure 37A The sectional view shown follows a path similar to Figure 32A The section A1-A1' in the middle. Figure 33B , Figure 34B , Figure 35B , Figure 36B ,and Figure 37B The sectional view shown follows a path similar to Figure 32A The section A2-A2' in the middle. Figure 33C , Figure 34C , Figure 35C , Figure 36C ,and Figure 37C The sectional view shown follows a path similar to Figure 32A The section B1-B1' in the middle. Figure 33D , Figure 34D , Figure 35D , Figure 36D ,and Figure 37D The sectional view shown follows a path similar to Figure 32A The section B2-B2' in the middle.

[0158] Figure 32A The continuous fin-like structure 61 shown corresponds to Figure 3A and Figure 3B The process steps are shown. Figure 32B This is a plan view of the continuous fin structure 61 formed after the gate structure and gate isolation region 120 are formed in some embodiments. Figure 32B The continuous fin-like structure 61 shown corresponds to Figure 21A and Figure 21BThe process steps are shown. (As shown) Figure 32B As shown, the gate structure extends through fin portions 62A' to 62E' and through a portion of the continuous fin structure 61 between fin portions 62' and fin portions 62B' to 62E' (which includes the offset end region 51'). An example of the offset end region 51' is shown below. Figure 32A As shown.

[0159] Figures 33A to 33D Some embodiments show the structure after the hard mask layer 122 has been formed. Figures 33A to 33D The materials and technologies used in the structure shown can be combined with... Figures 2 to 22D The description is similar. In summary, the hard mask layer 122 can be compared with... Figures 22A to 22D The hard mask layer 122 is similar and can be formed by similar techniques.

[0160] exist Figures 34A to 34D In some embodiments, patterned openings 123 are formed in the hard mask layer 122. Openings 123 can be paired with... Figures 23A to 23D The opening 123 shown above is similar and can be formed by similar techniques. For example, the opening 123 exposes some gate structure, and in some examples the gate structure may be adjacent to the fin end region 51 and / or the gate isolation region 120.

[0161] exist Figures 35A to 35D In some embodiments, one or more etching processes are performed to extend the opening 123 through the gate structure, the second nanostructure 66, and the fin 62. In some embodiments, portions of the gate structure, the second nanostructure 66, and the fin 62 exposed by the opening 123 may be completely removed. The opening 123 may extend through a portion of the shallow trench isolation region 70 into the substrate 50. The etching technique used in extending the opening 123 may be compatible with... Figures 24A to 25D The above description is similar. For example, in some embodiments, the method for removing the gate structure may employ a wet etching process, while the method for removing the second nanostructure 66 and the fin 62 may employ an isotropic dry etching process.

[0162] After one or more etching processes, the lower surface of the opening 123 may be flat, recessed, convex, irregular, or have other shapes. For example, in some examples, the lower surface of the opening 123 may have a serrated or fan-shaped shape, such as... Figure 35C and Figure 35DAs shown. For example, the selectivity of one or more etching processes can be controlled to control the shape or profile of the lower surface of opening 123. For example, if the etching process etches oxide at a rate greater than that of silicon, the notches in the lower surface of opening 123 may correspond to locations where opening 123 extends through shallow trench isolation region 70, first interlayer dielectric layer 104, or the like. In another example, if the etching process etches silicon at a rate greater than that of oxide, the notches in the lower surface of opening 123 may correspond to locations where opening 123 extends through fin 62. In some examples, etching processes with approximately the same selectivity between silicon and oxide can result in a flatter lower surface of opening 123. For example, using more boron trichloride in the etching process can increase the etching rate of oxide relative to silicon, although other etchants or process gases are also possible. These are for illustrative purposes only, and other conditions, etching parameters, etchants, structural setups, or structural features may affect the shape of the lower surface of opening 123.

[0163] exist Figures 36A to 36D In some embodiments, the insulating material of the deposition isolation region 125 is deposited over the hard mask layer 122 and within the opening 123. The insulating material can be combined with... Figures 26A to 26D The content described above is similar and can be formed by similar techniques. For example, in some embodiments, a liner layer 124 is compliantly deposited, followed by the deposition of a filler material 126 on the liner layer 124 to fill the opening 123. In some embodiments, the liner layer 124 comprises an oxide material, while the filler material 126 comprises a nitride material. Other materials, layers, or formation techniques are also possible.

[0164] exist Figures 37A to 37D In some embodiments, a planarization process is performed to remove excess insulating material and the hard mask layer 122 to form the isolation region 125. After the planarization process, the remaining portions of the padding layer 124 and the filler material form the isolation region 125. The planarization process can be combined with... Figures 27A to 27D The description is similar to the one above. For example, the planarization process may include a chemical mechanical polishing process, a polishing process, or a similar process. In some embodiments, the isolation region 125 may extend along a portion of the fin end region 51 and may separate adjacent fin end regions 51. Subsequent processes may be performed, such as in conjunction with... Figures 28A to 28C Similar process steps are described above.

[0165] Figure 38 This is a plan view of fins 62A to 62E after the isolation zone 125 is formed in some embodiments. Figure 38 The floor plan can correspond to Figures 37A to 37D A sectional view. For example... Figure 38As shown, the isolation zone 125 can separate the continuous fin structure 61 into separate fins 62A, 62B, 62C, 62D, and 62E. Figure 38 The cross section A3-A3' shown passes through fins 62A and 62E, corresponding to... Figure 39 The sectional view. Section A3-A3' is similar to... Figure 1 Section A-A' in the middle. Figure 39 In some embodiments, Figure 38 Cross-sectional views of fins 62A and 62E. (See attached image.) Figure 39 As shown, the isolation zone 125 can separate the fins 62 and thus extends between the fin end regions 51.

[0166] The embodiments offer several advantages. The techniques described herein allow for the formation of isolation regions after the gate structure is formed without increasing the risk of etch damage to the nanostructures or source / drain regions. Forming isolation regions after the gate structure allows for smaller spacing between fins. Furthermore, forming isolation regions after, rather than before, the gate structure avoids process difficulties such as polysilicon deformation or structural bending. Using dummy regions as described herein improves the etch selectivity of exposed nanostructures before the gate structure is formed, reducing the risk of etch damage to the nanostructures or source / drain regions. Specifically, using dummy regions reduces the risk of etch damage to offset regions from fins and / or between fins of varying widths. Therefore, the techniques described herein can improve yield, increase device density, and improve layout flexibility.

[0167] In one embodiment, a method for forming a semiconductor device includes forming a fin-like structure on a substrate; forming a plurality of first nanostructures and a plurality of second nanostructures on the fin-like structure, wherein the first nanostructures and individual second nanostructures are continuous structures; forming a plurality of first dielectric dummy regions between the first nanostructures and a plurality of second dielectric dummy regions between the second nanostructures; forming a plurality of first source / drain regions adjacent to the first nanostructures and forming a plurality of second source / drain regions adjacent to the second nanostructures; performing an etching process to remove the first dielectric dummy regions and the second dielectric dummy regions; depositing a plurality of gate structure layers on the first nanostructures and the second nanostructures; and forming an isolation region between the first nanostructures and the second nanostructures, wherein the isolation region physically separates the first nanostructures and the second nanostructures. In one embodiment, the first dielectric dummy region comprises an oxide material. In one embodiment, the first nanostructure is wider than the second nanostructure. In one embodiment, the step of forming the first dielectric dummy region includes depositing a dielectric material on the first nanostructure and the second nanostructure; and etching the dielectric material to expose the sidewalls of the first nanostructure and the second nanostructure. In one embodiment, the isolation region extends below the upper surface of the substrate. In one embodiment, forming the isolation region includes forming an opening in the gate structure layer and depositing an insulating material in the opening. In one embodiment, the sidewalls of the first nanostructure are offset from the sidewalls of the second nanostructure. In one embodiment, the method further includes forming a gate isolation region extending through the gate structure layer.

[0168] In one embodiment, a method of forming a semiconductor device includes forming a first nanostructure stack adjacent to a second nanostructure stack, wherein the first nanostructure stack and the second nanostructure stack include a plurality of first nanostructures and a plurality of second nanostructures, wherein a first sidewall of the first nanostructure stack is adjacent to a second sidewall of the second nanostructure stack, and wherein the first sidewall is perpendicularly offset from the second sidewall; replacing the first nanostructures of the first nanostructure stack and the first nanostructure stack with a plurality of dielectric regions; replacing the dielectric regions of the first nanostructure stack and the dielectric regions of the second nanostructures with a continuous gate structure; and replacing a portion of the continuous gate structure with an isolation region, wherein the isolation region extends between the first nanostructure stack and the second nanostructure stack. In one embodiment, prior to the step of replacing a portion of the continuous gate structure with an isolation region, the first nanostructure stack and the second nanostructure stack are a continuous structure. In one embodiment, the first semiconductor material of the first nanostructure is different from the second semiconductor material of the second nanostructure. In one embodiment, the step of replacing a portion of the continuous gate structure with an isolation region includes performing a first etching process that removes a portion of the continuous gate structure to form an opening; performing a second etching process that removes a second nanostructure from the portion of the continuous gate structure to expand the opening; and filling the opening with an insulating material. In one embodiment, the step of replacing the dielectric region includes etching the dielectric region with an etchant, wherein the etchant selectively etches the dielectric region at a rate greater than the rate at which the second nanostructure is etched. In one embodiment, a portion of the dielectric region remains on the sidewall of the continuous gate structure.

[0169] In one embodiment, the semiconductor device includes a first fin and a second fin located on a semiconductor substrate, wherein a first width of the first fin is different from a second width of the second fin; a plurality of first nanostructures are located on the first fin; a plurality of second nanostructures are located on the second fin; a first gate structure is located on the first fin, wherein the first gate structure separates individual adjacent first nanostructures; and a second gate structure is located on the second fin, wherein the second gate structure separates individual adjacent second nanostructures; and an isolation structure extending from the first fin to the second fin, wherein the isolation structure protrudes into the semiconductor substrate. In one embodiment, the distance between the first fin and the second fin is 20 nm to 80 nm. In one embodiment, the semiconductor device further includes a shallow trench isolation region surrounding the first fin, wherein the isolation structure extends between the first fin and the shallow trench isolation region. In one embodiment, the difference between the first width and the second width is 5 nm to 115 nm. In one embodiment, the semiconductor device further includes a third fin located on the semiconductor substrate, wherein the isolation structure extends from the first fin to the third fin. In one embodiment, the semiconductor device further includes a plurality of third nanostructures located on a third fin, and a third gate structure located on the third fin, wherein the third gate structure separates individual adjacent third nanostructures. In one embodiment, the third width of the third fin is different from the first width. In one embodiment, the third width of the third fin is equal to the second width. In one embodiment, an isolation structure completely covers the sidewalls of the first fin. In one embodiment, an isolation structure completely covers the sidewalls of the second fin.

[0170] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A first fin and a second fin are located on a semiconductor substrate, wherein a first width of the first fin is different from a second width of the second fin; Multiple first nanostructures are located on the first fin; Multiple second nanostructures are located on the second fin; A first gate structure is located on the first fin, wherein the first gate structure separates individual adjacent first nanostructures; and A second gate structure is located on the second fin, wherein the second gate structure separates individual adjacent second nanostructures; and An isolation structure extends from the first fin to the second fin, wherein the isolation structure protrudes into the semiconductor substrate.

2. The semiconductor device as claimed in claim 1, characterized in that, The distance between the first fin and the second fin is 20 nm to 80 nm.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, It further includes a shallow trench isolation area surrounding the first fin, wherein the isolation structure extends between the first fin and the shallow trench isolation area.

4. The semiconductor device as claimed in claim 1 or 2, characterized in that, The difference between the first width and the second width is 5nm to 115nm.

5. The semiconductor device as claimed in claim 1 or 2, characterized in that, It further includes a third fin located on the semiconductor substrate, wherein the isolation structure extends from the first fin to the third fin.

6. The semiconductor device as claimed in claim 5, characterized in that, It further includes multiple third nanostructures located on the third fin, and a third gate structure located on the third fin, wherein the third gate structure separates individual adjacent multiple third nanostructures.

7. The semiconductor device as claimed in claim 5, characterized in that, The third width of the third fin is different from the first width.

8. The semiconductor device as claimed in claim 5, characterized in that, The third width of the third fin is equal to the second width.

9. The semiconductor device as claimed in claim 1 or 2, characterized in that, The isolation structure completely covers the sidewall of the first fin.

10. The semiconductor device as claimed in claim 1 or 2, characterized in that, The isolation structure completely covers the sidewall of the second fin.

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