Semiconductor device

Abstract

A semiconductor device includes a source / drain region, a first nanostructure adjacent to the source / drain region, a second nanostructure adjacent to the source / drain region, the second nanostructure disposed above the first nanostructure, a third nanostructure adjacent to the source / drain region, the third nanostructure disposed above the second nanostructure, and a gate structure surrounding the first nanostructure, the second nanostructure, and the third nanostructure. A first portion of the gate structure is disposed between the first nanostructure and the second nanostructure, and a second portion of the gate structure is disposed between the second nanostructure and the third nanostructure. A length of the second portion of the gate structure is less than a length of the first portion of the gate structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for forming the same, particularly the design of a gate structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally formed by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and components thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously shrinking the minimum feature size, enabling more components to be integrated into a given area. However, as the minimum feature size shrinks, additional problems arise that need to be solved. Utility Model Content

[0004] A semiconductor device includes: a source / drain region; a first nanostructure adjacent to the source / drain region; a second nanostructure adjacent to the source / drain region, the second nanostructure being disposed on the first nanostructure; a third nanostructure adjacent to the source / drain region, the third nanostructure being disposed on the second nanostructure; and a gate structure surrounding the first nanostructure, the second nanostructure, and the third nanostructure, wherein a first portion of the gate structure is disposed between the first nanostructure and the second nanostructure, a second portion of the gate structure is disposed between the second nanostructure and the third nanostructure, and the length of the second portion of the gate structure is less than the length of the first portion of the gate structure.

[0005] In some embodiments, the semiconductor device further includes: a first inner spacer between the source / drain region and a first portion of the gate structure; and a second inner spacer between the source / drain region and a second portion of the gate structure.

[0006] In some embodiments, the width of the second inner spacer is greater than the width of the first inner spacer.

[0007] In some embodiments, the gate structure includes: a gate dielectric; and a metal gate electrode on the gate dielectric.

[0008] In some embodiments, the semiconductor device further includes a fin, and a third portion of the gate structure is disposed between the first nanostructure and the fin, wherein the length of the third portion of the gate structure is greater than the length of the second portion of the gate structure.

[0009] A semiconductor device includes: a source / drain region; a nanostructure adjacent to the source / drain region; a gate structure surrounding the nanostructure; a first inner spacer between the gate structure and the source / drain region, the first inner spacer having a first width; and a second inner spacer between the gate structure and the source / drain region, the second inner spacer having a second width greater than the first width, the first inner spacer and the second inner spacer being disposed on opposite sides of the nanostructure.

[0010] In some embodiments, the gate structure includes a metal gate electrode.

[0011] In some embodiments, the metal gate electrode has a pyramid geometry.

[0012] In some embodiments, the gate structure further includes a compliant gate dielectric layer.

[0013] In some embodiments, the gate structure has a first gate length and a second gate length, the first gate length being adjacent to a first inner spacer and the second gate length being adjacent to a second inner spacer, wherein the first gate length is greater than the second gate length. Attached Figure Description

[0014] The embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this utility model.

[0015] Figure 1 The above is a perspective view illustrating an example of a nanostructured field-effect transistor, based on some embodiments.

[0016] Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B ,and Figure 21C This is a cross-sectional schematic diagram of an intermediate stage in the fabrication of a nanostructured field-effect transistor, according to some embodiments.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 20: Division of areas

[0019] 50: Base

[0020] 50N: N-type region

[0021] 50P: P-type area

[0022] 51A: First semiconductor layer

[0023] 51B: First semiconductor layer

[0024] 51C: First semiconductor layer

[0025] 52A: First Nanostructure

[0026] 52B: First Nanostructure

[0027] 52C: The First Nanostructure

[0028] 53A: Second semiconductor layer

[0029] 53B: Second semiconductor layer

[0030] 53C: Second semiconductor layer

[0031] 54: Second Nanostructure

[0032] 54A: Second Nanostructure

[0033] 54B: Second Nanostructure

[0034] 54C: Second Nanostructure

[0035] 55: Nanostructure stacking

[0036] 64: Multi-layer stacking

[0037] 66: Fins

[0038] 68: Shallow trench isolation zone

[0039] 70: Dummy gate dielectric

[0040] 71: Sacrificial Materials

[0041] 71A: Sacrificial Material

[0042] 71B: Sacrificial Material

[0043] 71C: Sacrificial Material

[0044] 72: Residue

[0045] 76: Dummy Gate

[0046] 78: Mask

[0047] 81: Gate spacer

[0048] 83: Fin spacers

[0049] 86: First Groove

[0050] 88A: Sidewall Groove

[0051] 88B: Sidewall Groove

[0052] 88C: Sidewall Groove

[0053] 91: Internal spacer

[0054] 91A: Inner spacer

[0055] 91B: Internal spacer

[0056] 91C: Internal spacer

[0057] 94: Contact Etching Stop Layer

[0058] 96: First interlayer dielectric

[0059] 98: Second groove

[0060] 100: Gate dielectric layer

[0061] 102: Gate electrode

[0062] 102A: Lower part

[0063] 102B: Central Region

[0064] 102C: Upper part

[0065] 104: Gate mask

[0066] 106: Interlayer dielectric

[0067] 108: Third Groove

[0068] 110: Silicide region

[0069] 112: Contact element

[0070] 114: Contact element

[0071] 192: Epitaxial source / drain region

[0072] 192A: First semiconductor material layer

[0073] 192B: Second semiconductor material layer

[0074] 192C: Third semiconductor material layer

[0075] 200: Sidewall spacers

[0076] A-A': Cross-section

[0077] B-B': Section

[0078] C-C': Cross section Detailed Implementation

[0079] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided service. Specific examples of components and configurations are described below to simplify the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, references to a first component being formed on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this utility model. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed.

[0080] Furthermore, spatially related terms such as “below,” “under,” “lower,” “lower,” “above,” “above,” and similar terms may be used here to describe the relationship between an element or component and other elements or components, as shown in the diagram. Spatially related terms are intended to cover different orientations of the element in use or operation besides those depicted in the diagram. When the device is rotated to other orientations (90° rotation or other orientations), the spatially relative descriptions used here can also be interpreted according to the orientation after rotation.

[0081] The embodiments described below refer in particular to a die comprising a nanostructure field-effect transistor (nano-FET). However, various embodiments may be applied to dies comprising other transistor types (e.g., stacked transistors or other transistors) to replace or incorporate nanostructure field-effect transistors.

[0082] In some embodiments, the methods and structures described herein provide a gate structure with a pyramid geometry. The methods described herein can employ a top-down etching process to create a pyramid geometry metal gate structure, wherein the metal gate extrusion window of the upper nanostructure metal gate layer is greater than that of the lower nanostructure metal gate layer. In some embodiments, the pyramid geometry is obtained by varying the width of the spacers. The wider the spacers, the narrower the portion of the gate electrode between the spacers. In some embodiments, increasing the width of the spacers can reduce the likelihood of damage paths crossing the spacers. However, reducing the width of the gate electrode may degrade device performance because the resistance of a narrower gate electrode increases. In the methods and structures described herein, the upper portion of the gate structure can be configured to reduce the likelihood of damage channels forming therein, while the lower portion of the gate structure can be configured to have a larger width and lower resistance. In some embodiments, multiple disposable films within a nanostructure stack combined with selective etching can create a tunable inner spacer profile. In some embodiments, selective etching can control the profile of the disposable films one by one. In some embodiments, the adjustable profile of the inner spacers can amplify the metal gate extrusion margin forming the gate structure and reduce resistive-capacitance (RC) delay.

[0083] Figure 1 These are perspective views illustrating examples of nanostructured field-effect transistors (e.g., nanowire field-effect transistors, nanosheet field-effect transistors, or other similar structures) based on some embodiments. For ease of illustration, [the following is a simplified diagram]. Figure 1Specific components are simplified and / or omitted. A nanostructured field-effect transistor includes a nanostructure stack 55 (e.g., nanosheet, nanowire, or other similar structure) on fins 66 of a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure stack 55 serves as the channel region of the nanostructured field-effect transistor. The nanostructure stack 55 may include P-type nanostructures, N-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude from adjacent shallow trench isolation regions 68. Although the shallow trench isolation regions 68 are described / illustrated as being separated from the substrate 50, as used herein, "substrate" may mean only a semiconductor substrate, or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom of the fins 66 is illustrated as a single, continuous material with the substrate 50, the bottom of the fins 66 and / or the substrate 50 may include a single material or multiple materials. In this document, fins 66 refer to portions extending between adjacent shallow trench isolation regions 68.

[0084] A gate dielectric layer 100 is located on the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure stack 55. A gate electrode 102 is located on the gate dielectric layer 100. Epitaxial source / drain regions 192 are disposed on the fins 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102. The source / drain regions 192 may represent sources or drains individually or collectively, depending on the context.

[0085] Some embodiments discussed herein are discussed in the full text regarding nanostructured field-effect transistors formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments are conceived for use with planar devices (such as planar field-effect transistors) or fin field-effect transistors (finFETs).

[0086] Figure 1 Further reference cross-sections for use in subsequent diagrams are illustrated. Cross-section A-A' is along the longitudinal axis of the gate electrode and, for example, perpendicular to the current direction between the epitaxial source / drain regions 192 of the nanostructured field-effect transistor. Cross-section B-B' is perpendicular to cross-section A-A' and parallel to the longitudinal axis of the fins 66 of the nanostructured field-effect transistor, and, for example, in the direction of the current between the epitaxial source / drain regions 192 of the nanostructured field-effect transistor. Cross-section C-C' is parallel to cross-section A-A' and extends through the epitaxial source / drain regions of the nanostructured field-effect transistor. These reference cross-sections are referenced in subsequent diagrams for clarity.

[0087] Figures 2 to 21CThis is a cross-sectional schematic diagram of an intermediate stage in the fabrication of a nanostructured field-effect transistor, according to some embodiments. Figures 2-4 , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A ,and Figure 21A Draw Figure 1 The reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 17C , Figure 18B , Figure 19B , Figure 20B ,and Figure 21B Draw Figure 1 The reference section B-B' is shown. Figure 7C , Figure 12C , Figure 12D , Figure 13C , Figure 18C , Figure 19C , Figure 20C ,and Figure 21C Draw Figure 1 The reference section C-C' is shown.

[0088] exist Figure 2In this configuration, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or other similar structures, which can be doped (e.g., with P-type or N-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon (Si) wafer. Generally, a semiconductor-on-insulator substrate consists of a semiconductor material film formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide (SiO) layer, or other similar materials. The insulating layer is provided on the substrate (typically a silicon or glass substrate). Other substrates (such as multilayer or gradient substrates) can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium (Ge); compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide (GaInP). Arsenic phosphide (GaInAsP); or combinations thereof.

[0089] Substrate 50 has an N-type region 50N and a P-type region 50P. The N-type region 50N can be used to form N-type devices (such as N-type metal oxide semiconductor (NMOS) transistors), for example, N-type nanostructure field-effect transistors, while the P-type region 50P can be used to form P-type devices (such as P-type metal oxide semiconductor (PMOS) transistors), for example, P-type nanostructure field-effect transistors. The N-type region 50N may be physically separated from the P-type region 50P (as shown in partition 20), and any number of device components (such as other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are illustrated, any number of N-type regions 50N and P-type regions 50P may be provided. Subsequent figures describe the process steps that may be performed in the N-type region 50N or the P-type region 50P, unless otherwise noted.

[0090] Continued Figure 2 In this process, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating first semiconductor layers 51A, 51B, and 51C (collectively referred to as the first semiconductor layer) and second semiconductor layers 53A, 53B, and 53C (collectively referred to as the second semiconductor layer). For illustrative purposes and as detailed below, the second semiconductor layer is removed, and the first semiconductor layer is patterned to form channel regions of a nanostructured field-effect transistor of N-type region 50N and P-type region 50P. In some embodiments, the second semiconductor layer may be removed from both N-type region 50N and P-type region 50P, and the first semiconductor layer may be patterned to form channel regions of a nanostructured field-effect transistor. For example, the channel regions in both N-type region 50N and P-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously.

[0091] In other embodiments, a first semiconductor layer may be removed from the P-type region 50P and a second semiconductor layer may be patterned to form a channel region of a nanostructured field-effect transistor, and a second semiconductor layer may be removed from the N-type region 50N and a first semiconductor layer may be patterned to form a channel region of a nanostructured field-effect transistor. In yet another embodiment, a first semiconductor layer may be removed from the N-type region 50N and a second semiconductor layer may be patterned to form a channel region of a nanostructured field-effect transistor, and a second semiconductor layer may be removed from the P-type region 50P and a first semiconductor layer may be patterned to form a channel region of a nanostructured field-effect transistor. In the above embodiments, the channel regions of the N-type region 50N and the P-type region 50P may have different material compositions. The first and second semiconductor layers may be selectively removed from each of the N-type region 50N and the P-type region 50P by additional masking and etching steps. For example, the channel region of the N-type region 50N may be a silicon channel region, while the channel region of the P-type region 50P may be a silicon-germanium channel region.

[0092] The illustration of the multilayer stack 64 includes a first semiconductor layer with three film layers and a second semiconductor layer with three film layers, for illustrative purposes. In some embodiments, the multilayer stack 64 may include any number of first and second semiconductor layers. Each film layer of the multilayer stack 64 may be epitaxially grown using chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or other similar processes.

[0093] In various embodiments, a first semiconductor layer may be formed using a first semiconductor material (such as silicon, germanium, or other similar materials), and a second semiconductor layer may be formed using a second semiconductor material (such as silicon, silicon carbide, or other similar materials). The first and second semiconductor materials may be materials with a high etch selectivity to each other. Thus, the first semiconductor layer of the first semiconductor material can be removed without significantly removing the second semiconductor layer of the second semiconductor material, thereby allowing the second semiconductor layer to be patterned to form the channel region of a nanostructured field-effect transistor.

[0094] Reference Figure 3According to some embodiments, fins 66 are formed in a substrate 50, and a nanostructure stack 55 is formed in a multilayer stack 64. In some embodiments, the nanostructure stack 55 and fins 66 can be formed in the multilayer stack 64 and substrate 50, respectively, by etching trenches in the multilayer stack 64 and substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), other similar processes, or combinations thereof. The etching can be anisotropic. During the etching process, a hard mask can be used to define the patterning of the fins 66 and the nanostructure stack 55. The hard mask can contain any suitable insulating material, such as oxides, nitrides, oxynitrides, oxycarbonitrides, or other similar materials. In some embodiments (not shown separately), the hard mask can be a multilayer structure. Hard masks can be formed on nanostructure stacks 55 using acceptable processes such as thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition, combinations thereof, or other similar materials.

[0095] The fins 66 and the nanostructure stack 55 can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins 66 and the nanostructure stack 55. Generally, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes to create patterns with, for example, smaller pitches than those obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern the fins 66 and the nanostructure stack 55.

[0096] The nanostructure stack 55 formed by etching the multilayer stack 64 can further form first nanostructures 52A, 52B, and 52C (collectively referred to as the first nanostructures) from a first semiconductor layer, and second nanostructures 54A, 54B, and 54C (collectively referred to as the second nanostructures) are defined by a second semiconductor layer. The first nanostructures and the second nanostructures can be further referred to as the nanostructure stack 55.

[0097] Figure 3The fins 66 are illustrated with equal widths for illustrative purposes. In some embodiments, the width of the fins 66 in the N-type region 50N may be greater than or less than the width of the fins 66 in the P-type region 50P. Furthermore, although each fin 66 and nanostructure stack 55 is illustrated with a consistent width throughout, in other embodiments, the fins 66 and / or nanostructure stack 55 may have tapered sidewalls, with the width of each fin 66 and / or nanostructure stack 55 continuously increasing in the direction toward the substrate 50. In this embodiment, each nanostructure stack 55 may have a different width and be trapezoidal.

[0098] exist Figure 4 Shallow trench isolation regions 68 are formed adjacent to fins 66. Shallow trench isolation regions 68 can be formed by depositing insulating material on the substrate 50, fins 66, and nanostructure stack 55, and between adjacent fins 66. The insulating material can be an oxide (such as silicon oxide), a nitride, other similar materials, or combinations thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), other similar methods, or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure stack 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, fins 66, and nanostructure stack 55. Then, a filler material is formed on the liner, as discussed above.

[0099] Then, a removal process is applied to the insulating material to remove excess insulating material from the nanostructure stack 55. In some embodiments, a planarization process (such as chemical mechanical polishing (CMP)), an etch-back process, a combination thereof, or other similar methods may be used. The planarization process exposes the nanostructure stack 55 such that, after the planarization process is completed, the top surface of the nanostructure stack 55 is flush with the top surface of the insulating material.

[0100] Then, the insulating material is etched to form shallow trench isolation regions 68. The insulating material is etched such that the upper portion of the fin 66 protrudes between adjacent shallow trench isolation regions 68. Furthermore, the top surface of the shallow trench isolation region 68 may have a flat surface, a convex surface, a concave surface (such as a dishing), or a combination thereof, as shown. The top surface of the shallow trench isolation region 68 can be formed to be flat, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to etch the shallow trench isolation region 68, such as processes selective for the insulating material (e.g., etching the insulating material at a higher rate than etching the fin 66 and the nanostructure stack 55). For example, oxides can be removed using, for example, diluted hydrofluoric acid (dHF) acid.

[0101] exist Figure 4 In this process, suitable wells (not shown separately) can be formed in the fins 66 and / or the nanostructure stack 55. In embodiments with different types of wells, photoresist or other masks (not shown separately) can be used to achieve different implantation steps for the N-type region 50N and the P-type region 50P. For example, photoresist can be formed on the fins 66 and the nanostructure stack 55 in the N-type region 50N and the P-type region 50P. The photoresist is patterned to expose the P-type region 50P. The photoresist can be formed using a spin-on coating technique, and the photoresist can be patterned using acceptable lithography techniques. Once the photoresist is patterned, N-type impurities are implanted in the P-type region 50P, and the photoresist can act as a mask to substantially prevent the implantation of N-type impurities into the N-type region 50N. The N-type impurities can be phosphorus (P), arsenic (As), antimony (Sb), or other similar materials, implanted in the region to about 10 13 atoms / cm 3 Up to 10 14 atoms / cm 3 The concentration range. After implantation, the photoresist is removed, such as through an acceptable ashing process.

[0102] Before or after the implantation of the P-type region 50P, photoresist or other masks (not shown separately) are formed on the fins 66 and nanostructure stack 55 in the P-type region 50P and the N-type region 50N. The photoresist is patterned to expose the N-type region 50N. The photoresist can be formed using spin coating technology, and the photoresist can be patterned using acceptable lithography techniques. Once the photoresist is patterned, P-type impurities can be implanted in the N-type region 50N, while the photoresist acts as a mask to substantially prevent the implantation of P-type impurities into the P-type region 50P. The P-type impurities can be boron (B), boron difluoride (BF2), indium (In), or other similar materials, implanted in the region to approximately 10 13atoms / cm 3 Up to 10 14 atoms / cm 3 The concentration range. After application, the photoresist can be removed via an acceptable ashing process.

[0103] After implantation in the N-type region 50N and the P-type region 50P, annealing can be performed to repair implantation damage and activate the implanted P-type and / or N-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can eliminate the need for implantation, although in-situ and implantation doping can be used together.

[0104] exist Figure 5A and Figure 5B In this process, a dummy gate is formed on the nanostructure stack 55 and the fin 66 and along the sidewalls. To form the dummy gate, a dummy dielectric layer is first formed on the fin 66 and / or the nanostructure stack 55. The dummy dielectric layer may be, for example, silicon oxide, silicon nitride (SiN), combinations thereof, or other similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a masking layer is formed on the dummy gate layer. The dummy gate layer may be deposited on the dummy dielectric layer and then planarized by a process such as chemical mechanical polishing. A masking layer may be deposited on the dummy gate layer. The dummy gate layer may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The selected material can be deposited as a dummy gate layer using physical vapor deposition, chemical vapor deposition, sputtering deposition, or other similar methods. Other materials can be used to form the dummy gate layer, which have a high etch selectivity for etching the isolation region. The masking layer may include, for example, silicon nitride, silicon oxynitride (SiON), or other similar materials.

[0105] Subsequently, the mask layer can be patterned using acceptable lithography and etching techniques to form mask 78. The pattern of mask 78 can then be transferred onto the dummy gate layer and the dummy dielectric layer to form dummy gate 76 and dummy gate dielectric 70, respectively. The dummy gate 76 covers individual channel regions of the fin 66. The pattern of mask 78 can be used to physically separate adjacent dummy gates 76. The length direction of the dummy gate 76 may also be substantially perpendicular to the length direction of the individual fin 66. It should be noted that the dummy gate dielectric 70 is illustrated only over the fin 66 and the nanostructure stack 55 for illustrative purposes. In some embodiments, the dummy gate dielectric 70 may be deposited over the shallow trench isolation region 68, such that the dummy gate dielectric 70 extends between the dummy gate 76 and the shallow trench isolation region 68.

[0106] exist Figure 6A and Figure 6B In this process, gate spacers 81 are formed on the nanostructure stack 55 and the shallow trench isolation region 68, and on the exposed sidewalls of the mask 78 (if present), the dummy gate 76, and the dummy gate dielectric 70. The gate spacers 81 can be formed by conformally forming and subsequently etching one or more dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride (SiOCN), or other similar materials, which can be formed by chemical vapor deposition, atomic layer deposition, or other similar deposition processes. Other insulating materials formed by acceptable processes may be used. Any acceptable etching process (such as dry etching, wet etching, other similar methods, or combinations thereof) can be performed to pattern the dielectric material. The etching may be anisotropic. After etching, the dielectric material has a portion remaining on the sidewalls of the dummy gate 76 (thus forming the gate spacers 81). As detailed later, after etching, the dielectric material has portions remaining on the sidewalls of the fins 66 and / or the nanostructure stack 55 (thus forming fin spacers 83, see reference). Figure 7C After etching, the fin spacers 83 and / or the gate spacers 81 may have straight sidewalls (as shown) or curved sidewalls (not shown separately).

[0107] Furthermore, a lightly doped source / drain (LDD) region can be implanted (not shown separately). The lightly doped source / drain region implantation can be performed before the formation of the gate spacer 81. In embodiments with different element types, similar to the implantation of the well described above, a mask (e.g., photoresist) can be formed on the N-type region 50N, exposing the P-type region 50P, and an appropriate type (e.g., P-type) impurity can be implanted into the fin 66 and nanostructure stack 55 exposed in the P-type region 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed on the P-type region 50P, exposing the N-type region 50N, and an appropriate type (e.g., N-type) impurity can be implanted into the fin 66 and nanostructure stack 55 exposed in the N-type region 50N. The mask can then be removed. The N-type impurity can be any N-type impurity discussed previously, and the P-type impurity can be any P-type impurity discussed previously. The lightly doped source / drain region can have 10 15 atoms / cm 3 Up to 10 19 atoms / cm 3 The range of impurity concentrations. Annealing can be used to repair implantation damage and revitalize implanted impurities.

[0108] It should be noted that the previously disclosed process generally describes the formation of spacers and lightly doped source / drain regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, and / or other similar methods can be employed. Furthermore, different structures and steps can be used to form N-type and P-type devices.

[0109] exist Figures 7A to 7C In some embodiments, a first groove 86 is formed in the fin 66, the nanostructure stack 55, and the substrate 50. Subsequently, an epitaxial source / drain region is formed in the first groove 86. The first groove 86 can extend through the first and second nanostructures and into the substrate 50. Figure 7C As shown, the top surface of the shallow trench isolation region 68 may be flush with the bottom surface of the first groove 86. In other embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is disposed above or below the top surface of the shallow trench isolation region 68. The first groove 86 may be formed by etching the fin 66, the nanostructure stack 55, and the substrate 50 using an anisotropic etching process (such as reactive ion etching, neutral particle beam etching, or other similar methods). During the etching process for forming the first groove 86, the gate spacer 81 and the mask 78 partially shield the fin 66, the nanostructure stack 55, and the substrate 50. Each layer of the nanostructure stack 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first groove 86 after it has reached a desired depth.

[0110] exist Figure 8A , Figure 8B ,and Figure 9 In this embodiment, the first nanostructure is replaced with sacrificial materials 71A, 71B, and 71C (also referred to as a disposable oxide interposer, DOI). Replacing the first nanostructure may include using a suitable etching process to remove the first nanostructure, such as an isotropic etching process through the first groove 86, as shown in Figures 8A and 8B. The etching process may be selective in its application to the material of the first nanostructure and may remove the first nanostructure without significantly removing the second nanostructure or fin 66. In embodiments where the first nanostructure comprises, for example, silicon-germanium and the second nanostructure comprises, for example, silicon or silicon carbide, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or other similar chemicals may be used to remove the first nanostructure.

[0111] Subsequently, a sacrificial material 71 is deposited in the space where the first groove 86 and the first nanostructure are removed. The sacrificial material 71 can be deposited using a compliant deposition process (such as chemical vapor deposition, atomic layer deposition, or other similar methods). The sacrificial material 71 may include an insulating material (such as silicon oxide or other similar materials), which can be selectively etched by the second nanostructure. Figure 9 In this process, sacrificial material 71 can then be etched to form sacrificial material 71A, sacrificial material 71B, and sacrificial material 71C. The etching can be isotropic or anisotropic. For example, the sacrificial material layer can be etched using a wet etching process employing diluted hydrofluoric acid or other similar chemicals as etchants. In some embodiments, etching is performed until the sidewalls of sacrificial materials 71A, 71B, and 71C are etched through the sidewalls of the nanostructure.

[0112] Replacing the first nanostructure with sacrificial materials 71A, 71B, and 71C offers advantages. For example, in subsequent source / drain formation steps, one or more high-temperature processes can be performed to, for example, activate dopants in the source / drain regions. When the material of the first nanostructure (e.g., silicon-germanium) is exposed to high temperatures, germanium can become intermingled at the interface between the first and second nanostructures, increasing roughness. This manufacturing defect can degrade the performance of the resulting transistor device. For example, when germanium diffuses into the second nanostructure, germanium residue can remain in the channel region of the resulting transistor device, negatively impacting the performance of the channel region. By replacing the first nanostructure with an insulating material prior to high-temperature processes (e.g., source / drain annealing), manufacturing defects can be reduced, and device performance can be improved (e.g., enhanced current drive, reduced capacitance, and improved short-channel effect (SCE)).

[0113] exist Figures 10A to 10C In this process, portions of the sidewalls of sacrificial materials 71A, 71B, and 71C exposed by the first groove 86 are etched to form sidewall grooves 88A, 88B, and 88C in the N-type region 50N and the P-type region 50P. The sidewall grooves 88A, 88B, and 88C can be recessed or protruding.

[0114] Forming sidewall recesses 88A, 88B, and 88C allows at least some of the sacrificial materials 71A, 71B, and 71C to be etched separately, such that at least some of the recesses in the sidewalls of each layer in the nanostructure stack 55 can have different sizes. For example, sidewall recess 88C can be larger than sidewall recess 88A.

[0115] In some embodiments, to provide selective processing within the nanostructure stack 55, sidewall spacers 200 are formed along the sidewalls of the nanostructure stack 55. The sidewall spacers 200 may have a height exposing at least a portion of the sacrificial materials 71A, 71B, and 71C, allowing them to be etched, while the sidewall spacers 200 protect the remaining sacrificial materials 71A, 71B, and 71C from the effects of the etching process, such as... Figure 10A As shown.

[0116] Figure 10A The diagram illustrates the formation of sidewall spacers 200, which expose an upper (first) sacrificial material 71C in each of the N-type region 50N and the P-type region 50P. The sidewall spacers 200 may be composed of a dielectric material (such as an oxide, nitride, or oxynitride material). The dielectric material of the sidewall spacers 200 may differ from that of the sacrificial materials 71A, 71B, and 71C, such that the sacrificial materials 71A, 71B, and 71C have a high etch selectivity relative to the dielectric material of the sidewall spacers 200. In some examples, when the sacrificial materials 71A, 71B, and 71C are composed of oxides (such as silicon oxide), the sidewall spacers 200 may be composed of nitrides (such as silicon nitride). Other suitable materials may be used. For example, the sidewall spacers 200 may be composed of other dielectric materials (such as silicon oxynitride, silicon carbon boride (SiCB), aluminum oxide (Al2O3), other similar materials, or combinations thereof).

[0117] In some embodiments, techniques such as thermal oxidation or deposition, followed by etching, can be used to form the sidewall spacers 200. For example, the material for the sidewall spacers 200 can be deposited by chemical vapor deposition, atomic layer deposition, or other similar methods. The material that can initially form the sidewall spacers 200 is a film layer with a compliant thickness. The film layer deposited for the sidewall spacers 200 can then be etched using a suitable etching process (such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), or other similar methods). In one example, the anisotropic nature of the etching process removes the horizontal portion of the film layer, providing the sidewall spacers 200. Furthermore, the anisotropic nature of the etching process leaves the remaining vertical portion of the sidewall spacers 200 abutting the sidewalls of the nanostructure stack 55.

[0118] Figure 10A The etching process used to define the geometry of the sidewall spacer 200 continuously and vertically etches the upper surface of the sidewall spacer 200 to expose the sidewall surface of the first (upper) sacrificial material 71C. Figure 10AThe upper surface of the sidewall spacer 200 is etched to provide a height sufficient to protect the second (middle) sacrificial material 71B and the third (lower) sacrificial material 71A, while exposing the first (upper) sacrificial material 71C. The height of the sidewall spacer 200 can be etched to the appropriate level using timed anisotropic etching.

[0119] Figure 10A Also illustrated is that after the sidewall spacers 200 are formed (their height is etched to expose the first (upper) sacrificial material 71C), an etching process can be applied to etch the sidewalls of the first (upper) sacrificial material 71C laterally. This lateral etching process forms a first (upper) sidewall groove 88C in the sidewalls of the first (upper) sacrificial material 71C.

[0120] In some embodiments, isotropic etching processes (such as wet etching or other similar methods) can be used to etch the sidewalls of the first (upper) sacrificial material 71C. An etchant selective for removing the first (upper) sacrificial material 71C is applied such that the second nanostructure 54C and the substrate 50 remain relatively unetched.

[0121] Figure 10B The sidewall spacers 200 are illustrated to expose a second portion, such as a second (middle) sacrificial material 71B, of sacrificial materials 71A, 71B, and 71C. The height of the sidewall spacers 200 can be etched using an anisotropic etching process (such as reactive ion etching). In some embodiments, the height of the sidewall spacers 200 is etched to expose the middle portion of the film within the nanostructure stack 55. Figure 10B The upper surface of the sidewall spacer 200 is etched to provide a height sufficient to protect the third (lower) sacrificial material 71A, while exposing the first (upper) sacrificial material 71C and the second (middle) sacrificial material 71B. The height of the sidewall spacer 200 can be etched to the appropriate level using timed anisotropic etching.

[0122] Figure 10BThe second lateral etching further illustrates the second portion of sacrificial materials 71A, 71B, and 71C. For example, as the height of the sidewall spacer 200 is further etched, the exposed sacrificial materials may include a first (upper) sacrificial material 71C and a second (middle) sacrificial material 71B. The second lateral etching is an initial etching performed on the newly exposed sidewalls of the second (middle) sacrificial material 71B. The second lateral etching forms a second (middle) sidewall groove 88B in the sidewall of the second (middle) sacrificial material 71B. However, during the second lateral etching process step, the first (upper) sacrificial material 71C is also exposed, so the sidewall of the first (upper) sacrificial material 71C also receives a second dose of etchant. This provides that the first (upper) sidewall groove 88C is further extended into the sidewall of the first (upper) sacrificial material 71C.

[0123] In some embodiments, isotropic etching processes (such as wet etching or other similar methods) can be used to etch the sidewalls of the first (upper) sacrificial material 71C and the second (middle) sacrificial material 71B. An etchant selectively targeting the removal of the first (upper) sacrificial material 71C and the second (middle) sacrificial material 71B is applied such that the second nanostructure 54C and the substrate 50 remain relatively unetched.

[0124] In the illustrated embodiment, after the second lateral etching, the depth to which the first (upper) sidewall groove 88C penetrates into the remaining portion of the first (upper) sacrificial material 71C is greater than the depth to which the second (middle) sidewall groove 88B penetrates into the remaining portion of the second (middle) sacrificial material 71B. In another embodiment (described later), after the second lateral etching, the depth to which the first (upper) sidewall groove 88C penetrates into the remaining portion of the first (upper) sacrificial material 71C is equal to the depth to which the second (middle) sidewall groove 88B penetrates into the remaining portion of the second (middle) sacrificial material 71B.

[0125] Figure 10C The sidewall spacers 200 are depicted to expose a third portion of the sacrificial material, such as a third (lower) sacrificial material 71A. The height of the sidewall spacers 200 can be etched using an anisotropic etching process (such as reactive ion etching). In some embodiments, the height of the sidewall spacers 200 is etched to expose the bottom of the film within the nanostructure stack 55. Figure 10C The sidewall spacer 200 is shown to be completely removed. With the sidewall spacer 200 removed, the sidewalls of each of the sacrificial materials 71A, 71B, and 71C are exposed. The sidewall spacer 200 may not be completely removed. In some embodiments, a portion of the sidewall spacer 200 may be retained.

[0126] Figure 10CThe third portion of the third lateral etched disposable film layer is further illustrated. For example, due to the removal or etching of the sidewall spacers 200, the exposed sacrificial materials include a first (upper) sacrificial material 71C, a second (middle) sacrificial material 71B, and a third (lower) sacrificial material 71A. The third lateral etch is an initial etching of the sidewalls of the newly exposed third (lower) sacrificial material 71A. The third lateral etch forms a third (lower) sidewall groove 88A in the sidewalls of the third (lower) sacrificial material 71A. However, during the third lateral etch step, the first (upper) sacrificial material 71C and the second (middle) sacrificial material 71B are also exposed. This provides that the first (upper) sacrificial material 71C is etched in three different etch processes. The second (middle) sacrificial material 71B is exposed in the second etch process. Additional etch sleeves are used for the sidewalls of the first (upper) sacrificial material 71C and the second (middle) sacrificial material 71B. This provides a first (upper) sidewall groove 88C and a second (middle) sidewall groove 88B that further extend into the sidewalls of the first (upper) sacrificial material 71C and the second (middle) sacrificial material 71B.

[0127] In some embodiments, isotropic etching processes (such as wet etching or other similar methods) can be used to etch the sidewalls of the first (upper) sacrificial material 71C, the second (middle) sacrificial material 71B, and the third (lower) sacrificial material 71A. An etchant selectively targeting the removal of the first (upper) sacrificial material 71C, the second (middle) sacrificial material 71B, and the third (lower) sacrificial material 71A is applied such that the second nanostructure 54C and the substrate 50 remain relatively unetched.

[0128] In the illustrated embodiment, after the third lateral etching, the depth of the first (upper) sidewall groove 88C is greater than the depth of the first (upper) sidewall groove 88C after the second lateral etching. The depth of the first (upper) sidewall groove 88C is greater than the depth of the second (middle) sidewall groove 88B. Similar to the first (upper) sidewall groove 88C, after the third lateral etching, the depth of the second (middle) sidewall groove 88B is greater than the depth of the second (middle) sidewall groove 88B after the second lateral etching. After the third lateral etching, the depth of the second (middle) sidewall groove 88B entering the remaining portion of the second (middle) sacrificial material 71B is greater than the depth of the third (lower) sidewall groove 88A entering the remaining portion of the third (lower) sacrificial material 71A. In another embodiment (described later), after the third transverse etching, the depth to which the second (middle) sidewall groove 88B enters the remaining portion of the second (middle) sacrificial material 71B is equal to the depth to which the third (lower) sidewall groove 88A enters the remaining portion of the third (lower) sacrificial material 71A.

[0129] It should be noted that, in Figures 10A to 10CThe example shown is merely one example of the present invention and is not intended to limit the embodiments of the present invention to this example only. For example, the number of disposable membrane layers may be more or less than this example. Figures 10A to 10C The number of disposable film layers in a specific example shown. Furthermore, the number of grooves forming openings in the sidewalls of the disposable film layer and the number of lateral etching steps can be increased and / or decreased.

[0130] exist Figure 11A and Figure 11B In the process, inner spacers 91A, 91B, and 91C are formed in the sidewall grooves 88A, 88B, and 88C in the sidewalls of sacrificial materials 71A, 71B, and 71C. This allows for the formation of inner spacers 91A, 91B, and 91C. Figure 10C Inner spacer layers (not shown separately) are deposited on the structures shown (e.g., in the first recess 86, sidewall recess 88A, sidewall recess 88B, and sidewall recess 88C) to form inner spacers 91A, 91B, and 91C. Inner spacers 91A, 91B, and 91C act as isolation components between subsequently formed source / drain regions and subsequently formed gate structures. As will be detailed below, source / drain regions are formed in the first recess 86, and the remaining portions of sacrificial materials 71A, 71B, and 71C are replaced with corresponding gate structures.

[0131] The inner spacer layer can be deposited using compliant deposition processes (such as chemical vapor deposition, atomic layer deposition, or other similar methods). The inner spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material (such as a low-k material with a dielectric constant less than about 3.5) can be used. The inner spacer layer can then be anisotropically etched to form inner spacers 91A, 91B, and 91C. The inner spacer layer can be etched using anisotropic etching processes (such as reactive ion etching, neutral particle beam etching, or other similar methods).

[0132] Inner spacers 91A, 91B, and 91C are vertically spaced adjacent to the second nanostructures 54A, 54B, and 54C. The first (upper) inner spacer 91C is located near the upper surface of the nanostructure stack 55 and its width is greater than that of the second (middle) inner spacer 91B. The third (lower) inner spacer 91A is located near the base surface of the nanostructure stack 55 and its width is smaller than that of the second (middle) inner spacer 91B.

[0133] The formation of the gate structure (including a metal gate electrode) can create damage paths across inner spacers 91A, 91B, and 91C. The damage path can be an opening and / or a metal trace extending across inner spacers 91A, 91B, and 91C. In some embodiments, the metal trace extending through the damage path can provide a bridge between the gate electrode and the source / drain regions, which can result in an electrical short circuit. In some examples, an opening in the damage path can allow etchant used during the gate replacement process to reach the epitaxial material of the source / drain regions, which can adversely damage the epitaxial material.

[0134] In reference Figures 10A to 10C , Figure 11A ,and Figure 11B In the described embodiment, the first (upper) inner spacer 91C present at the top of the stack has the greatest width because it is formed in the first (upper) sidewall recess 88C of the first (upper) sacrificial material 71C. The first (upper) sidewall recess 88C has the greatest depth because it is exposed to the most lateral etching steps. The greater the width of the inner spacers 91A, 91B, and 91C, the stronger the protection against damage paths and their negative effects. For example, the upper part of the stack may be the part of the component most affected by damage paths. Therefore, the first (upper) inner spacer 91C formed in its recess has the greatest width, thus providing the greatest protection against damage paths compared to the inner spacers 91B and 91A formed in the lower part of the stack.

[0135] However, as the widths of the inner spacers 91A, 91B, and 91C increase, the width of the gate electrode decreases. A narrower gate electrode results in a higher resistance. Increased resistance degrades device performance. The third (lower) inner spacer 91A has the smallest width, providing a wider gate electrode portion with lower resistance than the portion of the gate electrode adjacent to the wider first (upper) inner spacer 91C. The methods and structures described herein can adjust the widths of the inner spacers and the gate electrode to provide protection against damage paths in the upper part of the stack and minimize the resistance of the gate electrode in the lower part of the stack.

[0136] exist Figures 12A-12D In this process, an epitaxial source / drain region 192 is formed in the first groove 86. In some embodiments, the epitaxial source / drain region 192 can apply stress to the nanostructure stack 55 in the N-type region 50N and / or the P-type region 50P, thereby improving performance. Figure 12AAs shown, an epitaxial source / drain region 192 is formed in the first groove 86, such that each dummy gate 76 is disposed between adjacent epitaxial source / drain regions 192. In some embodiments, gate spacers 81 are used to separate the epitaxial source / drain regions 192 from the dummy gates 76, while inner spacers 91A, 91B, and 91C are used to separate the epitaxial source / drain regions 192 from the sacrificial materials 71A, 71B, and 71C to an appropriate lateral spacing so that the epitaxial source / drain regions 192 are not electrically short-circuited with the gate formed by the subsequently obtained nanostructured field-effect transistor.

[0137] An epitaxial source / drain region 192 in an N-type region 50N (e.g., an N-type metal-oxide-semiconductor region) can be formed by shielding a P-type region 50P (e.g., a P-type metal-oxide-semiconductor region). The epitaxial source / drain region 192 is then epitaxially grown in a first recess 86 of the N-type region 50N. The epitaxial source / drain region 192 can comprise any acceptable material suitable for an N-type nanostructure field-effect transistor. For example, if the nanostructure stack 55 is silicon, the epitaxial source / drain region 192 can comprise a material that applies tensile strain to the nanostructure stack 55, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide (SiP), or other similar materials. The epitaxial source / drain region 192 may have a surface raised from the upper surface of the individual nanostructure stack 55 and may have facets.

[0138] An epitaxial source / drain region 192 in a P-type region 50P (e.g., a P-type metal-oxide-semiconductor region) can be formed by shielding an N-type region 50N (e.g., an N-type metal-oxide-semiconductor region). The epitaxial source / drain region 192 is then epitaxially grown in a first groove 86 of the P-type region 50P. The epitaxial source / drain region 192 can comprise any acceptable material suitable for a P-type nanostructure field-effect transistor. For example, if the nanostructure stack 55 is silicon-germanium, the epitaxial source / drain region 192 can comprise a material that applies compressive strain to the nanostructure stack 55, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin (GeSn), or other similar materials. The epitaxial source / drain region 192 may also have a surface raised from the upper surface of the individual nanostructure stack 55 and may have facets.

[0139] The source / drain regions can be formed by implanting doped epitaxial source / drain regions 192, nanostructure stacks 55, and / or a substrate 50, similar to the previously discussed process of forming lightly doped source / drain regions followed by annealing. The source / drain regions may have a density between approximately 1 × 10⁻⁶. 19 atoms / cm 3 and 1×10 21 atoms / cm3 The impurity concentrations between these values. The N-type and / or P-type impurities in the source / drain regions can be any of the impurities previously discussed. In some embodiments, the epitaxial source / drain regions 192 can be doped in situ during growth.

[0140] The result of using an epitaxial process to form epitaxial source / drain regions 192 in N-type region 50N and P-type region 50P is that the upper surface of the epitaxial source / drain regions 192 has facets that laterally extend outward beyond the sidewalls of the nanostructure stack 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 192 of the same nanostructure field-effect transistor to merge, such as Figure 12C As shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 192 remain separated, as shown. Figure 12D As shown. In Figures 12A-12D In the illustrated embodiment, a gate spacer 81 may be formed on the top surface of the shallow trench isolation region 68 to prevent epitaxial growth. In other embodiments, the gate spacer 81 may cover a portion of the sidewalls of the nanostructure stack 55 to further prevent epitaxial growth. In other embodiments, the spacer etching used to form the gate spacer 81 may be adjusted to remove spacer material, such that the epitaxial growth region extends to the surface of the shallow trench isolation region 68.

[0141] The epitaxial source / drain region 192 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 192 may include a first semiconductor material layer 192A, a second semiconductor material layer 192B, and a third semiconductor material layer 192C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 192. Each of the first semiconductor material layer 192A, the second semiconductor material layer 192B, and the third semiconductor material layer 192C may be formed of a different semiconductor material and may be doped to different doping concentrations. In some embodiments, the doping concentration of the first semiconductor material layer 192A may be lower than the doping concentration of the second semiconductor material layer 192B and higher than the doping concentration of the third semiconductor material layer 192C. In embodiments where the epitaxial source / drain region 192 includes three semiconductor material layers, the first semiconductor material layer 192A may be deposited, the second semiconductor material layer 192B may be deposited on the first semiconductor material layer 192A, and the third semiconductor material layer 192C may be deposited on the second semiconductor material layer 192B.

[0142] exist Figures 13A-13C In Figures 12A-12DA first interlayer dielectric (ILD) 96 is deposited on the structure shown. The first interlayer dielectric 96 can be formed of a dielectric material and can be deposited by any suitable method, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), or flow-through chemical vapor deposition. The dielectric material may include phosphosilicate glass (PSG), boron-doped silicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or other similar materials. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first interlayer dielectric 96 and the epitaxial source / drain region 192, the mask 78, and the gate spacer 81. The contact etch stop layer 94 may include a dielectric material (such as silicon nitride, silicon oxide, silicon oxynitride, or other similar materials) having an etch rate different from that of the material of the upper first interlayer dielectric 96.

[0143] exist Figure 14A and Figure 14B In this process, a planarization process (such as chemical mechanical polishing) can be performed to make the top surface of the first interlayer dielectric 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and portions of the gate spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the gate spacer 81, and the first interlayer dielectric 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first interlayer dielectric 96. In some embodiments, the mask 78 may be left, in which case the planarization makes the top surface of the first interlayer dielectric 96 flush with the top surfaces of the mask 78 and the gate spacer 81.

[0144] exist Figure 15A and Figure 15BIn one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form a second recess 98. A portion of the dummy gate dielectric 70 in the second recess 98 may also be removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 70 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas, which selectively etches the dummy gate 76 at a rate higher than the rate at which the first interlayer dielectric 96 or gate spacer 81 is etched. Each second recess 98 exposes and / or covers a portion of a nanostructure stack 55, which serves as a channel region for a subsequently completed nanostructured field-effect transistor. The portion of the nanostructure stack 55 serving as the channel region is disposed between adjacent epitaxial source / drain regions 192. During removal, the dummy gate dielectric 70 can be used as an etch stop layer when the dummy gate 76 is etched. The dummy gate dielectric 70 can then be removed after the dummy gate 76 has been removed.

[0145] exist Figure 16A and Figure 16B In this process, sacrificial materials 71A, 71B, and 71C are removed to extend the second groove 98. Sacrificial materials 71A, 71B, and 71C can be removed by an isotropic etching process (such as wet etching or other similar methods) using an etchant selective for removing sacrificial materials 71A, 71B, and 71C, while the second nanostructures 54A, 54B, and 54C remain relatively unetched compared to the sacrificial materials 71A, 71B, and 71C. In embodiments where sacrificial materials 71A, 71B, and 71C comprise, for example, silicon oxide, and the second nanostructures 54A, 54B, and 54C comprise, for example, silicon, silicon carbide, or other similar materials, sacrificial materials 71A, 71B, and 71C can be removed. The sacrificial material 71 can be completely removed, or residue of the sacrificial material 71 can be left on the sidewall of the inner spacer in the second groove 98 (see, for example) Figure 17C ).

[0146] In some embodiments, the shallow trench isolation region 68 can be etched while removing the sacrificial material 71, but the total wear of the shallow trench isolation region 68 can be reduced while removing the sacrificial material 71 by controlling the etching parameters (e.g., time). In other embodiments, the shallow trench isolation region 68 may include a hard mask (not shown separately) on the top surface to protect the underlying shallow trench isolation region 68 from etching while patterning and removing the sacrificial material 71. In this embodiment, the hard mask may include, for example, a nitride.

[0147] exist Figure 17A and Figure 17BIn this process, a gate dielectric layer 100 and a gate electrode 102 are formed as replacement gates. The gate dielectric layer 100 and the gate electrode 102 provide a functional gate structure. The gate dielectric layer 100 is compliantly deposited in the second trench 98. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructures 54A, 54B, and 54C. The gate dielectric layer 100 can also be deposited on the top surface of the first interlayer dielectric 96, the contact etch stop layer 94, the gate spacer 81, and the very shallow trench isolation region 68.

[0148] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, other similar materials, or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer on the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high dielectric constant material, and in this embodiment, the gate dielectric layer 100 may have a dielectric constant greater than about 7.0, and may include metal oxides, or silicates of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), manganese (Mn), barium (Ba), titanium (Ti), lead (Pb), or combinations thereof. The structures of the gate dielectric layer 100 in the N-type region 50N and the P-type region 50P may be the same or different. The gate dielectric layer 100 may be formed by molecular beam deposition (MBD), atomic layer deposition, plasma-assisted chemical vapor deposition, or other similar methods.

[0149] A gate electrode 102 is deposited on the gate dielectric layer 100, filling the remaining portion of the second trench 98. The gate electrode 102 may include a metallic material such as titanium nitride (TiN), titanium oxide (TiO2), tantalum nitride (TaN), tantalum carbide (TaC), cobalt (Co), ruthenium (Ru), aluminum, tungsten (W), combinations thereof, or multiple layers thereof. For example, although in Figure 17A and Figure 17B The diagram illustrates a single film layer of gate electrode 102, which may include any number of substrates, any number of work function adjustment layers, and filler material.

[0150] Gate dielectric layers 100 can be formed simultaneously in N-type region 50N and P-type region 50P, such that the gate dielectric layers 100 in each region are formed of the same material, and gate electrodes 102 can be formed simultaneously, such that the gate electrodes 102 in each region are formed of the same material. In some embodiments, the gate dielectric layers 100 in each region can be formed by different processes, such that the gate dielectric layers 100 in each region can be made of different materials and / or have different numbers of film layers, and / or the gate electrodes 102 in each region can be formed by different processes, such that the gate electrodes 102 can be made of different materials and / or have different numbers of film layers. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0151] After filling the second groove 98, a planarization process (such as chemical mechanical polishing) can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, which lies on the top surface of the first interlayer dielectric 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus form the replacement gate structure of the resulting nanostructured field-effect transistor. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as the "gate structure".

[0152] Reference Figure 17B The gate electrode 102 surrounds the nanostructure stack 55 (e.g., second nanostructures 54A, 54B, and 54C) and may be referred to as a gate-all-around (GAA) structure. The GAA structure has a pyramid geometry in the illustrated cross-section. The conductive material of the gate electrode 102 and the dielectric material of the gate dielectric layer 100 fill the space created by removing sacrificial materials 71A, 71B, and 71C. In some embodiments, because the width of the first (upper) inner spacer 91C is greater than the width of the second (middle) inner spacer 91B, and the width of the second (middle) inner spacer 91B is greater than the width of the third (lower) inner spacer 91A, the space occupied by the conductive material of the gate electrode 102 increases from the upper portion of the nanostructure stack 55 to the base portion of the nanostructure stack 55. These spaces are filled with the conductive material of the gate electrode 102 to create a gate electrode 102 having a pyramid geometry, the pyramid geometry including a first width at the top surface of the gate structure within the nanostructure stack 55, which is smaller than a second width at the base of the gate structure within the nanostructure stack 55.

[0153] It should be noted that, Figure 17B The geometry of the portion of the gate electrode 102 within the nanostructure stack 55 is merely one example of a gate structure that can be provided by the method described herein.

[0154] Figure 17CDraw Figure 17B Detailed schematic diagrams of various components, including epitaxial source / drain regions 192, gate dielectric layer 100, gate electrode 102, second nanostructure 54, and internal spacers 91. Figure 17C In some embodiments shown, residue 72 of the sacrificial material 71 may remain on the inner spacer 91, such as between the inner spacer 91 and the gate dielectric layer 100 / gate electrode 102. For example, the sacrificial material 71 may not be completely removed, and the gate dielectric layer 100 may be formed on the remaining sacrificial material 71. Because the sacrificial material 71 is an insulating material (e.g., silicon oxide), the remaining residue 72 may not significantly impact the electrical performance of the resulting device. Figure 17C Description only Figure 17B One of the inner spacers 91. However, Figure 17C The inner spacer 91 shown can represent Figure 17B Each of the inner spacers 91A, 91B, and 91C shown.

[0155] Figures 21A to 21C The illustrations show some examples of how the widths of inner spacers 91A, 91B, and 91C can be adjusted to provide different gate length portions of the gate electrode 102 within the nanostructure stack 55. The width of the gate electrode 102 between the opposite sides of inner spacers 91A, 91B, and 91C constitutes the gate length portion. Figures 21A to 21C The inner spacers are not shown in the drawing, but can be referenced. Figure 17B Let's observe.

[0156] Figure 21A Drawing reference Figure 17B In the embodiment described above, the upper portion 102C of the gate electrode 102 exists between the first (upper) inner spacers 91C. The first (upper) inner spacers 91C have the maximum width. Therefore, the upper portion 102C of the gate electrode 102 has the narrowest gate length. The lower portion 102A of the gate electrode 102 exists between the third (lower) inner spacers 91A. The third (lower) inner spacers 91A have the narrowest width. Therefore, the lower portion 102A of the gate electrode 102 has the widest gate length. The middle portion 102B of the gate electrode 102 has a gate length between the upper portion 102C and the lower portion 102A. This is a pyramid geometry with a gradually changing pyramid width (e.g., a gradually changing gate length). The pyramid geometry is provided by separately etching each disposable film layer at least once in the process sequence for forming the inner spacers 91A, inner spacers 91B, and inner spacers 91C.

[0157] However, Figure 21B and Figure 21CThe illustration shows adjacent stacked film layers within a nanostructure stack 55 that can form gate electrodes 102, having the same gate length. The same gate length can be provided by exposing at least two sidewalls of the disposable spacers through etching the sidewall spacers and simultaneously etching them using the same etching process. Figure 21B The lower portion 102A and the middle portion 102B of the gate electrode 102 are illustrated. Both lower nanostructures have the same gate length, which is greater than the gate length of the upper portion 102C. Figure 21C The middle portion 102B and the upper portion 102C of the gate electrode 102 are shown to have the same gate length for the two upper nanostructures, which is smaller than the gate length of the lower portion 102A.

[0158] exist Figures 18A-18C In the process, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 above it) is etched to form a groove directly above the gate structure between the gate spacers 81. A gate mask 104, comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, or other similar materials), is filled into the groove, followed by a planarization process to remove excess dielectric material extending onto the first interlayer dielectric 96. The subsequently formed gate contacts (such as contact 114, see...) Figures 20A to 20C (Discussed below) Through the gate shield 104 to contact the top surface of the etched gate electrode 102.

[0159] like Figures 18A-18C Further illustration shows the deposition of a second interlayer dielectric 106 on the first interlayer dielectric 96 and the gate mask 104. In some embodiments, the second interlayer dielectric 106 is a fluid film layer formed by fluid chemical vapor deposition. In some embodiments, the second interlayer dielectric 106 is formed of a dielectric material (such as phosphosilicate glass, boron-doped silicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or other similar materials), and the second interlayer dielectric 106 can be deposited by any suitable method (such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or other similar methods).

[0160] exist Figures 19A-19CIn this process, the second interlayer dielectric 106, the first interlayer dielectric 96, the contact etch stop layer 94, and the gate mask 104 are etched to form a third groove 108 exposing the surface of the epitaxial source / drain region 192 and / or the gate structure. The third groove 108 can be formed by etching using anisotropic etching processes (such as reactive ion etching, neutral particle beam etching, or other similar methods). In some embodiments, a first etching process can be used to etch the third groove 108 through the second interlayer dielectric 106 and the first interlayer dielectric 96; a second etching process can be used to etch the third groove 108 through the gate mask 104; and then a third etching process can be used to etch the third groove 108 through the contact etch stop layer 94. A mask (such as photoresist) can be formed and patterned on the second interlayer dielectric 106 to shield a portion of the second interlayer dielectric 106 from the effects of the first and second etching processes. In some embodiments, the etching process may over-etch, so that the third groove 108 extends into the epitaxial source / drain region 192 and / or gate structure, and the bottom of the third groove 108 may be flush with the epitaxial source / drain region 192 and / or gate structure (e.g., at the same level, or with the same spacing as the substrate) or lower than the epitaxial source / drain region 192 and / or gate structure (e.g., closer to the substrate). Although Figure 19B The third groove 108 is illustrated to expose the epitaxial source / drain region 192 and gate structure in the same cross-section. In various embodiments, the epitaxial source / drain region 192 and gate structure can be exposed in different cross-sections, thereby reducing the risk of short circuits in subsequently formed contacts. After forming the third groove 108, a silicide region 110 is formed on the epitaxial source / drain region 192. In some embodiments, the silicide region or germanide region is first formed by depositing a metal (not shown) that can react with the semiconductor material (e.g., silicon, silicon-germanium, or germanium) of the underlying epitaxial source / drain region 192, such as nickel (Ni), cobalt, titanium, tantalum (Ta), platinum (Pt), tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof on the exposed portion of the epitaxial source / drain region 192, and then a thermal annealing process is performed to form the silicide region 110. Then, unreacted portions of the deposited metal are removed by, for example, an etching process. While the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanium region (e.g., a region comprising both silicide and germanide). In one embodiment, the silicide region 110 comprises titanium silicide (TiSi) and has a thickness ranging from about 2 nm to 10 nm.

[0161] Next, in Figures 20A to 20CIn the third groove 108, contacts 112 and 114 (also referred to as contact plugs) are formed. Contacts 112 and 114 may each include one or more film layers, such as barrier layers, diffusion layers, or filler materials. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to an underlying conductive component (e.g., the gate electrode 102 and / or silicide region 110 in the illustrated embodiment). Contact 114, electrically coupled to the gate electrode 102, may be referred to as a gate contact, while contact 112, electrically coupled to the silicide region 110, may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or other similar materials. The conductive material may be copper (Cu), copper alloys, silver (Ag), gold (Au), tungsten, cobalt, aluminum, nickel, or other similar materials. A planarization process (such as chemical mechanical polishing) can be performed to remove excess material from the surface of the second interlayer dielectric 106.

[0162] The embodiments can achieve several advantages. For example, the methods and structures provide multiple disposable film layers in a stack for forming nanostructured channels, which, when combined with selective etching, can create adjustable inner spacer profiles. Selective etching can control the profile of the disposable film layers layer by layer. In some embodiments, the adjustable inner spacer profile can amplify metal gate process extrusion and provide lower capacitance.

[0163] According to some embodiments of the present invention, a semiconductor device includes: a source / drain region; a first nanostructure adjacent to the source / drain region; a second nanostructure adjacent to the source / drain region, the second nanostructure being disposed on the first nanostructure; a third nanostructure adjacent to the source / drain region, the third nanostructure being disposed on the second nanostructure; and a gate structure surrounding the first nanostructure, the second nanostructure, and the third nanostructure, wherein a first portion of the gate structure is disposed between the first nanostructure and the second nanostructure, a second portion of the gate structure is disposed between the second nanostructure and the third nanostructure, and the length of the second portion of the gate structure is less than the length of the first portion of the gate structure.

[0164] In one embodiment, the semiconductor device further includes: a first inner spacer between the source / drain region and a first portion of the gate structure; and a second inner spacer between the source / drain region and a second portion of the gate structure. In one embodiment, the width of the second inner spacer is greater than the width of the first inner spacer. In one embodiment, the first and second inner spacers comprise the same dielectric material. In one embodiment, the gate structure includes: a gate dielectric; and a metal gate electrode on the gate dielectric. In one embodiment, the semiconductor device further includes: a fin, a third portion of the gate structure disposed between the first nanostructure and the fin, and the length of the third portion of the gate structure is greater than the length of the second portion of the gate structure.

[0165] According to some embodiments of the present invention, a semiconductor device includes: a source / drain region; a nanostructure adjacent to the source / drain region; a gate structure surrounding the nanostructure; a first inner spacer between the gate structure and the source / drain region, the first inner spacer having a first width; and a second inner spacer between the gate structure and the source / drain region, the second inner spacer having a second width greater than the first width, the first inner spacer and the second inner spacer being disposed on opposite sides of the nanostructure.

[0166] In one embodiment, the gate structure includes a metal gate electrode. In one embodiment, the metal gate electrode has a pyramid geometry. In one embodiment, the gate structure further includes a compliant gate dielectric layer. In one embodiment, the first inner spacer and the second inner spacer comprise the same dielectric material. In one embodiment, the gate structure has a first gate length and a second gate length, the first gate length being adjacent to the first inner spacer and the second gate length being adjacent to the second inner spacer, wherein the first gate length is greater than the second gate length.

[0167] According to some embodiments of the present invention, a method for forming a semiconductor device includes: forming a stack of at least a first set of semiconductor layers and a second set of semiconductor layers; replacing the first set of semiconductor layers with a plurality of disposable film layers; forming sidewall spacers along the sidewalls of the stack, wherein a first portion of the disposable film layer is exposed by the sidewall spacers; first lateral etching of the exposed first portion of the disposable film layer; recess etching of the sidewall spacers to expose a second portion of the disposable film layer; second lateral etching of the exposed second portion of the disposable film layer by the sidewall spacers; forming a plurality of inner spacers in a plurality of grooves, the grooves being formed by the first and second lateral etching of the disposable film layers; and replacing the remaining portion of the disposable film layer with a gate structure disposed on the second set of semiconductor layers.

[0168] In one embodiment, sidewall spacers along the stack sidewalls are removed before forming the gate structure. In one embodiment, the first set of semiconductor layers and the second set of semiconductor layers have different compositions. In one embodiment, the gate electrode of the gate structure has a pyramid geometry. In one embodiment, the gate electrode of the gate structure is narrower on a second surface of the stack than on a first surface of the stack, the second surface being relative to the first surface. In one embodiment, forming the inner spacers includes compliantly depositing a dielectric material followed by an etching process. In one embodiment, etching the sidewall spacers includes performing an anisotropic etching process, the anisotropic etching process etching the material of the sidewall spacers at a faster rate than etching the material of the disposable film layer. In one embodiment, the method of forming the semiconductor device further includes forming a plurality of source / drain regions on opposite sides of the stack.

[0169] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: One source / drain region; A first nanostructure is located adjacent to the source / drain region; A second nanostructure is disposed on the first nanostructure, adjacent to the source / drain region. A third nanostructure is disposed on top of the second nanostructure, adjacent to the source / drain region. as well as A gate structure is provided surrounding the first nanostructure, the second nanostructure, and the third nanostructure. A first portion of the gate structure is disposed between the first nanostructure and the second nanostructure, and a second portion of the gate structure is disposed between the second nanostructure and the third nanostructure. The length of the second portion of the gate structure is less than the length of the first portion of the gate structure.

2. The semiconductor device as claimed in claim 1, characterized in that, Including: A first inner spacer is located between the source / drain region and the first portion of the gate structure; as well as A second inner spacer is located between the source / drain region and the second portion of the gate structure.

3. The semiconductor device as claimed in claim 2, characterized in that, The width of the second inner spacer is greater than the width of the first inner spacer.

4. The semiconductor device as claimed in claim 1, characterized in that, The gate structure includes: A gate dielectric; and A metal gate electrode is disposed on the gate dielectric.

5. The semiconductor device as claimed in claim 1, characterized in that, Including: A fin, wherein a third portion of the gate structure is disposed between the first nanostructure and the fin, and the length of the third portion of the gate structure is greater than the length of the second portion of the gate structure.

6. A semiconductor device, characterized in that, include: One source / drain region; A nanostructure adjacent to the source / drain region; A gate structure surrounds the nanostructure; A first inner spacer is located between the gate structure and the source / drain region, the first inner spacer having a first width; as well as A second inner spacer is provided between the gate structure and the source / drain region. The second inner spacer has a second width that is greater than the first width. The first inner spacer and the second inner spacer are disposed on opposite sides of the nanostructure.

7. The semiconductor device as claimed in claim 6, characterized in that, The gate structure includes A metal gate electrode.

8. The semiconductor device as claimed in claim 7, characterized in that, The metal gate electrode has a pyramid geometry.

9. The semiconductor device as claimed in claim 7, characterized in that, The gate structure further includes a compliant gate dielectric layer.

10. The semiconductor device as claimed in claim 7, characterized in that, The gate structure has a first gate length and a second gate length, the first gate length being adjacent to the first inner spacer and the second gate length being adjacent to the second inner spacer, wherein the first gate length is greater than the second gate length.

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